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Merge changes I8e67a921,I0dc06072,I5e149063,I962cdfc7,I5c5d0444 into integration

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* changes:
  plat: ti: k3: board: Let explicitly map our SEC_SRAM_BASE to 0x0
  plat: ti: k3: board: Lets cast our macros
  plat: ti: k3: common: bl31_setup: Use BL31_SIZE instead of computing
  plat: ti: k3: platform_def.h: Define the correct number of max table entries
  plat: ti: k3: board: lite: Increase SRAM size to account for additional table
This commit is contained in:
Manish Pandey 2021-04-30 12:23:04 +02:00 • committed by TrustedFirmware Code Review
commit dd6efc9ea5
4 changed files with 38 additions and 12 deletions
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21
plat/ti/k3/board/generic/include/board_def.h
View file

@ -18,15 +18,26 @@
/*
* This RAM will be used for the bootloader including code, bss, and stacks.
* It may need to be increased if BL31 grows in size.
*
* The link addresses are determined by SEC_SRAM_BASE + offset.
* When ENABLE_PIE is set, the TF images can be loaded anywhere, so
* SEC_SRAM_BASE is really arbitrary.
*
* When ENABLE_PIE is unset, SEC_SRAM_BASE should be chosen so that
* it matches to the physical address where BL31 is loaded, that is,
* SEC_SRAM_BASE should be the base address of the RAM region.
*
* Lets make things explicit by mapping SRAM_BASE to 0x0 since ENABLE_PIE is
* defined as default for our platform.
*/
#define SEC_SRAM_BASE 0x70000000 /* Base of MSMC SRAM */
#define SEC_SRAM_SIZE 0x00020000 /* 128k */
#define SEC_SRAM_BASE UL(0x00000000) /* PIE remapped on fly */
#define SEC_SRAM_SIZE UL(0x00020000) /* 128k */
#define PLAT_MAX_OFF_STATE U(2)
#define PLAT_MAX_RET_STATE U(1)
#define PLAT_PROC_START_ID 32
#define PLAT_PROC_DEVICE_START_ID 202
#define PLAT_CLUSTER_DEVICE_START_ID 198
#define PLAT_PROC_START_ID U(32)
#define PLAT_PROC_DEVICE_START_ID U(202)
#define PLAT_CLUSTER_DEVICE_START_ID U(198)
#endif /* BOARD_DEF_H */

21
plat/ti/k3/board/lite/include/board_def.h
View file

@ -20,15 +20,26 @@
* It may need to be increased if BL31 grows in size.
* Current computation assumes data structures necessary for GIC and ARM for
* a single cluster of 4 processor.
*
* The link addresses are determined by SEC_SRAM_BASE + offset.
* When ENABLE_PIE is set, the TF images can be loaded anywhere, so
* SEC_SRAM_BASE is really arbitrary.
*
* When ENABLE_PIE is unset, SEC_SRAM_BASE should be chosen so that
* it matches to the physical address where BL31 is loaded, that is,
* SEC_SRAM_BASE should be the base address of the RAM region.
*
* Lets make things explicit by mapping SRAM_BASE to 0x0 since ENABLE_PIE is
* defined as default for our platform.
*/
#define SEC_SRAM_BASE 0x70000000 /* Base of SRAM */
#define SEC_SRAM_SIZE 0x0001a000 /* 104k */
#define SEC_SRAM_BASE UL(0x00000000) /* PIE remapped on fly */
#define SEC_SRAM_SIZE UL(0x0001c000) /* 112k */
#define PLAT_MAX_OFF_STATE U(2)
#define PLAT_MAX_RET_STATE U(1)
#define PLAT_PROC_START_ID 32
#define PLAT_PROC_DEVICE_START_ID 135
#define PLAT_CLUSTER_DEVICE_START_ID 134
#define PLAT_PROC_START_ID U(32)
#define PLAT_PROC_DEVICE_START_ID U(135)
#define PLAT_CLUSTER_DEVICE_START_ID U(134)
#endif /* BOARD_DEF_H */

2
plat/ti/k3/common/k3_bl31_setup.c
View file

@ -101,7 +101,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
void bl31_plat_arch_setup(void)
{
const mmap_region_t bl_regions[] = {
MAP_REGION_FLAT(BL31_START, BL31_END - BL31_START, MT_MEMORY | MT_RW | MT_SECURE),
MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE),
MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_CODE | MT_RO | MT_SECURE),
MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, MT_RO_DATA | MT_RO | MT_SECURE),
#if USE_COHERENT_MEM

6
plat/ti/k3/include/platform_def.h
View file

@ -60,7 +60,11 @@
* used, choose the smallest value needed to map the required virtual addresses
* for each BL stage.
*/
#define MAX_XLAT_TABLES 8
#if USE_COHERENT_MEM
#define MAX_XLAT_TABLES 10
#else
#define MAX_XLAT_TABLES 9
#endif
/*
* Defines the maximum number of regions that are allocated by the translation