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Rename Cortex-Ares to Neoverse N1

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Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
This commit is contained in:
John Tsichritzis 2019-02-19 13:49:06 +00:00
parent b04ea14b79
commit da6d75a0e7
10 changed files with 82 additions and 82 deletions
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26
include/lib/cpus/aarch64/neoverse_n1.h
View file

@ -1,30 +1,30 @@
/* /*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#ifndef CORTEX_ARES_H #ifndef NEOVERSE_N1_H
#define CORTEX_ARES_H #define NEOVERSE_N1_H
#include <lib/utils_def.h> #include <lib/utils_def.h>
/* Cortex-ARES MIDR for revision 0 */ /* Neoverse N1 MIDR for revision 0 */
#define CORTEX_ARES_MIDR U(0x410fd0c0) #define NEOVERSE_N1_MIDR U(0x410fd0c0)
/******************************************************************************* /*******************************************************************************
* CPU Extended Control register specific definitions. * CPU Extended Control register specific definitions.
******************************************************************************/ ******************************************************************************/
#define CORTEX_ARES_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_ARES_CPUECTLR_EL1 S3_0_C15_C1_4 #define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4
/* Definitions of register field mask in CORTEX_ARES_CPUPWRCTLR_EL1 */ /* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */
#define CORTEX_ARES_CORE_PWRDN_EN_MASK U(0x1) #define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1)
#define CORTEX_ARES_ACTLR_AMEN_BIT (U(1) << 4) #define NEOVERSE_N1_ACTLR_AMEN_BIT (U(1) << 4)
#define CORTEX_ARES_AMU_NR_COUNTERS U(5) #define NEOVERSE_N1_AMU_NR_COUNTERS U(5)
#define CORTEX_ARES_AMU_GROUP0_MASK U(0x1f) #define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f)
/* Instruction patching registers */ /* Instruction patching registers */
#define CPUPSELR_EL3 S3_6_C15_C8_0 #define CPUPSELR_EL3 S3_6_C15_C8_0
@ -32,4 +32,4 @@
#define CPUPOR_EL3 S3_6_C15_C8_2 #define CPUPOR_EL3 S3_6_C15_C8_2
#define CPUPMR_EL3 S3_6_C15_C8_3 #define CPUPMR_EL3 S3_6_C15_C8_3
#endif /* CORTEX_ARES_H */ #endif /* NEOVERSE_N1_H */

64
lib/cpus/aarch64/neoverse_n1.S
View file

@ -1,24 +1,24 @@
/* /*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#include <arch.h> #include <arch.h>
#include <asm_macros.S> #include <asm_macros.S>
#include <cortex_ares.h> #include <neoverse_n1.h>
#include <cpuamu.h> #include <cpuamu.h>
#include <cpu_macros.S> #include <cpu_macros.S>
/* -------------------------------------------------- /* --------------------------------------------------
* Errata Workaround for Cortex-Ares Errata * Errata Workaround for Neoverse N1 Errata
* This applies to revision r0p0 and r1p0 of Cortex-Ares. * This applies to revision r0p0 and r1p0 of Neoverse N1.
* Inputs: * Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu. * x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17 * Shall clobber: x0-x17
* -------------------------------------------------- * --------------------------------------------------
*/ */
func errata_ares_1043202_wa func errata_n1_1043202_wa
/* Compare x0 against revision r1p0 */ /* Compare x0 against revision r1p0 */
mov x17, x30 mov x17, x30
bl check_errata_1043202 bl check_errata_1043202
@ -36,7 +36,7 @@ func errata_ares_1043202_wa
isb isb
1: 1:
ret x17 ret x17
endfunc errata_ares_1043202_wa endfunc errata_n1_1043202_wa
func check_errata_1043202 func check_errata_1043202
/* Applies to r0p0 and r1p0 */ /* Applies to r0p0 and r1p0 */
@ -44,58 +44,58 @@ func check_errata_1043202
b cpu_rev_var_ls b cpu_rev_var_ls
endfunc check_errata_1043202 endfunc check_errata_1043202
func cortex_ares_reset_func func neoverse_n1_reset_func
mov x19, x30 mov x19, x30
bl cpu_get_rev_var bl cpu_get_rev_var
mov x18, x0 mov x18, x0
#if ERRATA_ARES_1043202 #if ERRATA_N1_1043202
mov x0, x18 mov x0, x18
bl errata_ares_1043202_wa bl errata_n1_1043202_wa
#endif #endif
#if ENABLE_AMU #if ENABLE_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3 mrs x0, actlr_el3
orr x0, x0, #CORTEX_ARES_ACTLR_AMEN_BIT orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
msr actlr_el3, x0 msr actlr_el3, x0
isb isb
/* Make sure accesses from EL0/EL1 are not trapped to EL2 */ /* Make sure accesses from EL0/EL1 are not trapped to EL2 */
mrs x0, actlr_el2 mrs x0, actlr_el2
orr x0, x0, #CORTEX_ARES_ACTLR_AMEN_BIT orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
msr actlr_el2, x0 msr actlr_el2, x0
isb isb
/* Enable group0 counters */ /* Enable group0 counters */
mov x0, #CORTEX_ARES_AMU_GROUP0_MASK mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK
msr CPUAMCNTENSET_EL0, x0 msr CPUAMCNTENSET_EL0, x0
isb isb
#endif #endif
ret x19 ret x19
endfunc cortex_ares_reset_func endfunc neoverse_n1_reset_func
/* --------------------------------------------- /* ---------------------------------------------
* HW will do the cache maintenance while powering down * HW will do the cache maintenance while powering down
* --------------------------------------------- * ---------------------------------------------
*/ */
func cortex_ares_core_pwr_dwn func neoverse_n1_core_pwr_dwn
/* --------------------------------------------- /* ---------------------------------------------
* Enable CPU power down bit in power control register * Enable CPU power down bit in power control register
* --------------------------------------------- * ---------------------------------------------
*/ */
mrs x0, CORTEX_ARES_CPUPWRCTLR_EL1 mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_ARES_CORE_PWRDN_EN_MASK orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK
msr CORTEX_ARES_CPUPWRCTLR_EL1, x0 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0
isb isb
ret ret
endfunc cortex_ares_core_pwr_dwn endfunc neoverse_n1_core_pwr_dwn
#if REPORT_ERRATA #if REPORT_ERRATA
/* /*
* Errata printing function for Cortex-Ares. Must follow AAPCS. * Errata printing function for Neoverse N1. Must follow AAPCS.
*/ */
func cortex_ares_errata_report func neoverse_n1_errata_report
stp x8, x30, [sp, #-16]! stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var bl cpu_get_rev_var
@ -105,15 +105,15 @@ func cortex_ares_errata_report
* Report all errata. The revision-variant information is passed to * Report all errata. The revision-variant information is passed to
* checking functions of each errata. * checking functions of each errata.
*/ */
report_errata ERRATA_ARES_1043202, cortex_ares, 1043202 report_errata ERRATA_N1_1043202, neoverse_n1, 1043202
ldp x8, x30, [sp], #16 ldp x8, x30, [sp], #16
ret ret
endfunc cortex_ares_errata_report endfunc neoverse_n1_errata_report
#endif #endif
/* --------------------------------------------- /* ---------------------------------------------
* This function provides cortex_ares specific * This function provides neoverse_n1 specific
* register information for crash reporting. * register information for crash reporting.
* It needs to return with x6 pointing to * It needs to return with x6 pointing to
* a list of register names in ascii and * a list of register names in ascii and
@ -121,16 +121,16 @@ endfunc cortex_ares_errata_report
* reported. * reported.
* --------------------------------------------- * ---------------------------------------------
*/ */
.section .rodata.cortex_ares_regs, "aS" .section .rodata.neoverse_n1_regs, "aS"
cortex_ares_regs: /* The ascii list of register names to be reported */ neoverse_n1_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", "" .asciz "cpuectlr_el1", ""
func cortex_ares_cpu_reg_dump func neoverse_n1_cpu_reg_dump
adr x6, cortex_ares_regs adr x6, neoverse_n1_regs
mrs x8, CORTEX_ARES_CPUECTLR_EL1 mrs x8, NEOVERSE_N1_CPUECTLR_EL1
ret ret
endfunc cortex_ares_cpu_reg_dump endfunc neoverse_n1_cpu_reg_dump
declare_cpu_ops cortex_ares, CORTEX_ARES_MIDR, \ declare_cpu_ops neoverse_n1, NEOVERSE_N1_MIDR, \
cortex_ares_reset_func, \ neoverse_n1_reset_func, \
cortex_ares_core_pwr_dwn neoverse_n1_core_pwr_dwn

20
lib/cpus/aarch64/neoverse_n1_pubsub.c
View file

@ -1,28 +1,28 @@
/* /*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#include <cortex_ares.h> #include <neoverse_n1.h>
#include <cpuamu.h> #include <cpuamu.h>
#include <lib/el3_runtime/pubsub_events.h> #include <lib/el3_runtime/pubsub_events.h>
static void *cortex_ares_context_save(const void *arg) static void *neoverse_n1_context_save(const void *arg)
{ {
if (midr_match(CORTEX_ARES_MIDR) != 0) if (midr_match(NEOVERSE_N1_MIDR) != 0)
cpuamu_context_save(CORTEX_ARES_AMU_NR_COUNTERS); cpuamu_context_save(NEOVERSE_N1_AMU_NR_COUNTERS);
return (void *)0; return (void *)0;
} }
static void *cortex_ares_context_restore(const void *arg) static void *neoverse_n1_context_restore(const void *arg)
{ {
if (midr_match(CORTEX_ARES_MIDR) != 0) if (midr_match(NEOVERSE_N1_MIDR) != 0)
cpuamu_context_restore(CORTEX_ARES_AMU_NR_COUNTERS); cpuamu_context_restore(NEOVERSE_N1_AMU_NR_COUNTERS);
return (void *)0; return (void *)0;
} }
SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_start, cortex_ares_context_save); SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_start, neoverse_n1_context_save);
SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_finish, cortex_ares_context_restore); SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_finish, neoverse_n1_context_restore);

12
lib/cpus/cpu-ops.mk
View file

@ -1,5 +1,5 @@
# #
# Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. # Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
# #
# SPDX-License-Identifier: BSD-3-Clause # SPDX-License-Identifier: BSD-3-Clause
# #
@ -120,8 +120,8 @@ ERRATA_A57_859972 ?=0
ERRATA_A72_859971 ?=0 ERRATA_A72_859971 ?=0
# Flag to apply T32 CLREX workaround during reset. This erratum applies # Flag to apply T32 CLREX workaround during reset. This erratum applies
# only to r0p0 and r1p0 of the Ares cpu. # only to r0p0 and r1p0 of the Neoverse N1 cpu.
ERRATA_ARES_1043202 ?=1 ERRATA_N1_1043202 ?=1
# Flag to apply DSU erratum 936184. This erratum applies to DSUs containing # Flag to apply DSU erratum 936184. This erratum applies to DSUs containing
# the ACP interface and revision < r2p0. Applying the workaround results in # the ACP interface and revision < r2p0. Applying the workaround results in
@ -188,9 +188,9 @@ $(eval $(call add_define,ERRATA_A57_859972))
$(eval $(call assert_boolean,ERRATA_A72_859971)) $(eval $(call assert_boolean,ERRATA_A72_859971))
$(eval $(call add_define,ERRATA_A72_859971)) $(eval $(call add_define,ERRATA_A72_859971))
# Process ERRATA_ARES_1043202 flag # Process ERRATA_N1_1043202 flag
$(eval $(call assert_boolean,ERRATA_ARES_1043202)) $(eval $(call assert_boolean,ERRATA_N1_1043202))
$(eval $(call add_define,ERRATA_ARES_1043202)) $(eval $(call add_define,ERRATA_N1_1043202))
# Process ERRATA_DSU_936184 flag # Process ERRATA_DSU_936184 flag
$(eval $(call assert_boolean,ERRATA_DSU_936184)) $(eval $(call assert_boolean,ERRATA_DSU_936184))

4
plat/arm/board/fvp/platform.mk
View file

@ -103,7 +103,7 @@ FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
lib/cpus/aarch64/cortex_a73.S \ lib/cpus/aarch64/cortex_a73.S \
lib/cpus/aarch64/cortex_a75.S \ lib/cpus/aarch64/cortex_a75.S \
lib/cpus/aarch64/cortex_a76.S \ lib/cpus/aarch64/cortex_a76.S \
lib/cpus/aarch64/cortex_ares.S \ lib/cpus/aarch64/neoverse_n1.S \
lib/cpus/aarch64/cortex_deimos.S lib/cpus/aarch64/cortex_deimos.S
else else
FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S
@ -214,7 +214,7 @@ endif
ifeq (${ENABLE_AMU},1) ifeq (${ENABLE_AMU},1)
BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \
lib/cpus/aarch64/cortex_ares_pubsub.c \ lib/cpus/aarch64/neoverse_n1_pubsub.c \
lib/cpus/aarch64/cpuamu.c \ lib/cpus/aarch64/cpuamu.c \
lib/cpus/aarch64/cpuamu_helpers.S lib/cpus/aarch64/cpuamu_helpers.S
endif endif

14
plat/arm/board/n1sdp/aarch64/n1sdp_helper.S
View file

@ -1,12 +1,12 @@
/* /*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#include <arch.h> #include <arch.h>
#include <asm_macros.S> #include <asm_macros.S>
#include <cortex_ares.h> #include <neoverse_n1.h>
#include <cpu_macros.S> #include <cpu_macros.S>
#include <platform_def.h> #include <platform_def.h>
@ -58,17 +58,17 @@ endfunc plat_arm_calc_core_pos
*/ */
func plat_reset_handler func plat_reset_handler
jump_if_cpu_midr CORTEX_ARES_MIDR, ARES jump_if_cpu_midr NEOVERSE_N1_MIDR, N1
ret ret
/* ----------------------------------------------------- /* -----------------------------------------------------
* Disable CPU power down bit in power control register * Disable CPU power down bit in power control register
* ----------------------------------------------------- * -----------------------------------------------------
*/ */
ARES: N1:
mrs x0, CORTEX_ARES_CPUPWRCTLR_EL1 mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1
bic x0, x0, #CORTEX_ARES_CORE_PWRDN_EN_MASK bic x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK
msr CORTEX_ARES_CPUPWRCTLR_EL1, x0 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0
isb isb
ret ret
endfunc plat_reset_handler endfunc plat_reset_handler

4
plat/arm/board/n1sdp/platform.mk
View file

@ -1,5 +1,5 @@
# #
# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. # Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
# #
# SPDX-License-Identifier: BSD-3-Clause # SPDX-License-Identifier: BSD-3-Clause
# #
@ -12,7 +12,7 @@ INTERCONNECT_SOURCES := ${N1SDP_BASE}/n1sdp_interconnect.c
PLAT_INCLUDES := -I${N1SDP_BASE}/include PLAT_INCLUDES := -I${N1SDP_BASE}/include
N1SDP_CPU_SOURCES := lib/cpus/aarch64/cortex_ares.S N1SDP_CPU_SOURCES := lib/cpus/aarch64/neoverse_n1.S
N1SDP_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ N1SDP_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \

4
plat/arm/board/sgiclarka/platform.mk
View file

@ -1,5 +1,5 @@
# #
# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. # Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
# #
# SPDX-License-Identifier: BSD-3-Clause # SPDX-License-Identifier: BSD-3-Clause
# #
@ -10,7 +10,7 @@ SGICLARKA_BASE = plat/arm/board/sgiclarka
PLAT_INCLUDES += -I${SGICLARKA_BASE}/include/ PLAT_INCLUDES += -I${SGICLARKA_BASE}/include/
SGI_CPU_SOURCES := lib/cpus/aarch64/cortex_ares.S SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_n1.S
BL1_SOURCES += ${SGI_CPU_SOURCES} BL1_SOURCES += ${SGI_CPU_SOURCES}

14
plat/arm/css/sgi/aarch64/sgi_helper.S
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -8,7 +8,7 @@
#include <asm_macros.S> #include <asm_macros.S>
#include <platform_def.h> #include <platform_def.h>
#include <cortex_a75.h> #include <cortex_a75.h>
#include <cortex_ares.h> #include <neoverse_n1.h>
#include <cpu_macros.S> #include <cpu_macros.S>
.globl plat_arm_calc_core_pos .globl plat_arm_calc_core_pos
@ -59,7 +59,7 @@ endfunc plat_arm_calc_core_pos
*/ */
func plat_reset_handler func plat_reset_handler
jump_if_cpu_midr CORTEX_A75_MIDR, A75 jump_if_cpu_midr CORTEX_A75_MIDR, A75
jump_if_cpu_midr CORTEX_ARES_MIDR, ARES jump_if_cpu_midr NEOVERSE_N1_MIDR, N1
ret ret
/* ----------------------------------------------------- /* -----------------------------------------------------
@ -73,10 +73,10 @@ A75:
isb isb
ret ret
ARES: N1:
mrs x0, CORTEX_ARES_CPUPWRCTLR_EL1 mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1
bic x0, x0, #CORTEX_ARES_CORE_PWRDN_EN_MASK bic x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK
msr CORTEX_ARES_CPUPWRCTLR_EL1, x0 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0
isb isb
ret ret
endfunc plat_reset_handler endfunc plat_reset_handler

2
readme.rst
View file

@ -195,7 +195,7 @@ This release also contains the following platform support:
- Allwinner sun50i_64 and sun50i_h6 - Allwinner sun50i_64 and sun50i_h6
- Amlogic Meson S905 (GXBB) - Amlogic Meson S905 (GXBB)
- Arm SGI-575, SGI Clark.A, SGI Clark.H and SGM-775 - Arm SGI-575, SGI Clark.A, SGI Clark.H and SGM-775
- Arm NeoVerse N1 System Development Platform - Arm Neoverse N1 System Development Platform
- HiKey, HiKey960 and Poplar boards - HiKey, HiKey960 and Poplar boards
- Marvell Armada 3700 and 8K - Marvell Armada 3700 and 8K
- MediaTek MT6795 and MT8173 SoCs - MediaTek MT6795 and MT8173 SoCs