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fix(arm): add Event Log area behind Trustzone Controller

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To allow the SPD to access the Event Log on RME systems with
TrustZone Controller, the Event Log region needs to be configured
into the TZC. This change will enable read-write access of this
region from the secure world, which is currently denied.

Change-Id: I0c32977386f3d7c22f310b2b9404d48e8e6cac29
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
This commit is contained in:
Manish V Badarkhe 2023-09-01 07:54:33 +01:00
parent f1cb5bd190
commit d836df71ea
1 changed files with 24 additions and 10 deletions
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32
include/plat/arm/common/plat_arm.h
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@ -39,6 +39,20 @@ typedef struct arm_tzc_regions_info {
* - Region 1 with secure access only; * - Region 1 with secure access only;
* - the remaining DRAM regions access from the given Non-Secure masters. * - the remaining DRAM regions access from the given Non-Secure masters.
******************************************************************************/ ******************************************************************************/
#if ENABLE_RME
#define ARM_TZC_RME_REGIONS_DEF \
{ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\
{ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \
{ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
PLAT_ARM_TZC_NS_DEV_ACCESS}, \
/* Realm and Shared area share the same PAS */ \
{ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS, \
PLAT_ARM_TZC_NS_DEV_ACCESS}, \
{ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
PLAT_ARM_TZC_NS_DEV_ACCESS}
#endif
#if SPM_MM #if SPM_MM
#define ARM_TZC_REGIONS_DEF \ #define ARM_TZC_REGIONS_DEF \
{ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\
@ -52,16 +66,16 @@ typedef struct arm_tzc_regions_info {
PLAT_ARM_TZC_NS_DEV_ACCESS} PLAT_ARM_TZC_NS_DEV_ACCESS}
#elif ENABLE_RME #elif ENABLE_RME
#if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \
MEASURED_BOOT
#define ARM_TZC_REGIONS_DEF \ #define ARM_TZC_REGIONS_DEF \
{ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\ ARM_TZC_RME_REGIONS_DEF, \
{ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \ {ARM_EVENT_LOG_DRAM1_BASE, ARM_EVENT_LOG_DRAM1_END, \
{ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ TZC_REGION_S_RDWR, 0}
PLAT_ARM_TZC_NS_DEV_ACCESS}, \ #else
/* Realm and Shared area share the same PAS */ \ #define ARM_TZC_REGIONS_DEF \
{ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS, \ ARM_TZC_RME_REGIONS_DEF
PLAT_ARM_TZC_NS_DEV_ACCESS}, \ #endif
{ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
PLAT_ARM_TZC_NS_DEV_ACCESS}
#else #else
#define ARM_TZC_REGIONS_DEF \ #define ARM_TZC_REGIONS_DEF \