diff --git a/bl31/interrupt_mgmt.c b/bl31/interrupt_mgmt.c index a2b2c0685..1a1cbc4e7 100644 --- a/bl31/interrupt_mgmt.c +++ b/bl31/interrupt_mgmt.c @@ -219,9 +219,9 @@ int32_t register_interrupt_type_handler(uint32_t type, ******************************************************************************/ interrupt_type_handler_t get_interrupt_type_handler(uint32_t type) { - if (validate_interrupt_type(type) != 0) + if (validate_interrupt_type(type) != 0) { return NULL; - + } return intr_type_descs[type].handler; } diff --git a/common/runtime_svc.c b/common/runtime_svc.c index a2c0c09e1..cbba6216a 100644 --- a/common/runtime_svc.c +++ b/common/runtime_svc.c @@ -60,23 +60,23 @@ uintptr_t handle_runtime_svc(uint32_t smc_fid, ******************************************************************************/ static int32_t validate_rt_svc_desc(const rt_svc_desc_t *desc) { - if (desc == NULL) + if (desc == NULL) { return -EINVAL; - - if (desc->start_oen > desc->end_oen) + } + if (desc->start_oen > desc->end_oen) { return -EINVAL; - - if (desc->end_oen >= OEN_LIMIT) + } + if (desc->end_oen >= OEN_LIMIT) { return -EINVAL; - + } if ((desc->call_type != SMC_TYPE_FAST) && - (desc->call_type != SMC_TYPE_YIELD)) + (desc->call_type != SMC_TYPE_YIELD)) { return -EINVAL; - + } /* A runtime service having no init or handle function doesn't make sense */ - if ((desc->init == NULL) && (desc->handle == NULL)) + if ((desc->init == NULL) && (desc->handle == NULL)) { return -EINVAL; - + } return 0; } @@ -98,9 +98,9 @@ void __init runtime_svc_init(void) (RT_SVC_DECS_NUM < MAX_RT_SVCS)); /* If no runtime services are implemented then simply bail out */ - if (RT_SVC_DECS_NUM == 0U) + if (RT_SVC_DECS_NUM == 0U) { return; - + } /* Initialise internal variables to invalid state */ (void)memset(rt_svc_descs_indices, -1, sizeof(rt_svc_descs_indices)); @@ -148,7 +148,8 @@ void __init runtime_svc_init(void) service->call_type); assert(start_idx <= end_idx); assert(end_idx < MAX_RT_SVCS); - for (; start_idx <= end_idx; start_idx++) + for (; start_idx <= end_idx; start_idx++) { rt_svc_descs_indices[start_idx] = index; + } } } diff --git a/common/tf_log.c b/common/tf_log.c index 68f1be49a..2d976f61d 100644 --- a/common/tf_log.c +++ b/common/tf_log.c @@ -34,9 +34,9 @@ void tf_log(const char *fmt, ...) assert((log_level > 0U) && (log_level <= LOG_LEVEL_VERBOSE)); assert((log_level % 10U) == 0U); - if (log_level > max_log_level) + if (log_level > max_log_level) { return; - + } prefix_str = plat_log_get_prefix(log_level); while (*prefix_str != '\0') { @@ -57,8 +57,9 @@ void tf_log_newline(const char log_fmt[2]) assert((log_level > 0U) && (log_level <= LOG_LEVEL_VERBOSE)); assert((log_level % 10U) == 0U); - if (log_level > max_log_level) + if (log_level > max_log_level) { return; + } putchar('\n'); } diff --git a/drivers/arm/cci/cci.c b/drivers/arm/cci/cci.c index 2adfe1718..40d2efdeb 100644 --- a/drivers/arm/cci/cci.c +++ b/drivers/arm/cci/cci.c @@ -153,8 +153,9 @@ void cci_enable_snoop_dvm_reqs(unsigned int master_id) dsbish(); /* Wait for the dust to settle down */ - while ((mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT) != 0U) + while ((mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT) != 0U) { ; + } } void cci_disable_snoop_dvm_reqs(unsigned int master_id) @@ -180,7 +181,8 @@ void cci_disable_snoop_dvm_reqs(unsigned int master_id) dsbish(); /* Wait for the dust to settle down */ - while ((mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT) != 0U) + while ((mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT) != 0U) { ; + } } diff --git a/drivers/arm/gic/v2/gicv2_helpers.c b/drivers/arm/gic/v2/gicv2_helpers.c index 751316c03..a9ae0b53a 100644 --- a/drivers/arm/gic/v2/gicv2_helpers.c +++ b/drivers/arm/gic/v2/gicv2_helpers.c @@ -101,18 +101,19 @@ void gicv2_spis_configure_defaults(uintptr_t gicd_base) * Treat all SPIs as G1NS by default. The number of interrupts is * calculated as 32 * (IT_LINES + 1). We do 32 at a time. */ - for (index = MIN_SPI_ID; index < num_ints; index += 32U) + for (index = MIN_SPI_ID; index < num_ints; index += 32U) { gicd_write_igroupr(gicd_base, index, ~0U); - + } /* Setup the default SPI priorities doing four at a time */ - for (index = MIN_SPI_ID; index < num_ints; index += 4U) + for (index = MIN_SPI_ID; index < num_ints; index += 4U) { gicd_write_ipriorityr(gicd_base, index, GICD_IPRIORITYR_DEF_VAL); - + } /* Treat all SPIs as level triggered by default, 16 at a time */ - for (index = MIN_SPI_ID; index < num_ints; index += 16U) + for (index = MIN_SPI_ID; index < num_ints; index += 16U) { gicd_write_icfgr(gicd_base, index, 0U); + } } /******************************************************************************* @@ -126,15 +127,15 @@ void gicv2_secure_spis_configure_props(uintptr_t gicd_base, const interrupt_prop_t *prop_desc; /* Make sure there's a valid property array */ - if (interrupt_props_num != 0U) + if (interrupt_props_num != 0U) { assert(interrupt_props != NULL); - + } for (i = 0; i < interrupt_props_num; i++) { prop_desc = &interrupt_props[i]; - if (prop_desc->intr_num < MIN_SPI_ID) + if (prop_desc->intr_num < MIN_SPI_ID) { continue; - + } /* Configure this interrupt as a secure interrupt */ assert(prop_desc->intr_grp == GICV2_INTR_GROUP0); gicd_clr_igroupr(gicd_base, prop_desc->intr_num); @@ -168,9 +169,9 @@ void gicv2_secure_ppi_sgi_setup_props(uintptr_t gicd_base, const interrupt_prop_t *prop_desc; /* Make sure there's a valid property array */ - if (interrupt_props_num != 0U) + if (interrupt_props_num != 0U) { assert(interrupt_props != NULL); - + } /* * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a * more scalable approach as it avoids clearing the enable bits in the @@ -179,15 +180,15 @@ void gicv2_secure_ppi_sgi_setup_props(uintptr_t gicd_base, gicd_write_icenabler(gicd_base, 0U, ~0U); /* Setup the default PPI/SGI priorities doing four at a time */ - for (i = 0U; i < MIN_SPI_ID; i += 4U) + for (i = 0U; i < MIN_SPI_ID; i += 4U) { gicd_write_ipriorityr(gicd_base, i, GICD_IPRIORITYR_DEF_VAL); - + } for (i = 0U; i < interrupt_props_num; i++) { prop_desc = &interrupt_props[i]; - if (prop_desc->intr_num >= MIN_SPI_ID) + if (prop_desc->intr_num >= MIN_SPI_ID) { continue; - + } /* Configure this interrupt as a secure interrupt */ assert(prop_desc->intr_grp == GICV2_INTR_GROUP0); diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c index 696bede3c..f9993d411 100644 --- a/drivers/arm/gic/v2/gicv2_main.c +++ b/drivers/arm/gic/v2/gicv2_main.c @@ -220,9 +220,9 @@ unsigned int gicv2_get_pending_interrupt_id(void) * Find out which non-secure interrupt it is under the assumption that * the GICC_CTLR.AckCtl bit is 0. */ - if (id == PENDING_G1_INTID) + if (id == PENDING_G1_INTID) { id = gicc_read_ahppir(driver_data->gicc_base) & INT_ID_MASK; - + } return id; } @@ -301,9 +301,9 @@ void gicv2_set_pe_target_mask(unsigned int proc_num) assert(proc_num < driver_data->target_masks_num); /* Return if the target mask is already populated */ - if (driver_data->target_masks[proc_num] != 0U) + if (driver_data->target_masks[proc_num] != 0U) { return; - + } /* * Update target register corresponding to this CPU and flush for it to * be visible to other CPUs. diff --git a/drivers/console/multi_console.c b/drivers/console/multi_console.c index e962fff37..5ecbaed1d 100644 --- a/drivers/console/multi_console.c +++ b/drivers/console/multi_console.c @@ -22,8 +22,9 @@ int console_register(console_t *console) assert((console < stacks_start) || (console >= stacks_end)); /* Check that we won't make a circle in the list. */ - if (console_is_registered(console) == 1) + if (console_is_registered(console) == 1) { return 1; + } console->next = console_list; console_list = console; @@ -53,9 +54,11 @@ int console_is_registered(console_t *to_find) assert(to_find != NULL); - for (console = console_list; console != NULL; console = console->next) - if (console == to_find) + for (console = console_list; console != NULL; console = console->next) { + if (console == to_find) { return 1; + } + } return 0; } @@ -91,21 +94,24 @@ int console_putc(int c) int err = ERROR_NO_VALID_CONSOLE; console_t *console; - for (console = console_list; console != NULL; console = console->next) + for (console = console_list; console != NULL; console = console->next) { if ((console->flags & console_state) && (console->putc != NULL)) { int ret = do_putc(c, console); - if ((err == ERROR_NO_VALID_CONSOLE) || (ret < err)) + if ((err == ERROR_NO_VALID_CONSOLE) || (ret < err)) { err = ret; + } } + } return err; } int putchar(int c) { - if (console_putc(c) == 0) + if (console_putc(c) == 0) { return c; - else + } else { return EOF; + } } #if ENABLE_CONSOLE_GETC @@ -119,10 +125,12 @@ int console_getc(void) console = console->next) if ((console->flags & console_state) && (console->getc != NULL)) { int ret = console->getc(console); - if (ret >= 0) + if (ret >= 0) { return ret; - if (err != ERROR_NO_PENDING_CHAR) + } + if (err != ERROR_NO_PENDING_CHAR) { err = ret; + } } } while (err == ERROR_NO_PENDING_CHAR); diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index e28e1c34e..3388f1c52 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -1966,10 +1966,11 @@ void cm_el1_sysregs_context_save(uint32_t security_state) el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); #if IMAGE_BL31 - if (security_state == SECURE) + if (security_state == SECURE) { PUBLISH_EVENT(cm_exited_secure_world); - else + } else { PUBLISH_EVENT(cm_exited_normal_world); + } #endif } @@ -1983,10 +1984,11 @@ void cm_el1_sysregs_context_restore(uint32_t security_state) el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); #if IMAGE_BL31 - if (security_state == SECURE) + if (security_state == SECURE) { PUBLISH_EVENT(cm_entering_secure_world); - else + } else { PUBLISH_EVENT(cm_entering_normal_world); + } #endif } diff --git a/lib/locks/bakery/bakery_lock_coherent.c b/lib/locks/bakery/bakery_lock_coherent.c index bcd89ef8a..2617fdfa6 100644 --- a/lib/locks/bakery/bakery_lock_coherent.c +++ b/lib/locks/bakery/bakery_lock_coherent.c @@ -63,8 +63,9 @@ static unsigned int bakery_get_ticket(bakery_lock_t *bakery, unsigned int me) bakery->lock_data[me] = make_bakery_data(CHOOSING_TICKET, my_ticket); for (they = 0U; they < BAKERY_LOCK_MAX_CPUS; they++) { their_ticket = bakery_ticket_number(bakery->lock_data[they]); - if (their_ticket > my_ticket) + if (their_ticket > my_ticket) { my_ticket = their_ticket; + } } /* @@ -108,8 +109,9 @@ void bakery_lock_get(bakery_lock_t *bakery) */ my_prio = bakery_get_priority(my_ticket, me); for (they = 0U; they < BAKERY_LOCK_MAX_CPUS; they++) { - if (me == they) + if (me == they) { continue; + } /* Wait for the contender to get their ticket */ do { diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c index 4c2601eca..234a19509 100644 --- a/lib/psci/psci_common.c +++ b/lib/psci/psci_common.c @@ -138,9 +138,9 @@ int psci_validate_power_state(unsigned int power_state, psci_power_state_t *state_info) { /* Check SBZ bits in power state are zero */ - if (psci_check_power_state(power_state) != 0U) + if (psci_check_power_state(power_state) != 0U) { return PSCI_E_INVALID_PARAMS; - + } assert(psci_plat_pm_ops->validate_power_state != NULL); /* Validate the power_state using platform pm_ops */ @@ -439,8 +439,9 @@ void psci_get_target_local_pwr_states(unsigned int cpu_idx, unsigned int end_pwr } /* Set the the higher levels to RUN */ - for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) + for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) { target_state->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN; + } } /****************************************************************************** @@ -574,8 +575,9 @@ void psci_do_state_coordination(unsigned int cpu_idx, unsigned int end_pwrlvl, state_info->pwr_domain_state[lvl] = target_state; /* Break early if the negotiated target power state is RUN */ - if (is_local_state_run(state_info->pwr_domain_state[lvl]) != 0) + if (is_local_state_run(state_info->pwr_domain_state[lvl]) != 0) { break; + } parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; } @@ -757,8 +759,9 @@ unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info) int i; for (i = (int) PLAT_MAX_PWR_LVL; i >= (int) PSCI_CPU_PWR_LVL; i--) { - if (is_local_state_off(state_info->pwr_domain_state[i]) != 0) + if (is_local_state_off(state_info->pwr_domain_state[i]) != 0) { return (unsigned int) i; + } } return PSCI_INVALID_PWR_LVL; @@ -942,8 +945,9 @@ int psci_validate_entry_point(entry_point_info_t *ep, /* Validate the entrypoint using platform psci_ops */ if (psci_plat_pm_ops->validate_ns_entrypoint != NULL) { rc = psci_plat_pm_ops->validate_ns_entrypoint(entrypoint); - if (rc != PSCI_E_SUCCESS) + if (rc != PSCI_E_SUCCESS) { return PSCI_E_INVALID_ADDRESS; + } } /* @@ -1017,9 +1021,9 @@ void psci_warmboot_entrypoint(void) * of power management handler and perform the generic, architecture * and platform specific handling. */ - if (psci_get_aff_info_state() == AFF_STATE_ON_PENDING) + if (psci_get_aff_info_state() == AFF_STATE_ON_PENDING) { psci_cpu_on_finish(cpu_idx, &state_info); - else { + } else { unsigned int max_off_lvl = psci_find_max_off_lvl(&state_info); assert(max_off_lvl != PSCI_INVALID_PWR_LVL); diff --git a/lib/psci/psci_main.c b/lib/psci/psci_main.c index 45be63a24..34de10ffc 100644 --- a/lib/psci/psci_main.c +++ b/lib/psci/psci_main.c @@ -31,13 +31,15 @@ int psci_cpu_on(u_register_t target_cpu, entry_point_info_t ep; /* Validate the target CPU */ - if (!is_valid_mpidr(target_cpu)) + if (!is_valid_mpidr(target_cpu)) { return PSCI_E_INVALID_PARAMS; + } /* Validate the entry point and get the entry_point_info */ rc = psci_validate_entry_point(&ep, entrypoint, context_id); - if (rc != PSCI_E_SUCCESS) + if (rc != PSCI_E_SUCCESS) { return rc; + } /* * To turn this cpu on, specify which power @@ -102,8 +104,9 @@ int psci_cpu_suspend(unsigned int power_state, /* Fast path for CPU standby.*/ if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) { - if (psci_plat_pm_ops->cpu_standby == NULL) + if (psci_plat_pm_ops->cpu_standby == NULL) { return PSCI_E_INVALID_PARAMS; + } /* * Set the state of the CPU power domain to the platform @@ -171,8 +174,9 @@ int psci_cpu_suspend(unsigned int power_state, */ if (is_power_down_state != 0U) { rc = psci_validate_entry_point(&ep, entrypoint, context_id); - if (rc != PSCI_E_SUCCESS) + if (rc != PSCI_E_SUCCESS) { return rc; + } } /* @@ -199,13 +203,15 @@ int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id) unsigned int cpu_idx = plat_my_core_pos(); /* Check if the current CPU is the last ON CPU in the system */ - if (!psci_is_last_on_cpu(cpu_idx)) + if (!psci_is_last_on_cpu(cpu_idx)) { return PSCI_E_DENIED; + } /* Validate the entry point and get the entry_point_info */ rc = psci_validate_entry_point(&ep, entrypoint, context_id); - if (rc != PSCI_E_SUCCESS) + if (rc != PSCI_E_SUCCESS) { return rc; + } /* Query the psci_power_state for system suspend */ psci_query_sys_suspend_pwrstate(&state_info); @@ -214,9 +220,9 @@ int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id) * Check if platform allows suspend to Highest power level * (System level) */ - if (psci_find_target_suspend_lvl(&state_info) < PLAT_MAX_PWR_LVL) + if (psci_find_target_suspend_lvl(&state_info) < PLAT_MAX_PWR_LVL) { return PSCI_E_DENIED; - + } /* Ensure that the psci_power_state makes sense */ assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN) == PSCI_E_SUCCESS); @@ -264,13 +270,14 @@ int psci_affinity_info(u_register_t target_affinity, unsigned int target_idx; /* Validate the target affinity */ - if (!is_valid_mpidr(target_affinity)) + if (!is_valid_mpidr(target_affinity)) { return PSCI_E_INVALID_PARAMS; + } /* We dont support level higher than PSCI_CPU_PWR_LVL */ - if (lowest_affinity_level > PSCI_CPU_PWR_LVL) + if (lowest_affinity_level > PSCI_CPU_PWR_LVL) { return PSCI_E_INVALID_PARAMS; - + } /* Calculate the cpu index of the target */ target_idx = (unsigned int) plat_core_pos_by_mpidr(target_affinity); @@ -305,20 +312,23 @@ int psci_migrate(u_register_t target_cpu) return PSCI_E_INVALID_PARAMS; rc = psci_spd_migrate_info(&resident_cpu_mpidr); - if (rc != PSCI_TOS_UP_MIG_CAP) + if (rc != PSCI_TOS_UP_MIG_CAP) { return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ? PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED; + } /* * Migrate should only be invoked on the CPU where * the Secure OS is resident. */ - if (resident_cpu_mpidr != read_mpidr_el1()) + if (resident_cpu_mpidr != read_mpidr_el1()) { return PSCI_E_NOT_PRESENT; + } /* Check the validity of the specified target cpu */ - if (!is_valid_mpidr(target_cpu)) + if (!is_valid_mpidr(target_cpu)) { return PSCI_E_INVALID_PARAMS; + } assert((psci_spd_pm != NULL) && (psci_spd_pm->svc_migrate != NULL)); @@ -380,23 +390,23 @@ int psci_features(unsigned int psci_fid) { unsigned int local_caps = psci_caps; - if (psci_fid == SMCCC_VERSION) + if (psci_fid == SMCCC_VERSION) { return PSCI_E_SUCCESS; - + } /* Check if it is a 64 bit function */ - if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64) + if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64) { local_caps &= PSCI_CAP_64BIT_MASK; - + } /* Check for invalid fid */ if (!(is_std_svc_call(psci_fid) && is_valid_fast_smc(psci_fid) - && is_psci_fid(psci_fid))) + && is_psci_fid(psci_fid))) { return PSCI_E_NOT_SUPPORTED; - + } /* Check if the psci fid is supported or not */ - if ((local_caps & define_psci_cap(psci_fid)) == 0U) + if ((local_caps & define_psci_cap(psci_fid)) == 0U) { return PSCI_E_NOT_SUPPORTED; - + } /* Format the feature flags */ if ((psci_fid == PSCI_CPU_SUSPEND_AARCH32) || (psci_fid == PSCI_CPU_SUSPEND_AARCH64)) { @@ -458,12 +468,14 @@ u_register_t psci_smc_handler(uint32_t smc_fid, { u_register_t ret; - if (is_caller_secure(flags)) + if (is_caller_secure(flags)) { return (u_register_t)SMC_UNK; + } /* Check the fid against the capabilities */ - if ((psci_caps & define_psci_cap(smc_fid)) == 0U) + if ((psci_caps & define_psci_cap(smc_fid)) == 0U) { return (u_register_t)SMC_UNK; + } if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) { /* 32-bit PSCI function, clear top parameter bits */ diff --git a/lib/psci/psci_on.c b/lib/psci/psci_on.c index b2797749f..7e161ddb2 100644 --- a/lib/psci/psci_on.c +++ b/lib/psci/psci_on.c @@ -100,8 +100,9 @@ int psci_cpu_on_start(u_register_t target_cpu, * to let it do any bookeeping. If the handler encounters an error, it's * expected to assert within */ - if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_on != NULL)) + if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_on != NULL)) { psci_spd_pm->svc_on(target_cpu); + } /* * Set the Affinity info state of the target cpu to ON_PENDING. @@ -140,10 +141,10 @@ int psci_cpu_on_start(u_register_t target_cpu, rc = psci_plat_pm_ops->pwr_domain_on(target_cpu); assert((rc == PSCI_E_SUCCESS) || (rc == PSCI_E_INTERN_FAIL)); - if (rc == PSCI_E_SUCCESS) + if (rc == PSCI_E_SUCCESS) { /* Store the re-entry information for the non-secure world. */ cm_init_context_by_index(target_idx, ep); - else { + } else { /* Restore the state on error. */ psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_OFF); flush_cpu_data_by_index(target_idx, @@ -182,9 +183,9 @@ void psci_cpu_on_finish(unsigned int cpu_idx, const psci_power_state_t *state_in * can only be done with the cpu and the cluster guaranteed to * be coherent. */ - if (psci_plat_pm_ops->pwr_domain_on_finish_late != NULL) + if (psci_plat_pm_ops->pwr_domain_on_finish_late != NULL) { psci_plat_pm_ops->pwr_domain_on_finish_late(state_info); - + } /* * All the platform specific actions for turning this cpu * on have completed. Perform enough arch.initialization @@ -209,9 +210,9 @@ void psci_cpu_on_finish(unsigned int cpu_idx, const psci_power_state_t *state_in * Dispatcher to let it do any bookeeping. If the handler encounters an * error, it's expected to assert within */ - if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_on_finish != NULL)) + if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_on_finish != NULL)) { psci_spd_pm->svc_on_finish(0); - + } PUBLISH_EVENT(psci_cpu_on_finish); /* Populate the mpidr field within the cpu node array */ diff --git a/lib/psci/psci_setup.c b/lib/psci/psci_setup.c index a81ba4a20..360454929 100644 --- a/lib/psci/psci_setup.c +++ b/lib/psci/psci_setup.c @@ -244,35 +244,44 @@ int __init psci_setup(const psci_lib_args_t *lib_args) /* Initialize the psci capability */ psci_caps = PSCI_GENERIC_CAP; - if (psci_plat_pm_ops->pwr_domain_off != NULL) + if (psci_plat_pm_ops->pwr_domain_off != NULL) { psci_caps |= define_psci_cap(PSCI_CPU_OFF); + } if ((psci_plat_pm_ops->pwr_domain_on != NULL) && - (psci_plat_pm_ops->pwr_domain_on_finish != NULL)) + (psci_plat_pm_ops->pwr_domain_on_finish != NULL)) { psci_caps |= define_psci_cap(PSCI_CPU_ON_AARCH64); + } if ((psci_plat_pm_ops->pwr_domain_suspend != NULL) && (psci_plat_pm_ops->pwr_domain_suspend_finish != NULL)) { - if (psci_plat_pm_ops->validate_power_state != NULL) + if (psci_plat_pm_ops->validate_power_state != NULL) { psci_caps |= define_psci_cap(PSCI_CPU_SUSPEND_AARCH64); - if (psci_plat_pm_ops->get_sys_suspend_power_state != NULL) + } + if (psci_plat_pm_ops->get_sys_suspend_power_state != NULL) { psci_caps |= define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64); + } #if PSCI_OS_INIT_MODE psci_caps |= define_psci_cap(PSCI_SET_SUSPEND_MODE); #endif } - if (psci_plat_pm_ops->system_off != NULL) + if (psci_plat_pm_ops->system_off != NULL) { psci_caps |= define_psci_cap(PSCI_SYSTEM_OFF); - if (psci_plat_pm_ops->system_reset != NULL) + } + if (psci_plat_pm_ops->system_reset != NULL) { psci_caps |= define_psci_cap(PSCI_SYSTEM_RESET); - if (psci_plat_pm_ops->get_node_hw_state != NULL) + } + if (psci_plat_pm_ops->get_node_hw_state != NULL) { psci_caps |= define_psci_cap(PSCI_NODE_HW_STATE_AARCH64); + } if ((psci_plat_pm_ops->read_mem_protect != NULL) && - (psci_plat_pm_ops->write_mem_protect != NULL)) + (psci_plat_pm_ops->write_mem_protect != NULL)) { psci_caps |= define_psci_cap(PSCI_MEM_PROTECT); - if (psci_plat_pm_ops->mem_protect_chk != NULL) + } + if (psci_plat_pm_ops->mem_protect_chk != NULL) { psci_caps |= define_psci_cap(PSCI_MEM_CHK_RANGE_AARCH64); - if (psci_plat_pm_ops->system_reset2 != NULL) + } + if (psci_plat_pm_ops->system_reset2 != NULL) { psci_caps |= define_psci_cap(PSCI_SYSTEM_RESET2_AARCH64); - + } #if ENABLE_PSCI_STAT psci_caps |= define_psci_cap(PSCI_STAT_RESIDENCY_AARCH64); psci_caps |= define_psci_cap(PSCI_STAT_COUNT_AARCH64); diff --git a/lib/psci/psci_system_off.c b/lib/psci/psci_system_off.c index b9418a393..1dcaa2318 100644 --- a/lib/psci/psci_system_off.c +++ b/lib/psci/psci_system_off.c @@ -65,8 +65,9 @@ u_register_t psci_system_reset2(uint32_t reset_type, u_register_t cookie) /* * Only WARM_RESET is allowed for architectural type resets. */ - if (reset_type != PSCI_RESET2_SYSTEM_WARM_RESET) + if (reset_type != PSCI_RESET2_SYSTEM_WARM_RESET) { return (u_register_t) PSCI_E_INVALID_PARAMS; + } if ((psci_plat_pm_ops->write_mem_protect != NULL) && (psci_plat_pm_ops->write_mem_protect(0) < 0)) { return (u_register_t) PSCI_E_NOT_SUPPORTED; diff --git a/plat/common/aarch64/plat_common.c b/plat/common/aarch64/plat_common.c index 7a228b976..ba47b30a0 100644 --- a/plat/common/aarch64/plat_common.c +++ b/plat/common/aarch64/plat_common.c @@ -78,19 +78,27 @@ int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode) const char *get_el_str(unsigned int el) { + const char *mode = NULL; + switch (el) { case MODE_EL3: - return "EL3"; + mode = "EL3"; + break; case MODE_EL2: - return "EL2"; + mode = "EL2"; + break; case MODE_EL1: - return "EL1"; + mode = "EL1"; + break; case MODE_EL0: - return "EL0"; + mode = "EL0"; + break; default: assert(false); - return NULL; + break; } + + return mode; } #if FFH_SUPPORT diff --git a/plat/common/plat_bl_common.c b/plat/common/plat_bl_common.c index dbb6f81f7..4772bada9 100644 --- a/plat/common/plat_bl_common.c +++ b/plat/common/plat_bl_common.c @@ -51,8 +51,9 @@ void bl2_el3_plat_prepare_exit(void) void __dead2 plat_error_handler(int err) { - while (1) + while (1) { wfi(); + } } void bl2_plat_preload_setup(void) diff --git a/plat/common/plat_gicv2.c b/plat/common/plat_gicv2.c index f78d2dfc6..6a2d09032 100644 --- a/plat/common/plat_gicv2.c +++ b/plat/common/plat_gicv2.c @@ -48,8 +48,9 @@ uint32_t plat_ic_get_pending_interrupt_id(void) unsigned int id; id = gicv2_get_pending_interrupt_id(); - if (id == GIC_SPURIOUS_INTERRUPT) - return INTR_ID_UNAVAILABLE; + if (id == GIC_SPURIOUS_INTERRUPT) { + id = INTR_ID_UNAVAILABLE; + } return id; } @@ -68,22 +69,27 @@ uint32_t plat_ic_get_pending_interrupt_id(void) uint32_t plat_ic_get_pending_interrupt_type(void) { unsigned int id; + uint32_t interrupt_type; id = gicv2_get_pending_interrupt_type(); /* Assume that all secure interrupts are S-EL1 interrupts */ if (id < PENDING_G1_INTID) { #if GICV2_G0_FOR_EL3 - return INTR_TYPE_EL3; + interrupt_type = INTR_TYPE_EL3; #else - return INTR_TYPE_S_EL1; + interrupt_type = INTR_TYPE_S_EL1; #endif + } else { + + if (id == GIC_SPURIOUS_INTERRUPT) { + interrupt_type = INTR_TYPE_INVAL; + } else { + interrupt_type = INTR_TYPE_NS; + } } - if (id == GIC_SPURIOUS_INTERRUPT) - return INTR_TYPE_INVAL; - - return INTR_TYPE_NS; + return interrupt_type; } /* @@ -142,8 +148,9 @@ uint32_t plat_interrupt_type_to_line(uint32_t type, assert(sec_state_is_valid(security_state)); /* Non-secure interrupts are signaled on the IRQ line always */ - if (type == INTR_TYPE_NS) + if (type == INTR_TYPE_NS) { return __builtin_ctz(SCR_IRQ_BIT); + } /* * Secure interrupts are signaled using the IRQ line if the FIQ is @@ -329,8 +336,9 @@ unsigned int plat_ic_get_interrupt_id(unsigned int raw) { unsigned int id = (raw & INT_ID_MASK); - if (id == GIC_SPURIOUS_INTERRUPT) + if (id == GIC_SPURIOUS_INTERRUPT) { id = INTR_ID_UNAVAILABLE; + } return id; } diff --git a/plat/common/plat_psci_common.c b/plat/common/plat_psci_common.c index 4cea0b9ae..72b79adb6 100644 --- a/plat/common/plat_psci_common.c +++ b/plat/common/plat_psci_common.c @@ -59,10 +59,11 @@ static u_register_t calc_stat_residency(unsigned long long pwrupts, residency_div = read_cntfrq_el0() / MHZ_TICKS_PER_SEC; assert(residency_div > 0U); - if (pwrupts < pwrdnts) + if (pwrupts < pwrdnts) { res = MAX_TS - pwrdnts + pwrupts; - else + } else { res = pwrupts - pwrdnts; + } return res / residency_div; } @@ -170,8 +171,9 @@ plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, do { temp = *st; st++; - if (temp < target) + if (temp < target) { target = temp; + } n--; } while (n > 0U);