mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-27 07:15:20 +00:00
Merge changes from topic "stm32mp2_bl2_updates" into integration
* changes: feat(stm32mp2): load fw-config file feat(stm32mp2): add fw-config compilation feat(stm32mp2-fdts): add fw-config files for STM32MP257F-EV1 feat(stm32mp2-fdts): add fw-config file feat(stm32mp2-fdts): add clock tree for STM32MP257F-EV1 feat(stm32mp2): enable DDR sub-system clock feat(stm32mp2): add fixed regulators support feat(stm32mp2): print board info feat(stm32mp2): display CPU info feat(stm32mp2): get chip ID feat(stm32mp2): add BL2 boot first steps feat(stm32mp2): add defines for the PWR peripheral feat(stm32mp2-fdts): add SD-card and eMMC support on STM32MP257F-EV1 feat(stm32mp2-fdts): add sdmmc pins definition feat(stm32mp2-fdts): add sdmmc nodes in SoC DT file feat(stm32mp2-fdts): add io_policies feat(stm32mp2-fdts): remove pins-are-numbered
This commit is contained in:
Madhukar Pappireddy
TrustedFirmware Code Review
commit
d76d27e978
21 changed files with 1528 additions and 20 deletions
15
drivers/st/ddr/stm32mp2_ddr_helpers.c
Normal file
15
drivers/st/ddr/stm32mp2_ddr_helpers.c
Normal file
|
|
@ -0,0 +1,15 @@
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/*
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||||
* Copyright (c) 2024, STMicroelectronics - All Rights Reserved
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||||
*
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||||
* SPDX-License-Identifier: BSD-3-Clause
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||||
*/
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||||
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#include <lib/mmio.h>
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#include <platform_def.h>
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void ddr_sub_system_clk_init(void)
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{
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mmio_write_32(stm32mp_rcc_base() + RCC_DDRCPCFGR,
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RCC_DDRCPCFGR_DDRCPEN | RCC_DDRCPCFGR_DDRCPLPEN);
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}
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|
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@ -1,4 +1,35 @@
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|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
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||||
/*
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* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
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* Copyright (C) 2023-2024, STMicroelectronics - All Rights Reserved
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||||
*/
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||||
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/ {
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soc@0 {
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#if !STM32MP_EMMC && !STM32MP_SDMMC
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rifsc@42080000 {
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/delete-node/ mmc@48220000;
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/delete-node/ mmc@48230000;
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};
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#endif
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};
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/*
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* UUID's here are UUID RFC 4122 compliant meaning fieds are stored in
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* network order (big endian)
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*/
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st-io_policies {
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fip-handles {
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compatible = "st,io-fip-handle";
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fw_cfg_uuid = "5807e16a-8459-47be-8ed5-648e8dddab0e";
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bl31_uuid = "47d4086d-4cfe-9846-9b95-2950cbbd5a00";
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bl32_uuid = "05d0e189-53dc-1347-8d2b-500a4b7a3e38";
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bl32_extra1_uuid = "0b70c29b-2a5a-7840-9f65-0a5682738288";
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bl32_extra2_uuid = "8ea87bb1-cfa2-3f4d-85fd-e7bba50220d9";
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bl33_uuid = "d6d0eea7-fcea-d54b-9782-9934f234b6e4";
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hw_cfg_uuid = "08b8f1d9-c9cf-9349-a962-6fbc6b7265cc";
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tos_fw_cfg_uuid = "26257c1a-dbc6-7f47-8d96-c4c4b0248021";
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nt_fw_cfg_uuid = "28da9815-93e8-7e44-ac66-1aaf801550f9";
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};
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};
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};
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|
|
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|||
32
fdts/stm32mp25-fw-config.dtsi
Normal file
32
fdts/stm32mp25-fw-config.dtsi
Normal file
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@ -0,0 +1,32 @@
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|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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/*
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* Copyright (c) 2024, STMicroelectronics - All Rights Reserved
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||||
*/
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#include <common/tbbr/tbbr_img_def.h>
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#include <platform_def.h>
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/dts-v1/;
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/ {
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dtb-registry {
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compatible = "fconf,dyn_cfg-dtb_registry";
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hw-config {
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load-address = <0x0 STM32MP_HW_CONFIG_BASE>;
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max-size = <STM32MP_HW_CONFIG_MAX_SIZE>;
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id = <HW_CONFIG_ID>;
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};
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nt_fw {
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load-address = <0x0 STM32MP_BL33_BASE>;
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max-size = <STM32MP_BL33_MAX_SIZE>;
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id = <BL33_IMAGE_ID>;
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};
|
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|
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tos_fw {
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id = <BL32_IMAGE_ID>;
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||||
};
|
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};
|
||||
};
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|
|
@ -1,11 +1,64 @@
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|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
|
||||
* Copyright (C) 2023-2024, STMicroelectronics - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
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#include <dt-bindings/pinctrl/stm32-pinfunc.h>
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&pinctrl {
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/omit-if-no-ref/
|
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sdmmc1_b4_pins_a: sdmmc1-b4-0 {
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pins1 {
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pinmux = <STM32_PINMUX('E', 4, AF10)>, /* SDMMC1_D0 */
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<STM32_PINMUX('E', 5, AF10)>, /* SDMMC1_D1 */
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<STM32_PINMUX('E', 0, AF10)>, /* SDMMC1_D2 */
|
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<STM32_PINMUX('E', 1, AF10)>, /* SDMMC1_D3 */
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<STM32_PINMUX('E', 2, AF10)>; /* SDMMC1_CMD */
|
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slew-rate = <2>;
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drive-push-pull;
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bias-disable;
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};
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pins2 {
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pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC1_CK */
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slew-rate = <3>;
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drive-push-pull;
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bias-disable;
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};
|
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};
|
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|
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/omit-if-no-ref/
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sdmmc2_b4_pins_a: sdmmc2-b4-0 {
|
||||
pins1 {
|
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pinmux = <STM32_PINMUX('E', 13, AF12)>, /* SDMMC2_D0 */
|
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<STM32_PINMUX('E', 11, AF12)>, /* SDMMC2_D1 */
|
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<STM32_PINMUX('E', 8, AF12)>, /* SDMMC2_D2 */
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<STM32_PINMUX('E', 12, AF12)>, /* SDMMC2_D3 */
|
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<STM32_PINMUX('E', 15, AF12)>; /* SDMMC2_CMD */
|
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slew-rate = <2>;
|
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drive-push-pull;
|
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bias-pull-up;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('E', 14, AF12)>; /* SDMMC2_CK */
|
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slew-rate = <3>;
|
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drive-push-pull;
|
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bias-pull-up;
|
||||
};
|
||||
};
|
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|
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/omit-if-no-ref/
|
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sdmmc2_d47_pins_a: sdmmc2-d47-0 {
|
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pins {
|
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pinmux = <STM32_PINMUX('E', 10, AF12)>, /* SDMMC2_D4 */
|
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<STM32_PINMUX('E', 9, AF12)>, /* SDMMC2_D5 */
|
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<STM32_PINMUX('E', 6, AF12)>, /* SDMMC2_D6 */
|
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<STM32_PINMUX('E', 7, AF12)>; /* SDMMC2_D7 */
|
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slew-rate = <2>;
|
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drive-push-pull;
|
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bias-pull-up;
|
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};
|
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};
|
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/omit-if-no-ref/
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usart2_pins_a: usart2-0 {
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pins1 {
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|
|
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|||
|
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@ -97,6 +97,32 @@
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resets = <&rcc USART2_R>;
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status = "disabled";
|
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};
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|
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sdmmc1: mmc@48220000 {
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compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00353180>;
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reg = <0x48220000 0x400>, <0x44230400 0x8>;
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clocks = <&rcc CK_KER_SDMMC1>;
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clock-names = "apb_pclk";
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resets = <&rcc SDMMC1_R>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <120000000>;
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status = "disabled";
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};
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sdmmc2: mmc@48230000 {
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compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00353180>;
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reg = <0x48230000 0x400>, <0x44230800 0x8>;
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clocks = <&rcc CK_KER_SDMMC2>;
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clock-names = "apb_pclk";
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resets = <&rcc SDMMC2_R>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <120000000>;
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status = "disabled";
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};
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};
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bsec: efuse@44000000 {
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@ -120,6 +146,9 @@
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nand2_otp: otp20@50 {
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reg = <0x50 0x4>;
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};
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rev_otp@198 {
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reg = <0x198 0x4>;
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};
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package_otp: package-otp@1e8 {
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reg = <0x1e8 0x1>;
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};
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@ -176,7 +205,6 @@
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#size-cells = <1>;
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compatible = "st,stm32mp257-pinctrl";
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ranges = <0 0x44240000 0xa0400>;
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pins-are-numbered;
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gpioa: gpio@44240000 {
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gpio-controller;
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@ -305,7 +333,6 @@
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#size-cells = <1>;
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compatible = "st,stm32mp257-z-pinctrl";
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ranges = <0 0x46200000 0x400>;
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pins-are-numbered;
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gpioz: gpio@46200000 {
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gpio-controller;
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|
|
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19
fdts/stm32mp257f-ev1-ca35tdcid-fw-config.dtsi
Normal file
19
fdts/stm32mp257f-ev1-ca35tdcid-fw-config.dtsi
Normal file
|
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@ -0,0 +1,19 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2024 - All Rights Reserved
|
||||
*/
|
||||
|
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/*
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* STM32MP25 tf-a firmware config
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* Project : open
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* Generated by XLmx tool version 2.2 - 2/27/2024 11:46:17 AM
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*/
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/ {
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dtb-registry {
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tos_fw {
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load-address = <0x0 0x82000000>;
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max-size = <0x2000000>;
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};
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};
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};
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97
fdts/stm32mp257f-ev1-ca35tdcid-rcc.dtsi
Normal file
97
fdts/stm32mp257f-ev1-ca35tdcid-rcc.dtsi
Normal file
|
|
@ -0,0 +1,97 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
|
||||
/*
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||||
* Copyright (C) STMicroelectronics 2024 - All Rights Reserved
|
||||
* Author: Loic Pallardy loic.pallardy@foss.st.com for STMicroelectronics.
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||||
*/
|
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/*
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||||
* STM32MP25 Clock tree device tree configuration
|
||||
* Project : open
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* Generated by XLmx tool version 2.2 - 2/27/2024 11:46:16 AM
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||||
*/
|
||||
|
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&clk_hse {
|
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clock-frequency = <40000000>;
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};
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|
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&clk_hsi {
|
||||
clock-frequency = <64000000>;
|
||||
};
|
||||
|
||||
&clk_lse {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
&clk_lsi {
|
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clock-frequency = <32000>;
|
||||
};
|
||||
|
||||
&clk_msi {
|
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clock-frequency = <16000000>;
|
||||
};
|
||||
|
||||
&rcc {
|
||||
st,busclk = <
|
||||
DIV_CFG(DIV_LSMCU, 1)
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||||
DIV_CFG(DIV_APB1, 0)
|
||||
DIV_CFG(DIV_APB2, 0)
|
||||
DIV_CFG(DIV_APB3, 0)
|
||||
DIV_CFG(DIV_APB4, 0)
|
||||
DIV_CFG(DIV_APBDBG, 0)
|
||||
>;
|
||||
|
||||
st,flexgen = <
|
||||
FLEXGEN_CFG(0, XBAR_SRC_PLL4, 0, 2)
|
||||
FLEXGEN_CFG(1, XBAR_SRC_PLL4, 0, 5)
|
||||
FLEXGEN_CFG(2, XBAR_SRC_PLL4, 0, 1)
|
||||
FLEXGEN_CFG(4, XBAR_SRC_PLL4, 0, 3)
|
||||
FLEXGEN_CFG(5, XBAR_SRC_PLL4, 0, 2)
|
||||
FLEXGEN_CFG(8, XBAR_SRC_HSI_KER, 0, 0)
|
||||
FLEXGEN_CFG(48, XBAR_SRC_PLL5, 0, 3)
|
||||
FLEXGEN_CFG(51, XBAR_SRC_PLL4, 0, 5)
|
||||
FLEXGEN_CFG(52, XBAR_SRC_PLL4, 0, 5)
|
||||
FLEXGEN_CFG(58, XBAR_SRC_HSE, 0, 1)
|
||||
FLEXGEN_CFG(63, XBAR_SRC_PLL4, 0, 2)
|
||||
>;
|
||||
|
||||
st,kerclk = <
|
||||
MUX_CFG(MUX_USB2PHY1, MUX_USB2PHY1_FLEX57)
|
||||
MUX_CFG(MUX_USB2PHY2, MUX_USB2PHY2_FLEX58)
|
||||
>;
|
||||
|
||||
pll1: st,pll-1 {
|
||||
st,pll = <&pll1_cfg_1200Mhz>;
|
||||
|
||||
pll1_cfg_1200Mhz: pll1-cfg-1200Mhz {
|
||||
cfg = <30 1 1 1>;
|
||||
src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
|
||||
};
|
||||
};
|
||||
|
||||
pll2: st,pll-2 {
|
||||
st,pll = <&pll2_cfg_600Mhz>;
|
||||
|
||||
pll2_cfg_600Mhz: pll2-cfg-600Mhz {
|
||||
cfg = <30 1 1 2>;
|
||||
src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>;
|
||||
};
|
||||
};
|
||||
|
||||
pll4: st,pll-4 {
|
||||
st,pll = <&pll4_cfg_1200Mhz>;
|
||||
|
||||
pll4_cfg_1200Mhz: pll4-cfg-1200Mhz {
|
||||
cfg = <30 1 1 1>;
|
||||
src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>;
|
||||
};
|
||||
};
|
||||
|
||||
pll5: st,pll-5 {
|
||||
st,pll = <&pll5_cfg_532Mhz>;
|
||||
|
||||
pll5_cfg_532Mhz: pll5-cfg-532Mhz {
|
||||
cfg = <133 5 1 2>;
|
||||
src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
7
fdts/stm32mp257f-ev1-fw-config.dts
Normal file
7
fdts/stm32mp257f-ev1-fw-config.dts
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (c) 2024, STMicroelectronics - All Rights Reserved
|
||||
*/
|
||||
|
||||
#include "stm32mp25-fw-config.dtsi"
|
||||
#include "stm32mp257f-ev1-ca35tdcid-fw-config.dtsi"
|
||||
|
|
@ -6,8 +6,10 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/clock/stm32mp25-clksrc.h>
|
||||
#include "stm32mp257.dtsi"
|
||||
#include "stm32mp25xf.dtsi"
|
||||
#include "stm32mp257f-ev1-ca35tdcid-rcc.dtsi"
|
||||
#include "stm32mp25-pinctrl.dtsi"
|
||||
#include "stm32mp25xxai-pinctrl.dtsi"
|
||||
|
||||
|
|
@ -35,6 +37,25 @@
|
|||
};
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc1_b4_pins_a>;
|
||||
st,neg-edge;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
|
||||
non-removable;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
st,neg-edge;
|
||||
bus-width = <8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usart2_pins_a>;
|
||||
|
|
|
|||
12
include/drivers/st/stm32mp2_ddr_helpers.h
Normal file
12
include/drivers/st/stm32mp2_ddr_helpers.h
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2024, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef STM32MP2_DDR_HELPERS_H
|
||||
#define STM32MP2_DDR_HELPERS_H
|
||||
|
||||
void ddr_sub_system_clk_init(void);
|
||||
|
||||
#endif /* STM32MP2_DDR_HELPERS_H */
|
||||
478
include/drivers/st/stm32mp2_pwr.h
Normal file
478
include/drivers/st/stm32mp2_pwr.h
Normal file
|
|
@ -0,0 +1,478 @@
|
|||
/*
|
||||
* Copyright (c) 2018-2024, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef STM32MP2_PWR_H
|
||||
#define STM32MP2_PWR_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
#define PWR_CR1 U(0x00)
|
||||
#define PWR_CR2 U(0x04)
|
||||
#define PWR_CR3 U(0x08)
|
||||
#define PWR_CR4 U(0x0C)
|
||||
#define PWR_CR5 U(0x10)
|
||||
#define PWR_CR6 U(0x14)
|
||||
#define PWR_CR7 U(0x18)
|
||||
#define PWR_CR8 U(0x1C)
|
||||
#define PWR_CR9 U(0x20)
|
||||
#define PWR_CR10 U(0x24)
|
||||
#define PWR_CR11 U(0x28)
|
||||
#define PWR_CR12 U(0x2C)
|
||||
#define PWR_UCPDR U(0x30)
|
||||
#define PWR_BDCR1 U(0x38)
|
||||
#define PWR_BDCR2 U(0x3C)
|
||||
#define PWR_CPU1CR U(0x40)
|
||||
#define PWR_CPU2CR U(0x44)
|
||||
#define PWR_CPU3CR U(0x48)
|
||||
#define PWR_D1CR U(0x4C)
|
||||
#define PWR_D2CR U(0x50)
|
||||
#define PWR_D3CR U(0x54)
|
||||
#define PWR_WKUPCR1 U(0x60)
|
||||
#define PWR_WKUPCR2 U(0x64)
|
||||
#define PWR_WKUPCR3 U(0x68)
|
||||
#define PWR_WKUPCR4 U(0x6C)
|
||||
#define PWR_WKUPCR5 U(0x70)
|
||||
#define PWR_WKUPCR6 U(0x74)
|
||||
#define PWR_D3WKUPENR U(0x98)
|
||||
#define PWR_RSECCFGR U(0x100)
|
||||
#define PWR_RPRIVCFGR U(0x104)
|
||||
#define PWR_R0CIDCFGR U(0x108)
|
||||
#define PWR_R1CIDCFGR U(0x10C)
|
||||
#define PWR_R2CIDCFGR U(0x110)
|
||||
#define PWR_R3CIDCFGR U(0x114)
|
||||
#define PWR_R4CIDCFGR U(0x118)
|
||||
#define PWR_R5CIDCFGR U(0x11C)
|
||||
#define PWR_R6CIDCFGR U(0x120)
|
||||
#define PWR_WIOSECCFGR U(0x180)
|
||||
#define PWR_WIOPRIVCFGR U(0x184)
|
||||
#define PWR_WIO1CIDCFGR U(0x188)
|
||||
#define PWR_WIO1SEMCR U(0x18C)
|
||||
#define PWR_WIO2CIDCFGR U(0x190)
|
||||
#define PWR_WIO2SEMCR U(0x194)
|
||||
#define PWR_WIO3CIDCFGR U(0x198)
|
||||
#define PWR_WIO3SEMCR U(0x19C)
|
||||
#define PWR_WIO4CIDCFGR U(0x1A0)
|
||||
#define PWR_WIO4SEMCR U(0x1A4)
|
||||
#define PWR_WIO5CIDCFGR U(0x1A8)
|
||||
#define PWR_WIO5SEMCR U(0x1AC)
|
||||
#define PWR_WIO6CIDCFGR U(0x1B0)
|
||||
#define PWR_WIO6SEMCR U(0x1B4)
|
||||
#define PWR_CPU1D1SR U(0x200)
|
||||
#define PWR_CPU2D2SR U(0x204)
|
||||
#define PWR_CPU3D3SR U(0x208)
|
||||
#define PWR_DBGR U(0x308)
|
||||
#define PWR_VERR U(0x3F4)
|
||||
#define PWR_IPIDR U(0x3F8)
|
||||
#define PWR_SIDR U(0x3FC)
|
||||
|
||||
/* PWR_CR1 register fields */
|
||||
#define PWR_CR1_VDDIO3VMEN BIT_32(0)
|
||||
#define PWR_CR1_VDDIO4VMEN BIT_32(1)
|
||||
#define PWR_CR1_USB33VMEN BIT_32(2)
|
||||
#define PWR_CR1_UCPDVMEN BIT_32(3)
|
||||
#define PWR_CR1_AVMEN BIT_32(4)
|
||||
#define PWR_CR1_VDDIO3SV BIT_32(8)
|
||||
#define PWR_CR1_VDDIO4SV BIT_32(9)
|
||||
#define PWR_CR1_USB33SV BIT_32(10)
|
||||
#define PWR_CR1_UCPDSV BIT_32(11)
|
||||
#define PWR_CR1_ASV BIT_32(12)
|
||||
#define PWR_CR1_VDDIO3RDY BIT_32(16)
|
||||
#define PWR_CR1_VDDIO4RDY BIT_32(17)
|
||||
#define PWR_CR1_USB33RDY BIT_32(18)
|
||||
#define PWR_CR1_UCPDRDY BIT_32(19)
|
||||
#define PWR_CR1_ARDY BIT_32(20)
|
||||
#define PWR_CR1_VDDIOVRSEL BIT_32(24)
|
||||
#define PWR_CR1_VDDIO3VRSEL BIT_32(25)
|
||||
#define PWR_CR1_VDDIO4VRSEL BIT_32(26)
|
||||
#define PWR_CR1_GPVMO BIT_32(31)
|
||||
|
||||
/* PWR_CR2 register fields */
|
||||
#define PWR_CR2_MONEN BIT_32(0)
|
||||
#define PWR_CR2_VBATL BIT_32(8)
|
||||
#define PWR_CR2_VBATH BIT_32(9)
|
||||
#define PWR_CR2_TEMPL BIT_32(10)
|
||||
#define PWR_CR2_TEMPH BIT_32(11)
|
||||
|
||||
/* PWR_CR3 register fields */
|
||||
#define PWR_CR3_PVDEN BIT_32(0)
|
||||
#define PWR_CR3_PVDO BIT_32(8)
|
||||
|
||||
/* PWR_CR5 register fields */
|
||||
#define PWR_CR5_VCOREMONEN BIT_32(0)
|
||||
#define PWR_CR5_VCOREL BIT_32(8)
|
||||
#define PWR_CR5_VCOREH BIT_32(9)
|
||||
|
||||
/* PWR_CR6 register fields */
|
||||
#define PWR_CR6_VCPUMONEN BIT_32(0)
|
||||
#define PWR_CR6_VCPULLS BIT_32(4)
|
||||
#define PWR_CR6_VCPUL BIT_32(8)
|
||||
#define PWR_CR6_VCPUH BIT_32(9)
|
||||
|
||||
/* PWR_CR7 register fields */
|
||||
#define PWR_CR7_VDDIO2VMEN BIT_32(0)
|
||||
#define PWR_CR7_VDDIO2SV BIT_32(8)
|
||||
#define PWR_CR7_VDDIO2RDY BIT_32(16)
|
||||
#define PWR_CR7_VDDIO2VRSEL BIT_32(24)
|
||||
#define PWR_CR7_VDDIO2VRSTBY BIT_32(25)
|
||||
|
||||
/* PWR_CR8 register fields */
|
||||
#define PWR_CR8_VDDIO1VMEN BIT_32(0)
|
||||
#define PWR_CR8_VDDIO1SV BIT_32(8)
|
||||
#define PWR_CR8_VDDIO1RDY BIT_32(16)
|
||||
#define PWR_CR8_VDDIO1VRSEL BIT_32(24)
|
||||
#define PWR_CR8_VDDIO1VRSTBY BIT_32(25)
|
||||
|
||||
/* PWR_CR9 register fields */
|
||||
#define PWR_CR9_BKPRBSEN BIT_32(0)
|
||||
#define PWR_CR9_LPR1BSEN BIT_32(4)
|
||||
|
||||
/* PWR_CR10 register fields */
|
||||
#define PWR_CR10_RETRBSEN_MASK GENMASK_32(1, 0)
|
||||
#define PWR_CR10_RETRBSEN_SHIFT U(0)
|
||||
|
||||
/* PWR_CR11 register fields */
|
||||
#define PWR_CR11_DDRRETDIS BIT_32(0)
|
||||
|
||||
/* PWR_CR12 register fields */
|
||||
#define PWR_CR12_GPUVMEN BIT_32(0)
|
||||
#define PWR_CR12_GPULVTEN BIT_32(1)
|
||||
#define PWR_CR12_GPUSV BIT_32(8)
|
||||
#define PWR_CR12_VDDGPURDY BIT_32(16)
|
||||
|
||||
/* PWR_UCPDR register fields */
|
||||
#define PWR_UCPDR_UCPD_DBDIS BIT_32(0)
|
||||
#define PWR_UCPDR_UCPD_STBY BIT_32(1)
|
||||
|
||||
/* PWR_BDCR1 register fields */
|
||||
#define PWR_BDCR1_DBD3P BIT_32(0)
|
||||
|
||||
/* PWR_BDCR2 register fields */
|
||||
#define PWR_BDCR2_DBP BIT_32(0)
|
||||
|
||||
/* PWR_CPU1CR register fields */
|
||||
#define PWR_CPU1CR_PDDS_D2 BIT_32(0)
|
||||
#define PWR_CPU1CR_PDDS_D1 BIT_32(1)
|
||||
#define PWR_CPU1CR_VBF BIT_32(4)
|
||||
#define PWR_CPU1CR_STOPF BIT_32(5)
|
||||
#define PWR_CPU1CR_SBF BIT_32(6)
|
||||
#define PWR_CPU1CR_SBF_D1 BIT_32(7)
|
||||
#define PWR_CPU1CR_SBF_D3 BIT_32(8)
|
||||
#define PWR_CPU1CR_CSSF BIT_32(9)
|
||||
#define PWR_CPU1CR_STANDBYWFIL2 BIT_32(15)
|
||||
#define PWR_CPU1CR_LPDS_D1 BIT_32(16)
|
||||
#define PWR_CPU1CR_LVDS_D1 BIT_32(17)
|
||||
|
||||
/* PWR_CPU2CR register fields */
|
||||
#define PWR_CPU2CR_PDDS_D2 BIT_32(0)
|
||||
#define PWR_CPU2CR_VBF BIT_32(4)
|
||||
#define PWR_CPU2CR_STOPF BIT_32(5)
|
||||
#define PWR_CPU2CR_SBF BIT_32(6)
|
||||
#define PWR_CPU2CR_SBF_D2 BIT_32(7)
|
||||
#define PWR_CPU2CR_SBF_D3 BIT_32(8)
|
||||
#define PWR_CPU2CR_CSSF BIT_32(9)
|
||||
#define PWR_CPU2CR_DEEPSLEEP BIT_32(15)
|
||||
#define PWR_CPU2CR_LPDS_D2 BIT_32(16)
|
||||
#define PWR_CPU2CR_LVDS_D2 BIT_32(17)
|
||||
|
||||
/* PWR_CPU3CR register fields */
|
||||
#define PWR_CPU3CR_VBF BIT_32(4)
|
||||
#define PWR_CPU3CR_SBF_D3 BIT_32(8)
|
||||
#define PWR_CPU3CR_CSSF BIT_32(9)
|
||||
#define PWR_CPU3CR_DEEPSLEEP BIT_32(15)
|
||||
|
||||
/* PWR_D1CR register fields */
|
||||
#define PWR_D1CR_LPCFG_D1 BIT_32(0)
|
||||
#define PWR_D1CR_POPL_D1_MASK GENMASK_32(12, 8)
|
||||
#define PWR_D1CR_POPL_D1_SHIFT U(8)
|
||||
|
||||
/* PWR_D2CR register fields */
|
||||
#define PWR_D2CR_LPCFG_D2 BIT_32(0)
|
||||
#define PWR_D2CR_POPL_D2_MASK GENMASK_32(12, 8)
|
||||
#define PWR_D2CR_POPL_D2_SHIFT U(8)
|
||||
#define PWR_D2CR_LPLVDLY_D2_MASK GENMASK_32(18, 16)
|
||||
#define PWR_D2CR_LPLVDLY_D2_SHIFT U(16)
|
||||
#define PWR_D2CR_PODH_D2_MASK GENMASK_32(27, 24)
|
||||
#define PWR_D2CR_PODH_D2_SHIFT U(24)
|
||||
|
||||
/* PWR_D3CR register fields */
|
||||
#define PWR_D3CR_PDDS_D3 BIT_32(0)
|
||||
#define PWR_D3CR_D3RDY BIT_32(31)
|
||||
|
||||
/* PWR_WKUPCR1 register fields */
|
||||
#define PWR_WKUPCR1_WKUPC BIT_32(0)
|
||||
#define PWR_WKUPCR1_WKUPP BIT_32(8)
|
||||
#define PWR_WKUPCR1_WKUPPUPD_MASK GENMASK_32(13, 12)
|
||||
#define PWR_WKUPCR1_WKUPPUPD_SHIFT U(12)
|
||||
#define PWR_WKUPCR1_WKUPENCPU1 BIT_32(16)
|
||||
#define PWR_WKUPCR1_WKUPENCPU2 BIT_32(17)
|
||||
#define PWR_WKUPCR1_WKUPF BIT_32(31)
|
||||
|
||||
/* PWR_WKUPCR2 register fields */
|
||||
#define PWR_WKUPCR2_WKUPC BIT_32(0)
|
||||
#define PWR_WKUPCR2_WKUPP BIT_32(8)
|
||||
#define PWR_WKUPCR2_WKUPPUPD_MASK GENMASK_32(13, 12)
|
||||
#define PWR_WKUPCR2_WKUPPUPD_SHIFT U(12)
|
||||
#define PWR_WKUPCR2_WKUPENCPU1 BIT_32(16)
|
||||
#define PWR_WKUPCR2_WKUPENCPU2 BIT_32(17)
|
||||
#define PWR_WKUPCR2_WKUPF BIT_32(31)
|
||||
|
||||
/* PWR_WKUPCR3 register fields */
|
||||
#define PWR_WKUPCR3_WKUPC BIT_32(0)
|
||||
#define PWR_WKUPCR3_WKUPP BIT_32(8)
|
||||
#define PWR_WKUPCR3_WKUPPUPD_MASK GENMASK_32(13, 12)
|
||||
#define PWR_WKUPCR3_WKUPPUPD_SHIFT U(12)
|
||||
#define PWR_WKUPCR3_WKUPENCPU1 BIT_32(16)
|
||||
#define PWR_WKUPCR3_WKUPENCPU2 BIT_32(17)
|
||||
#define PWR_WKUPCR3_WKUPF BIT_32(31)
|
||||
|
||||
/* PWR_WKUPCR4 register fields */
|
||||
#define PWR_WKUPCR4_WKUPC BIT_32(0)
|
||||
#define PWR_WKUPCR4_WKUPP BIT_32(8)
|
||||
#define PWR_WKUPCR4_WKUPPUPD_MASK GENMASK_32(13, 12)
|
||||
#define PWR_WKUPCR4_WKUPPUPD_SHIFT U(12)
|
||||
#define PWR_WKUPCR4_WKUPENCPU1 BIT_32(16)
|
||||
#define PWR_WKUPCR4_WKUPENCPU2 BIT_32(17)
|
||||
#define PWR_WKUPCR4_WKUPF BIT_32(31)
|
||||
|
||||
/* PWR_WKUPCR5 register fields */
|
||||
#define PWR_WKUPCR5_WKUPC BIT_32(0)
|
||||
#define PWR_WKUPCR5_WKUPP BIT_32(8)
|
||||
#define PWR_WKUPCR5_WKUPPUPD_MASK GENMASK_32(13, 12)
|
||||
#define PWR_WKUPCR5_WKUPPUPD_SHIFT U(12)
|
||||
#define PWR_WKUPCR5_WKUPENCPU1 BIT_32(16)
|
||||
#define PWR_WKUPCR5_WKUPENCPU2 BIT_32(17)
|
||||
#define PWR_WKUPCR5_WKUPF BIT_32(31)
|
||||
|
||||
/* PWR_WKUPCR6 register fields */
|
||||
#define PWR_WKUPCR6_WKUPC BIT_32(0)
|
||||
#define PWR_WKUPCR6_WKUPP BIT_32(8)
|
||||
#define PWR_WKUPCR6_WKUPPUPD_MASK GENMASK_32(13, 12)
|
||||
#define PWR_WKUPCR6_WKUPPUPD_SHIFT U(12)
|
||||
#define PWR_WKUPCR6_WKUPENCPU1 BIT_32(16)
|
||||
#define PWR_WKUPCR6_WKUPENCPU2 BIT_32(17)
|
||||
#define PWR_WKUPCR6_WKUPF BIT_32(31)
|
||||
|
||||
/* PWR_D3WKUPENR register fields */
|
||||
#define PWR_D3WKUPENR_TAMP_WKUPEN_D3 BIT_32(0)
|
||||
|
||||
/* PWR_RSECCFGR register fields */
|
||||
#define PWR_RSECCFGR_RSEC0 BIT_32(0)
|
||||
#define PWR_RSECCFGR_RSEC1 BIT_32(1)
|
||||
#define PWR_RSECCFGR_RSEC2 BIT_32(2)
|
||||
#define PWR_RSECCFGR_RSEC3 BIT_32(3)
|
||||
#define PWR_RSECCFGR_RSEC4 BIT_32(4)
|
||||
#define PWR_RSECCFGR_RSEC5 BIT_32(5)
|
||||
#define PWR_RSECCFGR_RSEC6 BIT_32(6)
|
||||
|
||||
/* PWR_RPRIVCFGR register fields */
|
||||
#define PWR_RPRIVCFGR_RPRIV0 BIT_32(0)
|
||||
#define PWR_RPRIVCFGR_RPRIV1 BIT_32(1)
|
||||
#define PWR_RPRIVCFGR_RPRIV2 BIT_32(2)
|
||||
#define PWR_RPRIVCFGR_RPRIV3 BIT_32(3)
|
||||
#define PWR_RPRIVCFGR_RPRIV4 BIT_32(4)
|
||||
#define PWR_RPRIVCFGR_RPRIV5 BIT_32(5)
|
||||
#define PWR_RPRIVCFGR_RPRIV6 BIT_32(6)
|
||||
|
||||
/* PWR_R0CIDCFGR register fields */
|
||||
#define PWR_R0CIDCFGR_CFEN BIT_32(0)
|
||||
#define PWR_R0CIDCFGR_SCID_MASK GENMASK_32(6, 4)
|
||||
#define PWR_R0CIDCFGR_SCID_SHIFT U(4)
|
||||
|
||||
/* PWR_R1CIDCFGR register fields */
|
||||
#define PWR_R1CIDCFGR_CFEN BIT_32(0)
|
||||
#define PWR_R1CIDCFGR_SCID_MASK GENMASK_32(6, 4)
|
||||
#define PWR_R1CIDCFGR_SCID_SHIFT U(4)
|
||||
|
||||
/* PWR_R2CIDCFGR register fields */
|
||||
#define PWR_R2CIDCFGR_CFEN BIT_32(0)
|
||||
#define PWR_R2CIDCFGR_SCID_MASK GENMASK_32(6, 4)
|
||||
#define PWR_R2CIDCFGR_SCID_SHIFT U(4)
|
||||
|
||||
/* PWR_R3CIDCFGR register fields */
|
||||
#define PWR_R3CIDCFGR_CFEN BIT_32(0)
|
||||
#define PWR_R3CIDCFGR_SCID_MASK GENMASK_32(6, 4)
|
||||
#define PWR_R3CIDCFGR_SCID_SHIFT U(4)
|
||||
|
||||
/* PWR_R4CIDCFGR register fields */
|
||||
#define PWR_R4CIDCFGR_CFEN BIT_32(0)
|
||||
#define PWR_R4CIDCFGR_SCID_MASK GENMASK_32(6, 4)
|
||||
#define PWR_R4CIDCFGR_SCID_SHIFT U(4)
|
||||
|
||||
/* PWR_R5CIDCFGR register fields */
|
||||
#define PWR_R5CIDCFGR_CFEN BIT_32(0)
|
||||
#define PWR_R5CIDCFGR_SCID_MASK GENMASK_32(6, 4)
|
||||
#define PWR_R5CIDCFGR_SCID_SHIFT U(4)
|
||||
|
||||
/* PWR_R6CIDCFGR register fields */
|
||||
#define PWR_R6CIDCFGR_CFEN BIT_32(0)
|
||||
#define PWR_R6CIDCFGR_SCID_MASK GENMASK_32(6, 4)
|
||||
#define PWR_R6CIDCFGR_SCID_SHIFT U(4)
|
||||
|
||||
/* PWR_WIOSECCFGR register fields */
|
||||
#define PWR_WIOSECCFGR_WIOSEC1 BIT_32(0)
|
||||
#define PWR_WIOSECCFGR_WIOSEC2 BIT_32(1)
|
||||
#define PWR_WIOSECCFGR_WIOSEC3 BIT_32(2)
|
||||
#define PWR_WIOSECCFGR_WIOSEC4 BIT_32(3)
|
||||
#define PWR_WIOSECCFGR_WIOSEC5 BIT_32(4)
|
||||
#define PWR_WIOSECCFGR_WIOSEC6 BIT_32(5)
|
||||
|
||||
/* PWR_WIOPRIVCFGR register fields */
|
||||
#define PWR_WIOPRIVCFGR_WIOPRIV1 BIT_32(0)
|
||||
#define PWR_WIOPRIVCFGR_WIOPRIV2 BIT_32(1)
|
||||
#define PWR_WIOPRIVCFGR_WIOPRIV3 BIT_32(2)
|
||||
#define PWR_WIOPRIVCFGR_WIOPRIV4 BIT_32(3)
|
||||
#define PWR_WIOPRIVCFGR_WIOPRIV5 BIT_32(4)
|
||||
#define PWR_WIOPRIVCFGR_WIOPRIV6 BIT_32(5)
|
||||
|
||||
/* PWR_WIO1CIDCFGR register fields */
|
||||
#define PWR_WIO1CIDCFGR_CFEN BIT_32(0)
|
||||
#define PWR_WIO1CIDCFGR_SEM_EN BIT_32(1)
|
||||
#define PWR_WIO1CIDCFGR_SCID_MASK GENMASK_32(6, 4)
|
||||
#define PWR_WIO1CIDCFGR_SCID_SHIFT U(4)
|
||||
#define PWR_WIO1CIDCFGR_SEMWLC0 BIT_32(16)
|
||||
#define PWR_WIO1CIDCFGR_SEMWLC1 BIT_32(17)
|
||||
#define PWR_WIO1CIDCFGR_SEMWLC2 BIT_32(18)
|
||||
#define PWR_WIO1CIDCFGR_SEMWLC3 BIT_32(19)
|
||||
#define PWR_WIO1CIDCFGR_SEMWLC4 BIT_32(20)
|
||||
#define PWR_WIO1CIDCFGR_SEMWLC5 BIT_32(21)
|
||||
#define PWR_WIO1CIDCFGR_SEMWLC6 BIT_32(22)
|
||||
#define PWR_WIO1CIDCFGR_SEMWLC7 BIT_32(23)
|
||||
|
||||
/* PWR_WIO1SEMCR register fields */
|
||||
#define PWR_WIO1SEMCR_SEM_MUTEX BIT_32(0)
|
||||
#define PWR_WIO1SEMCR_SEMCID_MASK GENMASK_32(6, 4)
|
||||
#define PWR_WIO1SEMCR_SEMCID_SHIFT U(4)
|
||||
|
||||
/* PWR_WIO2CIDCFGR register fields */
|
||||
#define PWR_WIO2CIDCFGR_CFEN BIT_32(0)
|
||||
#define PWR_WIO2CIDCFGR_SEM_EN BIT_32(1)
|
||||
#define PWR_WIO2CIDCFGR_SCID_MASK GENMASK_32(6, 4)
|
||||
#define PWR_WIO2CIDCFGR_SCID_SHIFT U(4)
|
||||
#define PWR_WIO2CIDCFGR_SEMWLC0 BIT_32(16)
|
||||
#define PWR_WIO2CIDCFGR_SEMWLC1 BIT_32(17)
|
||||
#define PWR_WIO2CIDCFGR_SEMWLC2 BIT_32(18)
|
||||
#define PWR_WIO2CIDCFGR_SEMWLC3 BIT_32(19)
|
||||
#define PWR_WIO2CIDCFGR_SEMWLC4 BIT_32(20)
|
||||
#define PWR_WIO2CIDCFGR_SEMWLC5 BIT_32(21)
|
||||
#define PWR_WIO2CIDCFGR_SEMWLC6 BIT_32(22)
|
||||
#define PWR_WIO2CIDCFGR_SEMWLC7 BIT_32(23)
|
||||
|
||||
/* PWR_WIO2SEMCR register fields */
|
||||
#define PWR_WIO2SEMCR_SEM_MUTEX BIT_32(0)
|
||||
#define PWR_WIO2SEMCR_SEMCID_MASK GENMASK_32(6, 4)
|
||||
#define PWR_WIO2SEMCR_SEMCID_SHIFT U(4)
|
||||
|
||||
/* PWR_WIO3CIDCFGR register fields */
|
||||
#define PWR_WIO3CIDCFGR_CFEN BIT_32(0)
|
||||
#define PWR_WIO3CIDCFGR_SEM_EN BIT_32(1)
|
||||
#define PWR_WIO3CIDCFGR_SCID_MASK GENMASK_32(6, 4)
|
||||
#define PWR_WIO3CIDCFGR_SCID_SHIFT U(4)
|
||||
#define PWR_WIO3CIDCFGR_SEMWLC0 BIT_32(16)
|
||||
#define PWR_WIO3CIDCFGR_SEMWLC1 BIT_32(17)
|
||||
#define PWR_WIO3CIDCFGR_SEMWLC2 BIT_32(18)
|
||||
#define PWR_WIO3CIDCFGR_SEMWLC3 BIT_32(19)
|
||||
#define PWR_WIO3CIDCFGR_SEMWLC4 BIT_32(20)
|
||||
#define PWR_WIO3CIDCFGR_SEMWLC5 BIT_32(21)
|
||||
#define PWR_WIO3CIDCFGR_SEMWLC6 BIT_32(22)
|
||||
#define PWR_WIO3CIDCFGR_SEMWLC7 BIT_32(23)
|
||||
|
||||
/* PWR_WIO3SEMCR register fields */
|
||||
#define PWR_WIO3SEMCR_SEM_MUTEX BIT_32(0)
|
||||
#define PWR_WIO3SEMCR_SEMCID_MASK GENMASK_32(6, 4)
|
||||
#define PWR_WIO3SEMCR_SEMCID_SHIFT U(4)
|
||||
|
||||
/* PWR_WIO4CIDCFGR register fields */
|
||||
#define PWR_WIO4CIDCFGR_CFEN BIT_32(0)
|
||||
#define PWR_WIO4CIDCFGR_SEM_EN BIT_32(1)
|
||||
#define PWR_WIO4CIDCFGR_SCID_MASK GENMASK_32(6, 4)
|
||||
#define PWR_WIO4CIDCFGR_SCID_SHIFT U(4)
|
||||
#define PWR_WIO4CIDCFGR_SEMWLC0 BIT_32(16)
|
||||
#define PWR_WIO4CIDCFGR_SEMWLC1 BIT_32(17)
|
||||
#define PWR_WIO4CIDCFGR_SEMWLC2 BIT_32(18)
|
||||
#define PWR_WIO4CIDCFGR_SEMWLC3 BIT_32(19)
|
||||
#define PWR_WIO4CIDCFGR_SEMWLC4 BIT_32(20)
|
||||
#define PWR_WIO4CIDCFGR_SEMWLC5 BIT_32(21)
|
||||
#define PWR_WIO4CIDCFGR_SEMWLC6 BIT_32(22)
|
||||
#define PWR_WIO4CIDCFGR_SEMWLC7 BIT_32(23)
|
||||
|
||||
/* PWR_WIO4SEMCR register fields */
|
||||
#define PWR_WIO4SEMCR_SEM_MUTEX BIT_32(0)
|
||||
#define PWR_WIO4SEMCR_SEMCID_MASK GENMASK_32(6, 4)
|
||||
#define PWR_WIO4SEMCR_SEMCID_SHIFT U(4)
|
||||
|
||||
/* PWR_WIO5CIDCFGR register fields */
|
||||
#define PWR_WIO5CIDCFGR_CFEN BIT_32(0)
|
||||
#define PWR_WIO5CIDCFGR_SEM_EN BIT_32(1)
|
||||
#define PWR_WIO5CIDCFGR_SCID_MASK GENMASK_32(6, 4)
|
||||
#define PWR_WIO5CIDCFGR_SCID_SHIFT U(4)
|
||||
#define PWR_WIO5CIDCFGR_SEMWLC0 BIT_32(16)
|
||||
#define PWR_WIO5CIDCFGR_SEMWLC1 BIT_32(17)
|
||||
#define PWR_WIO5CIDCFGR_SEMWLC2 BIT_32(18)
|
||||
#define PWR_WIO5CIDCFGR_SEMWLC3 BIT_32(19)
|
||||
#define PWR_WIO5CIDCFGR_SEMWLC4 BIT_32(20)
|
||||
#define PWR_WIO5CIDCFGR_SEMWLC5 BIT_32(21)
|
||||
#define PWR_WIO5CIDCFGR_SEMWLC6 BIT_32(22)
|
||||
#define PWR_WIO5CIDCFGR_SEMWLC7 BIT_32(23)
|
||||
|
||||
/* PWR_WIO5SEMCR register fields */
|
||||
#define PWR_WIO5SEMCR_SEM_MUTEX BIT_32(0)
|
||||
#define PWR_WIO5SEMCR_SEMCID_MASK GENMASK_32(6, 4)
|
||||
#define PWR_WIO5SEMCR_SEMCID_SHIFT U(4)
|
||||
|
||||
/* PWR_WIO6CIDCFGR register fields */
|
||||
#define PWR_WIO6CIDCFGR_CFEN BIT_32(0)
|
||||
#define PWR_WIO6CIDCFGR_SEM_EN BIT_32(1)
|
||||
#define PWR_WIO6CIDCFGR_SCID_MASK GENMASK_32(6, 4)
|
||||
#define PWR_WIO6CIDCFGR_SCID_SHIFT U(4)
|
||||
#define PWR_WIO6CIDCFGR_SEMWLC0 BIT_32(16)
|
||||
#define PWR_WIO6CIDCFGR_SEMWLC1 BIT_32(17)
|
||||
#define PWR_WIO6CIDCFGR_SEMWLC2 BIT_32(18)
|
||||
#define PWR_WIO6CIDCFGR_SEMWLC3 BIT_32(19)
|
||||
#define PWR_WIO6CIDCFGR_SEMWLC4 BIT_32(20)
|
||||
#define PWR_WIO6CIDCFGR_SEMWLC5 BIT_32(21)
|
||||
#define PWR_WIO6CIDCFGR_SEMWLC6 BIT_32(22)
|
||||
#define PWR_WIO6CIDCFGR_SEMWLC7 BIT_32(23)
|
||||
|
||||
/* PWR_WIO6SEMCR register fields */
|
||||
#define PWR_WIO6SEMCR_SEM_MUTEX BIT_32(0)
|
||||
#define PWR_WIO6SEMCR_SEMCID_MASK GENMASK_32(6, 4)
|
||||
#define PWR_WIO6SEMCR_SEMCID_SHIFT U(4)
|
||||
|
||||
/* PWR_CPU1D1SR register fields */
|
||||
#define PWR_CPU1D1SR_HOLD_BOOT BIT_32(0)
|
||||
#define PWR_CPU1D1SR_CSTATE_MASK GENMASK_32(3, 2)
|
||||
#define PWR_CPU1D1SR_CSTATE_SHIFT U(2)
|
||||
#define PWR_CPU1D1SR_DSTATE_MASK GENMASK_32(10, 8)
|
||||
#define PWR_CPU1D1SR_DSTATE_SHIFT U(8)
|
||||
|
||||
/* PWR_CPU2D2SR register fields */
|
||||
#define PWR_CPU2D2SR_HOLD_BOOT BIT_32(0)
|
||||
#define PWR_CPU2D2SR_WFBEN BIT_32(1)
|
||||
#define PWR_CPU2D2SR_CSTATE_MASK GENMASK_32(3, 2)
|
||||
#define PWR_CPU2D2SR_CSTATE_SHIFT U(2)
|
||||
#define PWR_CPU2D2SR_DSTATE_MASK GENMASK_32(10, 8)
|
||||
#define PWR_CPU2D2SR_DSTATE_SHIFT U(8)
|
||||
|
||||
/* PWR_CPU3D3SR register fields */
|
||||
#define PWR_CPU3D3SR_CSTATE_MASK GENMASK_32(3, 2)
|
||||
#define PWR_CPU3D3SR_CSTATE_SHIFT U(2)
|
||||
#define PWR_CPU3D3SR_DSTATE_MASK GENMASK_32(10, 8)
|
||||
#define PWR_CPU3D3SR_DSTATE_SHIFT U(8)
|
||||
|
||||
/* PWR_DBGR register fields */
|
||||
#define PWR_DBGR_FD3S BIT_32(0)
|
||||
#define PWR_DBGR_VDDIOKRETRAM BIT_32(16)
|
||||
#define PWR_DBGR_VDDIOKBKPRAM BIT_32(17)
|
||||
#define PWR_DBGR_VDDIOKD3 BIT_32(18)
|
||||
#define PWR_DBGR_VDDIOKLPSRAM1 BIT_32(19)
|
||||
|
||||
/* PWR_VERR register fields */
|
||||
#define PWR_VERR_MINREV_MASK GENMASK_32(3, 0)
|
||||
#define PWR_VERR_MINREV_SHIFT U(0)
|
||||
#define PWR_VERR_MAJREV_MASK GENMASK_32(7, 4)
|
||||
#define PWR_VERR_MAJREV_SHIFT U(4)
|
||||
|
||||
#endif /* STM32MP2_PWR_H */
|
||||
|
|
@ -4,30 +4,268 @@
|
|||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <cdefs.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <common/desc_image_load.h>
|
||||
#include <drivers/clk.h>
|
||||
#include <drivers/mmc.h>
|
||||
#include <drivers/st/regulator_fixed.h>
|
||||
#include <drivers/st/stm32mp2_ddr_helpers.h>
|
||||
#include <lib/fconf/fconf.h>
|
||||
#include <lib/fconf/fconf_dyn_cfg_getter.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <lib/xlat_tables/xlat_tables_v2.h>
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
#include <stm32mp_common.h>
|
||||
#include <stm32mp_dt.h>
|
||||
|
||||
#define BOOT_CTX_ADDR 0x0e000020UL
|
||||
|
||||
static void print_reset_reason(void)
|
||||
{
|
||||
uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_C1BOOTRSTSCLRR);
|
||||
|
||||
if (rstsr == 0U) {
|
||||
WARN("Reset reason unknown\n");
|
||||
return;
|
||||
}
|
||||
|
||||
INFO("Reset reason (0x%x):\n", rstsr);
|
||||
|
||||
if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) == 0U) {
|
||||
if ((rstsr & RCC_C1BOOTRSTSCLRR_STBYC1RSTF) != 0U) {
|
||||
INFO("System exits from Standby for CA35\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if ((rstsr & RCC_C1BOOTRSTSCLRR_D1STBYRSTF) != 0U) {
|
||||
INFO("D1 domain exits from DStandby\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
if ((rstsr & RCC_C1BOOTRSTSCLRR_PORRSTF) != 0U) {
|
||||
INFO(" Power-on Reset (rst_por)\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if ((rstsr & RCC_C1BOOTRSTSCLRR_BORRSTF) != 0U) {
|
||||
INFO(" Brownout Reset (rst_bor)\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC2RSTF) != 0U) {
|
||||
INFO(" System reset (SYSRST) by M33\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC1RSTF) != 0U) {
|
||||
INFO(" System reset (SYSRST) by A35\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if ((rstsr & RCC_C1BOOTRSTSCLRR_HCSSRSTF) != 0U) {
|
||||
INFO(" Clock failure on HSE\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF) != 0U) {
|
||||
INFO(" IWDG1 system reset (rst_iwdg1)\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF) != 0U) {
|
||||
INFO(" IWDG2 system reset (rst_iwdg2)\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF) != 0U) {
|
||||
INFO(" IWDG3 system reset (rst_iwdg3)\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF) != 0U) {
|
||||
INFO(" IWDG4 system reset (rst_iwdg4)\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF) != 0U) {
|
||||
INFO(" IWDG5 system reset (rst_iwdg5)\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if ((rstsr & RCC_C1BOOTRSTSCLRR_C1P1RSTF) != 0U) {
|
||||
INFO(" A35 processor core 1 reset\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) != 0U) {
|
||||
INFO(" Pad Reset from NRST\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if ((rstsr & RCC_C1BOOTRSTSCLRR_VCORERSTF) != 0U) {
|
||||
INFO(" Reset due to a failure of VDD_CORE\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if ((rstsr & RCC_C1BOOTRSTSCLRR_C1RSTF) != 0U) {
|
||||
INFO(" A35 processor reset\n");
|
||||
return;
|
||||
}
|
||||
|
||||
ERROR(" Unidentified reset reason\n");
|
||||
}
|
||||
|
||||
void bl2_el3_early_platform_setup(u_register_t arg0 __unused,
|
||||
u_register_t arg1 __unused,
|
||||
u_register_t arg2 __unused,
|
||||
u_register_t arg3 __unused)
|
||||
{
|
||||
stm32mp_save_boot_ctx_address(BOOT_CTX_ADDR);
|
||||
}
|
||||
|
||||
void bl2_platform_setup(void)
|
||||
{
|
||||
}
|
||||
|
||||
static void reset_backup_domain(void)
|
||||
{
|
||||
uintptr_t pwr_base = stm32mp_pwr_base();
|
||||
uintptr_t rcc_base = stm32mp_rcc_base();
|
||||
|
||||
/*
|
||||
* Disable the backup domain write protection.
|
||||
* The protection is enable at each reset by hardware
|
||||
* and must be disabled by software.
|
||||
*/
|
||||
mmio_setbits_32(pwr_base + PWR_BDCR1, PWR_BDCR1_DBD3P);
|
||||
|
||||
while ((mmio_read_32(pwr_base + PWR_BDCR1) & PWR_BDCR1_DBD3P) == 0U) {
|
||||
;
|
||||
}
|
||||
|
||||
/* Reset backup domain on cold boot cases */
|
||||
if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCCKEN) == 0U) {
|
||||
mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
|
||||
|
||||
while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 0U) {
|
||||
;
|
||||
}
|
||||
|
||||
mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
|
||||
}
|
||||
}
|
||||
|
||||
void bl2_el3_plat_arch_setup(void)
|
||||
{
|
||||
const char *board_model;
|
||||
boot_api_context_t *boot_context =
|
||||
(boot_api_context_t *)stm32mp_get_boot_ctx_address();
|
||||
|
||||
if (stm32_otp_probe() != 0U) {
|
||||
EARLY_ERROR("OTP probe failed\n");
|
||||
panic();
|
||||
}
|
||||
|
||||
mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
|
||||
BL_CODE_END - BL_CODE_BASE,
|
||||
MT_CODE | MT_SECURE);
|
||||
|
||||
configure_mmu();
|
||||
|
||||
/* Prevent corruption of preloaded Device Tree */
|
||||
mmap_add_dynamic_region(DTB_BASE, DTB_BASE,
|
||||
DTB_LIMIT - DTB_BASE,
|
||||
MT_RO_DATA | MT_SECURE);
|
||||
|
||||
if (dt_open_and_check(STM32MP_DTB_BASE) < 0) {
|
||||
panic();
|
||||
}
|
||||
|
||||
reset_backup_domain();
|
||||
|
||||
/*
|
||||
* Initialize DDR sub-system clock. This needs to be done before enabling DDR PLL (PLL2),
|
||||
* and so before stm32mp2_clk_init().
|
||||
*/
|
||||
ddr_sub_system_clk_init();
|
||||
|
||||
if (stm32mp2_clk_init() < 0) {
|
||||
panic();
|
||||
}
|
||||
|
||||
stm32_save_boot_info(boot_context);
|
||||
|
||||
if (stm32mp_uart_console_setup() != 0) {
|
||||
goto skip_console_init;
|
||||
}
|
||||
|
||||
stm32mp_print_cpuinfo();
|
||||
|
||||
board_model = dt_get_board_model();
|
||||
if (board_model != NULL) {
|
||||
NOTICE("Model: %s\n", board_model);
|
||||
}
|
||||
|
||||
stm32mp_print_boardinfo();
|
||||
|
||||
print_reset_reason();
|
||||
|
||||
skip_console_init:
|
||||
if (fixed_regulator_register() != 0) {
|
||||
panic();
|
||||
}
|
||||
|
||||
fconf_populate("TB_FW", STM32MP_DTB_BASE);
|
||||
|
||||
stm32mp_io_setup();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* This function can be used by the platforms to update/use image
|
||||
* information for given `image_id`.
|
||||
******************************************************************************/
|
||||
int bl2_plat_handle_post_image_load(unsigned int image_id)
|
||||
{
|
||||
int err = 0;
|
||||
bl_mem_params_node_t *bl_mem_params __maybe_unused = get_bl_mem_params_node(image_id);
|
||||
|
||||
assert(bl_mem_params != NULL);
|
||||
|
||||
#if STM32MP_SDMMC || STM32MP_EMMC
|
||||
/*
|
||||
* Invalidate remaining data read from MMC but not flushed by load_image_flush().
|
||||
* We take the worst case which is 2 MMC blocks.
|
||||
*/
|
||||
if ((image_id != FW_CONFIG_ID) &&
|
||||
((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) {
|
||||
inv_dcache_range(bl_mem_params->image_info.image_base +
|
||||
bl_mem_params->image_info.image_size,
|
||||
2U * MMC_BLOCK_SIZE);
|
||||
}
|
||||
#endif /* STM32MP_SDMMC || STM32MP_EMMC */
|
||||
|
||||
switch (image_id) {
|
||||
case FW_CONFIG_ID:
|
||||
/* Set global DTB info for fixed fw_config information */
|
||||
set_config_info(STM32MP_FW_CONFIG_BASE, ~0UL, STM32MP_FW_CONFIG_MAX_SIZE,
|
||||
FW_CONFIG_ID);
|
||||
fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE);
|
||||
|
||||
mmap_remove_dynamic_region(DTB_BASE, DTB_LIMIT - DTB_BASE);
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
/* Do nothing in default case */
|
||||
break;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -86,7 +86,7 @@
|
|||
/* Image Header related definitions */
|
||||
|
||||
/* Definition of header version */
|
||||
#define BOOT_API_HEADER_VERSION 0x00020000U
|
||||
#define BOOT_API_HEADER_VERSION 0x00020200U
|
||||
|
||||
/*
|
||||
* Magic number used to detect header in memory
|
||||
|
|
|
|||
47
plat/st/stm32mp2/include/plat_tbbr_img_def.h
Normal file
47
plat/st/stm32mp2/include/plat_tbbr_img_def.h
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* Copyright (c) 2024, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLAT_TBBR_IMG_DEF_H
|
||||
#define PLAT_TBBR_IMG_DEF_H
|
||||
|
||||
#include <export/common/tbbr/tbbr_img_def_exp.h>
|
||||
|
||||
/* Undef the existing values */
|
||||
#undef BKUP_FWU_METADATA_IMAGE_ID
|
||||
#undef FWU_METADATA_IMAGE_ID
|
||||
#undef FW_CONFIG_ID
|
||||
#undef ENC_IMAGE_ID
|
||||
#undef GPT_IMAGE_ID
|
||||
#undef NT_FW_CONFIG_ID
|
||||
#undef SOC_FW_CONFIG_ID
|
||||
#undef TB_FW_CONFIG_ID
|
||||
#undef HW_CONFIG_ID
|
||||
#undef TRUSTED_BOOT_FW_CERT_ID
|
||||
#undef SOC_FW_CONTENT_CERT_ID
|
||||
#undef BL32_EXTRA1_IMAGE_ID
|
||||
#undef TOS_FW_CONFIG_ID
|
||||
|
||||
/* Define the STM32MP2 used ID */
|
||||
#define FW_CONFIG_ID U(1)
|
||||
#define HW_CONFIG_ID U(2)
|
||||
#define ENC_IMAGE_ID U(6)
|
||||
#define BL32_EXTRA1_IMAGE_ID U(8)
|
||||
#define FWU_METADATA_IMAGE_ID U(12)
|
||||
#define BKUP_FWU_METADATA_IMAGE_ID U(13)
|
||||
#define TOS_FW_CONFIG_ID U(16)
|
||||
#define NT_FW_CONFIG_ID U(18)
|
||||
#define SOC_FW_CONFIG_ID U(19)
|
||||
#define TB_FW_CONFIG_ID U(20)
|
||||
#define TRUSTED_BOOT_FW_CERT_ID U(21)
|
||||
#define SOC_FW_CONTENT_CERT_ID U(23)
|
||||
#define STM32MP_CONFIG_CERT_ID U(24)
|
||||
#define GPT_IMAGE_ID U(25)
|
||||
|
||||
/* Increase the MAX_NUMBER_IDS to match the authentication pool required */
|
||||
#define MAX_NUMBER_IDS U(26)
|
||||
|
||||
#endif /* PLAT_TBBR_IMG_DEF_H */
|
||||
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2023, STMicroelectronics - All Rights Reserved
|
||||
* Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -61,11 +61,32 @@
|
|||
#define BL2_LIMIT (STM32MP_BL2_BASE + \
|
||||
STM32MP_BL2_SIZE)
|
||||
|
||||
#define BL2_RO_BASE STM32MP_BL2_RO_BASE
|
||||
#define BL2_RO_LIMIT (STM32MP_BL2_RO_BASE + \
|
||||
STM32MP_BL2_RO_SIZE)
|
||||
|
||||
#define BL2_RW_BASE STM32MP_BL2_RW_BASE
|
||||
#define BL2_RW_LIMIT (STM32MP_BL2_RW_BASE + \
|
||||
STM32MP_BL2_RW_SIZE)
|
||||
|
||||
/*******************************************************************************
|
||||
* BL31 specific defines.
|
||||
******************************************************************************/
|
||||
#define BL31_BASE 0
|
||||
#define BL31_LIMIT STM32MP_BL31_SIZE
|
||||
|
||||
/*******************************************************************************
|
||||
* BL33 specific defines.
|
||||
******************************************************************************/
|
||||
#define BL33_BASE STM32MP_BL33_BASE
|
||||
|
||||
/*******************************************************************************
|
||||
* DTB specific defines.
|
||||
******************************************************************************/
|
||||
#define DTB_BASE STM32MP_DTB_BASE
|
||||
#define DTB_LIMIT (STM32MP_DTB_BASE + \
|
||||
STM32MP_DTB_SIZE)
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform specific page table and MMU setup constants
|
||||
******************************************************************************/
|
||||
|
|
|
|||
|
|
@ -7,6 +7,10 @@
|
|||
#ifndef STM32MP2_PRIVATE_H
|
||||
#define STM32MP2_PRIVATE_H
|
||||
|
||||
void configure_mmu(void);
|
||||
|
||||
uint32_t stm32mp_syscfg_get_chip_dev_id(void);
|
||||
|
||||
/* Wrappers for OTP / BSEC functions */
|
||||
static inline uint32_t stm32_otp_probe(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1,10 +1,14 @@
|
|||
/*
|
||||
* Copyright (c) 2023, STMicroelectronics - All Rights Reserved
|
||||
* Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <common/bl_common.h>
|
||||
#include <common/desc_image_load.h>
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Following descriptor provides BL image/ep information that gets used
|
||||
|
|
@ -15,6 +19,21 @@
|
|||
* the next executable image id.
|
||||
******************************************************************************/
|
||||
static bl_mem_params_node_t bl2_mem_params_descs[] = {
|
||||
/* Fill FW_CONFIG related information if it exists */
|
||||
{
|
||||
.image_id = FW_CONFIG_ID,
|
||||
SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
|
||||
VERSION_2, entry_point_info_t,
|
||||
SECURE | NON_EXECUTABLE),
|
||||
SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
|
||||
VERSION_2, image_info_t,
|
||||
IMAGE_ATTRIB_PLAT_SETUP),
|
||||
|
||||
.image_info.image_base = STM32MP_FW_CONFIG_BASE,
|
||||
.image_info.image_max_size = STM32MP_FW_CONFIG_MAX_SIZE,
|
||||
|
||||
.next_handoff_image_id = INVALID_IMAGE_ID,
|
||||
},
|
||||
};
|
||||
|
||||
REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@ include plat/st/common/common.mk
|
|||
CRASH_REPORTING := 1
|
||||
ENABLE_PIE := 1
|
||||
PROGRAMMABLE_RESET_ADDRESS := 1
|
||||
BL2_IN_XIP_MEM := 1
|
||||
|
||||
# Default Device tree
|
||||
DTB_FILE_NAME ?= stm32mp257f-ev1.dtb
|
||||
|
|
@ -35,9 +36,32 @@ STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(
|
|||
STM32_LD_FILE := plat/st/stm32mp2/${ARCH}/stm32mp2.ld.S
|
||||
STM32_BINARY_MAPPING := plat/st/stm32mp2/${ARCH}/stm32mp2.S
|
||||
|
||||
STM32MP_FW_CONFIG_NAME := $(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME))
|
||||
STM32MP_FW_CONFIG := ${BUILD_PLAT}/fdts/$(STM32MP_FW_CONFIG_NAME)
|
||||
FDT_SOURCES += $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32MP_FW_CONFIG_NAME)))
|
||||
# Add the FW_CONFIG to FIP and specify the same to certtool
|
||||
$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_FW_CONFIG},--fw-config))
|
||||
|
||||
# Enable flags for C files
|
||||
$(eval $(call assert_booleans,\
|
||||
$(sort \
|
||||
STM32MP25 \
|
||||
)))
|
||||
|
||||
$(eval $(call assert_numerics,\
|
||||
$(sort \
|
||||
PLAT_PARTITION_MAX_ENTRIES \
|
||||
STM32_HEADER_VERSION_MAJOR \
|
||||
STM32_TF_A_COPIES \
|
||||
)))
|
||||
|
||||
$(eval $(call add_defines,\
|
||||
$(sort \
|
||||
DWL_BUFFER_BASE \
|
||||
PLAT_PARTITION_MAX_ENTRIES \
|
||||
PLAT_TBBR_IMG_DEF \
|
||||
STM32_TF_A_COPIES \
|
||||
STM32MP25 \
|
||||
)))
|
||||
|
||||
# STM32MP2x is based on Cortex-A35, which is Armv8.0, and does not support BTI
|
||||
|
|
@ -51,17 +75,28 @@ PLAT_BL_COMMON_SOURCES += lib/cpus/${ARCH}/cortex_a35.S
|
|||
PLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S
|
||||
PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S
|
||||
|
||||
PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/stm32mp2_private.c
|
||||
|
||||
PLAT_BL_COMMON_SOURCES += drivers/st/bsec/bsec3.c \
|
||||
drivers/st/reset/stm32mp2_reset.c
|
||||
drivers/st/reset/stm32mp2_reset.c \
|
||||
plat/st/stm32mp2/stm32mp2_syscfg.c
|
||||
|
||||
PLAT_BL_COMMON_SOURCES += drivers/st/clk/clk-stm32-core.c \
|
||||
drivers/st/clk/clk-stm32mp2.c
|
||||
|
||||
BL2_SOURCES += plat/st/stm32mp2/plat_bl2_mem_params_desc.c
|
||||
|
||||
BL2_SOURCES += plat/st/stm32mp2/bl2_plat_setup.c
|
||||
|
||||
ifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),)
|
||||
BL2_SOURCES += drivers/st/mmc/stm32_sdmmc2.c
|
||||
endif
|
||||
|
||||
ifeq (${STM32MP_USB_PROGRAMMER},1)
|
||||
BL2_SOURCES += plat/st/stm32mp2/stm32mp2_usb_dfu.c
|
||||
endif
|
||||
|
||||
BL2_SOURCES += drivers/st/ddr/stm32mp2_ddr_helpers.c
|
||||
|
||||
# Compilation rules
|
||||
include plat/st/common/common_rules.mk
|
||||
|
|
|
|||
|
|
@ -12,6 +12,10 @@
|
|||
#include <drivers/st/bsec.h>
|
||||
#endif
|
||||
#include <drivers/st/stm32mp25_rcc.h>
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <drivers/st/stm32mp2_clk.h>
|
||||
#endif
|
||||
#include <drivers/st/stm32mp2_pwr.h>
|
||||
#include <dt-bindings/clock/stm32mp25-clks.h>
|
||||
#include <dt-bindings/clock/stm32mp25-clksrc.h>
|
||||
#include <dt-bindings/gpio/stm32-gpio.h>
|
||||
|
|
@ -25,15 +29,49 @@
|
|||
#include <stm32mp_shared_resources.h>
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* CHIP ID
|
||||
******************************************************************************/
|
||||
#define STM32MP2_CHIP_ID U(0x505)
|
||||
|
||||
#define STM32MP251A_PART_NB U(0x400B3E6D)
|
||||
#define STM32MP251C_PART_NB U(0x000B306D)
|
||||
#define STM32MP251D_PART_NB U(0xC00B3E6D)
|
||||
#define STM32MP251F_PART_NB U(0x800B306D)
|
||||
#define STM32MP253A_PART_NB U(0x400B3E0C)
|
||||
#define STM32MP253C_PART_NB U(0x000B300C)
|
||||
#define STM32MP253D_PART_NB U(0xC00B3E0C)
|
||||
#define STM32MP253F_PART_NB U(0x800B300C)
|
||||
#define STM32MP255A_PART_NB U(0x40082E00)
|
||||
#define STM32MP255C_PART_NB U(0x00082000)
|
||||
#define STM32MP255D_PART_NB U(0xC0082E00)
|
||||
#define STM32MP255F_PART_NB U(0x80082000)
|
||||
#define STM32MP257A_PART_NB U(0x40002E00)
|
||||
#define STM32MP257C_PART_NB U(0x00002000)
|
||||
#define STM32MP257D_PART_NB U(0xC0002E00)
|
||||
#define STM32MP257F_PART_NB U(0x80002000)
|
||||
|
||||
#define STM32MP2_REV_A U(0x08)
|
||||
#define STM32MP2_REV_B U(0x10)
|
||||
#define STM32MP2_REV_X U(0x12)
|
||||
#define STM32MP2_REV_Y U(0x11)
|
||||
#define STM32MP2_REV_Z U(0x09)
|
||||
|
||||
/*******************************************************************************
|
||||
* PACKAGE ID
|
||||
******************************************************************************/
|
||||
#define STM32MP25_PKG_CUSTOM U(0)
|
||||
#define STM32MP25_PKG_AL_VFBGA361 U(1)
|
||||
#define STM32MP25_PKG_AK_VFBGA424 U(3)
|
||||
#define STM32MP25_PKG_AI_TFBGA436 U(5)
|
||||
#define STM32MP25_PKG_UNKNOWN U(7)
|
||||
|
||||
/*******************************************************************************
|
||||
* STM32MP2 memory map related constants
|
||||
******************************************************************************/
|
||||
#define STM32MP_SYSRAM_BASE U(0x0E000000)
|
||||
#define STM32MP_SYSRAM_SIZE U(0x00040000)
|
||||
|
||||
#define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE
|
||||
#define STM32MP_SEC_SYSRAM_SIZE STM32MP_SYSRAM_SIZE
|
||||
|
||||
/* DDR configuration */
|
||||
#define STM32MP_DDR_BASE U(0x80000000)
|
||||
#define STM32MP_DDR_MAX_SIZE UL(0x100000000) /* Max 4GB */
|
||||
|
|
@ -49,28 +87,38 @@ enum ddr_type {
|
|||
|
||||
/* Section used inside TF binaries */
|
||||
#define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
|
||||
/* 512 Octets reserved for header */
|
||||
/* 512 Bytes reserved for header */
|
||||
#define STM32MP_HEADER_SIZE U(0x00000200)
|
||||
#define STM32MP_HEADER_BASE (STM32MP_SEC_SYSRAM_BASE + \
|
||||
#define STM32MP_HEADER_BASE (STM32MP_SYSRAM_BASE + \
|
||||
STM32MP_PARAM_LOAD_SIZE)
|
||||
|
||||
/* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */
|
||||
#define STM32MP_HEADER_RESERVED_SIZE U(0x3000)
|
||||
|
||||
#define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \
|
||||
#define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \
|
||||
STM32MP_PARAM_LOAD_SIZE + \
|
||||
STM32MP_HEADER_SIZE)
|
||||
|
||||
#define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
|
||||
#define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \
|
||||
(STM32MP_PARAM_LOAD_SIZE + \
|
||||
STM32MP_HEADER_SIZE))
|
||||
|
||||
#define STM32MP_BL2_SIZE U(0x0002A000) /* 168 KB for BL2 */
|
||||
#define STM32MP_BL2_RO_SIZE U(0x00020000) /* 128 KB */
|
||||
#define STM32MP_BL2_SIZE U(0x00029000) /* 164 KB for BL2 */
|
||||
|
||||
#define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \
|
||||
STM32MP_SEC_SYSRAM_SIZE - \
|
||||
#define STM32MP_BL2_BASE (STM32MP_SYSRAM_BASE + \
|
||||
STM32MP_SYSRAM_SIZE - \
|
||||
STM32MP_BL2_SIZE)
|
||||
|
||||
#define STM32MP_BL2_RO_BASE STM32MP_BL2_BASE
|
||||
|
||||
#define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \
|
||||
STM32MP_BL2_RO_SIZE)
|
||||
|
||||
#define STM32MP_BL2_RW_SIZE (STM32MP_SYSRAM_BASE + \
|
||||
STM32MP_SYSRAM_SIZE - \
|
||||
STM32MP_BL2_RW_BASE)
|
||||
|
||||
/* BL2 and BL32/sp_min require 4 tables */
|
||||
#define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
|
||||
|
||||
|
|
@ -81,13 +129,30 @@ enum ddr_type {
|
|||
#define MAX_MMAP_REGIONS 6
|
||||
|
||||
/* DTB initialization value */
|
||||
#define STM32MP_BL2_DTB_SIZE U(0x00005000) /* 20 KB for DTB */
|
||||
#define STM32MP_BL2_DTB_SIZE U(0x00006000) /* 24 KB for DTB */
|
||||
|
||||
#define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \
|
||||
STM32MP_BL2_DTB_SIZE)
|
||||
|
||||
#if defined(IMAGE_BL2)
|
||||
#define STM32MP_DTB_SIZE STM32MP_BL2_DTB_SIZE
|
||||
#define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE
|
||||
#endif
|
||||
|
||||
#define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE
|
||||
#define STM32MP_FW_CONFIG_BASE STM32MP_SYSRAM_BASE
|
||||
|
||||
#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000))
|
||||
#define STM32MP_BL33_MAX_SIZE U(0x400000)
|
||||
#define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \
|
||||
STM32MP_BL33_MAX_SIZE)
|
||||
#define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000)
|
||||
|
||||
/*******************************************************************************
|
||||
* STM32MP2 device/io map related constants (used for MMU)
|
||||
******************************************************************************/
|
||||
#define STM32MP_DEVICE_BASE U(0x40000000)
|
||||
#define STM32MP_DEVICE_SIZE U(0x40000000)
|
||||
|
||||
/*******************************************************************************
|
||||
* STM32MP2 RCC
|
||||
|
|
@ -172,6 +237,7 @@ enum ddr_type {
|
|||
|
||||
/* OTP labels */
|
||||
#define PART_NUMBER_OTP "part-number-otp"
|
||||
#define REVISION_OTP "rev_otp"
|
||||
#define PACKAGE_OTP "package-otp"
|
||||
#define HCONF1_OTP "otp124"
|
||||
#define NAND_OTP "otp16"
|
||||
|
|
@ -314,6 +380,7 @@ static inline uintptr_t tamp_bkpr(uint32_t idx)
|
|||
#define DT_DDR_COMPAT "st,stm32mp2-ddr"
|
||||
#define DT_PWR_COMPAT "st,stm32mp25-pwr"
|
||||
#define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc"
|
||||
#define DT_SDMMC2_COMPAT "st,stm32mp25-sdmmc2"
|
||||
#define DT_UART_COMPAT "st,stm32h7-uart"
|
||||
|
||||
#endif /* STM32MP2_DEF_H */
|
||||
|
|
|
|||
254
plat/st/stm32mp2/stm32mp2_private.c
Normal file
254
plat/st/stm32mp2/stm32mp2_private.c
Normal file
|
|
@ -0,0 +1,254 @@
|
|||
/*
|
||||
* Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#include <lib/xlat_tables/xlat_tables_v2.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#define BKPR_BOOT_MODE 96U
|
||||
|
||||
#define MAP_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \
|
||||
STM32MP_SYSRAM_SIZE, \
|
||||
MT_MEMORY | \
|
||||
MT_RW | \
|
||||
MT_SECURE | \
|
||||
MT_EXECUTE_NEVER)
|
||||
|
||||
#define MAP_DEVICE MAP_REGION_FLAT(STM32MP_DEVICE_BASE, \
|
||||
STM32MP_DEVICE_SIZE, \
|
||||
MT_DEVICE | \
|
||||
MT_RW | \
|
||||
MT_SECURE | \
|
||||
MT_EXECUTE_NEVER)
|
||||
|
||||
#if defined(IMAGE_BL2)
|
||||
static const mmap_region_t stm32mp2_mmap[] = {
|
||||
MAP_SYSRAM,
|
||||
MAP_DEVICE,
|
||||
{0}
|
||||
};
|
||||
#endif
|
||||
|
||||
void configure_mmu(void)
|
||||
{
|
||||
mmap_add(stm32mp2_mmap);
|
||||
init_xlat_tables();
|
||||
|
||||
enable_mmu_el3(0);
|
||||
}
|
||||
|
||||
uintptr_t stm32_get_gpio_bank_base(unsigned int bank)
|
||||
{
|
||||
if (bank == GPIO_BANK_Z) {
|
||||
return GPIOZ_BASE;
|
||||
}
|
||||
|
||||
assert(bank <= GPIO_BANK_K);
|
||||
|
||||
return GPIOA_BASE + (bank * GPIO_BANK_OFFSET);
|
||||
}
|
||||
|
||||
uint32_t stm32_get_gpio_bank_offset(unsigned int bank)
|
||||
{
|
||||
if (bank == GPIO_BANK_Z) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
assert(bank <= GPIO_BANK_K);
|
||||
|
||||
return bank * GPIO_BANK_OFFSET;
|
||||
}
|
||||
|
||||
unsigned long stm32_get_gpio_bank_clock(unsigned int bank)
|
||||
{
|
||||
if (bank == GPIO_BANK_Z) {
|
||||
return CK_BUS_GPIOZ;
|
||||
}
|
||||
|
||||
assert(bank <= GPIO_BANK_K);
|
||||
|
||||
return CK_BUS_GPIOA + (bank - GPIO_BANK_A);
|
||||
}
|
||||
|
||||
uint32_t stm32mp_get_chip_version(void)
|
||||
{
|
||||
static uint32_t rev;
|
||||
|
||||
if (rev != 0U) {
|
||||
return rev;
|
||||
}
|
||||
|
||||
if (stm32_get_otp_value(REVISION_OTP, &rev) != 0) {
|
||||
panic();
|
||||
}
|
||||
|
||||
return rev;
|
||||
}
|
||||
|
||||
uint32_t stm32mp_get_chip_dev_id(void)
|
||||
{
|
||||
return stm32mp_syscfg_get_chip_dev_id();
|
||||
}
|
||||
|
||||
static uint32_t get_part_number(void)
|
||||
{
|
||||
static uint32_t part_number;
|
||||
|
||||
if (part_number != 0U) {
|
||||
return part_number;
|
||||
}
|
||||
|
||||
if (stm32_get_otp_value(PART_NUMBER_OTP, &part_number) != 0) {
|
||||
panic();
|
||||
}
|
||||
|
||||
return part_number;
|
||||
}
|
||||
|
||||
static uint32_t get_cpu_package(void)
|
||||
{
|
||||
static uint32_t package = UINT32_MAX;
|
||||
|
||||
if (package == UINT32_MAX) {
|
||||
if (stm32_get_otp_value(PACKAGE_OTP, &package) != 0) {
|
||||
panic();
|
||||
}
|
||||
}
|
||||
|
||||
return (package & PACKAGE_OTP_PKG_MASK) >> PACKAGE_OTP_PKG_SHIFT;
|
||||
}
|
||||
|
||||
void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE])
|
||||
{
|
||||
char *cpu_s, *cpu_r, *pkg;
|
||||
|
||||
/* MPUs Part Numbers */
|
||||
switch (get_part_number()) {
|
||||
case STM32MP251A_PART_NB:
|
||||
cpu_s = "251A";
|
||||
break;
|
||||
case STM32MP251C_PART_NB:
|
||||
cpu_s = "251C";
|
||||
break;
|
||||
case STM32MP251D_PART_NB:
|
||||
cpu_s = "251D";
|
||||
break;
|
||||
case STM32MP251F_PART_NB:
|
||||
cpu_s = "251F";
|
||||
break;
|
||||
case STM32MP253A_PART_NB:
|
||||
cpu_s = "253A";
|
||||
break;
|
||||
case STM32MP253C_PART_NB:
|
||||
cpu_s = "253C";
|
||||
break;
|
||||
case STM32MP253D_PART_NB:
|
||||
cpu_s = "253D";
|
||||
break;
|
||||
case STM32MP253F_PART_NB:
|
||||
cpu_s = "253F";
|
||||
break;
|
||||
case STM32MP255A_PART_NB:
|
||||
cpu_s = "255A";
|
||||
break;
|
||||
case STM32MP255C_PART_NB:
|
||||
cpu_s = "255C";
|
||||
break;
|
||||
case STM32MP255D_PART_NB:
|
||||
cpu_s = "255D";
|
||||
break;
|
||||
case STM32MP255F_PART_NB:
|
||||
cpu_s = "255F";
|
||||
break;
|
||||
case STM32MP257A_PART_NB:
|
||||
cpu_s = "257A";
|
||||
break;
|
||||
case STM32MP257C_PART_NB:
|
||||
cpu_s = "257C";
|
||||
break;
|
||||
case STM32MP257D_PART_NB:
|
||||
cpu_s = "257D";
|
||||
break;
|
||||
case STM32MP257F_PART_NB:
|
||||
cpu_s = "257F";
|
||||
break;
|
||||
default:
|
||||
cpu_s = "????";
|
||||
break;
|
||||
}
|
||||
|
||||
/* Package */
|
||||
switch (get_cpu_package()) {
|
||||
case STM32MP25_PKG_CUSTOM:
|
||||
pkg = "XX";
|
||||
break;
|
||||
case STM32MP25_PKG_AL_VFBGA361:
|
||||
pkg = "AL";
|
||||
break;
|
||||
case STM32MP25_PKG_AK_VFBGA424:
|
||||
pkg = "AK";
|
||||
break;
|
||||
case STM32MP25_PKG_AI_TFBGA436:
|
||||
pkg = "AI";
|
||||
break;
|
||||
default:
|
||||
pkg = "??";
|
||||
break;
|
||||
}
|
||||
|
||||
/* REVISION */
|
||||
switch (stm32mp_get_chip_version()) {
|
||||
case STM32MP2_REV_A:
|
||||
cpu_r = "A";
|
||||
break;
|
||||
case STM32MP2_REV_B:
|
||||
cpu_r = "B";
|
||||
break;
|
||||
case STM32MP2_REV_X:
|
||||
cpu_r = "X";
|
||||
break;
|
||||
case STM32MP2_REV_Y:
|
||||
cpu_r = "Y";
|
||||
break;
|
||||
case STM32MP2_REV_Z:
|
||||
cpu_r = "Z";
|
||||
break;
|
||||
default:
|
||||
cpu_r = "?";
|
||||
break;
|
||||
}
|
||||
|
||||
snprintf(name, STM32_SOC_NAME_SIZE,
|
||||
"STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r);
|
||||
}
|
||||
|
||||
void stm32mp_print_cpuinfo(void)
|
||||
{
|
||||
char name[STM32_SOC_NAME_SIZE];
|
||||
|
||||
stm32mp_get_soc_name(name);
|
||||
NOTICE("CPU: %s\n", name);
|
||||
}
|
||||
|
||||
void stm32mp_print_boardinfo(void)
|
||||
{
|
||||
uint32_t board_id = 0U;
|
||||
|
||||
if (stm32_get_otp_value(BOARD_ID_OTP, &board_id) != 0) {
|
||||
return;
|
||||
}
|
||||
|
||||
if (board_id != 0U) {
|
||||
stm32_display_board_info(board_id);
|
||||
}
|
||||
}
|
||||
|
||||
uintptr_t stm32_get_bkpr_boot_mode_addr(void)
|
||||
{
|
||||
return tamp_bkpr(BKPR_BOOT_MODE);
|
||||
}
|
||||
31
plat/st/stm32mp2/stm32mp2_syscfg.c
Normal file
31
plat/st/stm32mp2/stm32mp2_syscfg.c
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* Copyright (c) 2024, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
#include <stm32mp2_private.h>
|
||||
|
||||
/*
|
||||
* SYSCFG register offsets (base relative)
|
||||
*/
|
||||
#define SYSCFG_DEVICEID 0x6400U
|
||||
|
||||
/*
|
||||
* SYSCFG_DEVICEID Register
|
||||
*/
|
||||
#define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK_32(11, 0)
|
||||
|
||||
/*
|
||||
* @brief Get device ID from SYSCFG registers.
|
||||
* @retval device ID (DEV_ID).
|
||||
*/
|
||||
uint32_t stm32mp_syscfg_get_chip_dev_id(void)
|
||||
{
|
||||
return mmio_read_32(SYSCFG_BASE + SYSCFG_DEVICEID) & SYSCFG_DEVICEID_DEV_ID_MASK;
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue