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Prevent colliding identifiers
There was a collision between the name of the typedef in the CASSERT and something else, so we make the name of the typedef unique to the invocation of DEFFINE_SVC_UUID2 by appending the name that's passed into the macro. This eliminates the following MISRA violation: bl1/bl1_main.c:233:[MISRA C-2012 Rule 5.6 (required)] Identifier "invalid_svc_uuid" is already used to represent a typedef. This also resolves MISRA rule 5.9. These renamings are as follows: * tzram -> secram. This matches the function call name as it has sec_mem in it's name * fw_config_base -> config_base. This file does not mess with hw_conig, so there's little chance of confusion Change-Id: I8734ba0956140c8e29b89d0596d10d61a6ef351e Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
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3 changed files with 12 additions and 11 deletions
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@ -122,7 +122,8 @@
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*/
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*/
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#define DEFINE_SVC_UUID2(_name, _tl, _tm, _th, _cl, _ch, \
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#define DEFINE_SVC_UUID2(_name, _tl, _tm, _th, _cl, _ch, \
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_n0, _n1, _n2, _n3, _n4, _n5) \
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_n0, _n1, _n2, _n3, _n4, _n5) \
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CASSERT((uint32_t)(_tl) != (uint32_t)SMC_UNK, invalid_svc_uuid);\
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CASSERT((uint32_t)(_tl) != (uint32_t)SMC_UNK, \
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invalid_svc_uuid_##_name); \
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static const uuid_t _name = { \
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static const uuid_t _name = { \
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{((_tl) >> 24) & 0xFF, \
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{((_tl) >> 24) & 0xFF, \
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((_tl) >> 16) & 0xFF, \
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((_tl) >> 16) & 0xFF, \
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@ -27,7 +27,7 @@
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static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
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static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
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/* Base address of fw_config received from BL1 */
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/* Base address of fw_config received from BL1 */
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static uintptr_t fw_config_base;
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static uintptr_t config_base;
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/*
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/*
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* Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is
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* Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is
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@ -66,7 +66,7 @@ void arm_bl2_early_platform_setup(uintptr_t fw_config,
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/* Setup the BL2 memory layout */
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/* Setup the BL2 memory layout */
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bl2_tzram_layout = *mem_layout;
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bl2_tzram_layout = *mem_layout;
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fw_config_base = fw_config;
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config_base = fw_config;
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/* Initialise the IO layer and register platform IO devices */
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/* Initialise the IO layer and register platform IO devices */
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plat_arm_io_setup();
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plat_arm_io_setup();
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@ -152,7 +152,7 @@ void bl2_plat_arch_setup(void)
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arm_bl2_plat_arch_setup();
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arm_bl2_plat_arch_setup();
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/* Fill the properties struct with the info from the config dtb */
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/* Fill the properties struct with the info from the config dtb */
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fconf_populate("FW_CONFIG", fw_config_base);
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fconf_populate("FW_CONFIG", config_base);
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/* TB_FW_CONFIG was also loaded by BL1 */
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/* TB_FW_CONFIG was also loaded by BL1 */
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tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID);
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tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID);
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@ -83,8 +83,8 @@ int bl1_plat_mem_check(uintptr_t mem_base, unsigned int mem_size,
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*/
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*/
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int bl1_plat_handle_post_image_load(unsigned int image_id)
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int bl1_plat_handle_post_image_load(unsigned int image_id)
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{
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{
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meminfo_t *bl2_tzram_layout;
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meminfo_t *bl2_secram_layout;
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meminfo_t *bl1_tzram_layout;
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meminfo_t *bl1_secram_layout;
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image_desc_t *image_desc;
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image_desc_t *image_desc;
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entry_point_info_t *ep_info;
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entry_point_info_t *ep_info;
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@ -99,7 +99,7 @@ int bl1_plat_handle_post_image_load(unsigned int image_id)
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ep_info = &image_desc->ep_info;
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ep_info = &image_desc->ep_info;
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/* Find out how much free trusted ram remains after BL1 load */
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/* Find out how much free trusted ram remains after BL1 load */
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bl1_tzram_layout = bl1_plat_sec_mem_layout();
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bl1_secram_layout = bl1_plat_sec_mem_layout();
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/*
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/*
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* Create a new layout of memory for BL2 as seen by BL1 i.e.
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* Create a new layout of memory for BL2 as seen by BL1 i.e.
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@ -108,14 +108,14 @@ int bl1_plat_handle_post_image_load(unsigned int image_id)
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* to BL2. BL2 will read the memory layout before using its
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* to BL2. BL2 will read the memory layout before using its
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* memory for other purposes.
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* memory for other purposes.
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*/
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*/
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bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->total_base;
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bl2_secram_layout = (meminfo_t *) bl1_secram_layout->total_base;
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bl1_calc_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout);
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bl1_calc_bl2_mem_layout(bl1_secram_layout, bl2_secram_layout);
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ep_info->args.arg1 = (uintptr_t)bl2_tzram_layout;
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ep_info->args.arg1 = (uintptr_t)bl2_secram_layout;
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VERBOSE("BL1: BL2 memory layout address = %p\n",
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VERBOSE("BL1: BL2 memory layout address = %p\n",
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(void *) bl2_tzram_layout);
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(void *) bl2_secram_layout);
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return 0;
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return 0;
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}
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}
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