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feat(intel): support QSPI ECC Linux for Agilex

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Add QSPI ECC new opcodes for Linux to access to SDM register

Change-Id: I548e30340320ae2c2c9d60d20b218ee844516d64
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
This commit is contained in:
Sieu Mun Tang 2023-12-22 00:43:57 +08:00
parent 6cf16b3682
commit d6ae69c8c6
3 changed files with 34 additions and 19 deletions
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15
plat/intel/soc/agilex/include/agilex_system_manager.h
View file

@ -143,6 +143,18 @@
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_8 0x278 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_8 0x278
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_9 0x27C #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_9 0x27C
/* QSPI ECC from SDM register */
#define SOCFPGA_ECC_QSPI_CTRL 0x08
#define SOCFPGA_ECC_QSPI_ERRINTEN 0x10
#define SOCFPGA_ECC_QSPI_ERRINTENS 0x14
#define SOCFPGA_ECC_QSPI_ERRINTENR 0x18
#define SOCFPGA_ECC_QSPI_INTMODE 0x1C
#define SOCFPGA_ECC_QSPI_INTSTAT 0x20
#define SOCFPGA_ECC_QSPI_INTTEST 0x24
#define SOCFPGA_ECC_QSPI_ECC_ACCCTRL 0x78
#define SOCFPGA_ECC_QSPI_ECC_STARTACC 0x7C
#define SOCFPGA_ECC_QSPI_ECC_WDCTRL 0x80
#define DMA0_STREAM_CTRL_REG 0x10D1217C #define DMA0_STREAM_CTRL_REG 0x10D1217C
#define DMA1_STREAM_CTRL_REG 0x10D12180 #define DMA1_STREAM_CTRL_REG 0x10D12180
#define SDM_STREAM_CTRL_REG 0x10D12184 #define SDM_STREAM_CTRL_REG 0x10D12184
@ -183,6 +195,9 @@
#define RMMUSECSID_REG_VAL BIT(5) #define RMMUSECSID_REG_VAL BIT(5)
/* Macros */ /* Macros */
#define SOCFPGA_ECC_QSPI(_reg) (SOCFPGA_ECC_QSPI_REG_BASE \
+ (SOCFPGA_ECC_QSPI_##_reg))
#define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \
+ (SOCFPGA_SYSMGR_##_reg)) + (SOCFPGA_SYSMGR_##_reg))

1
plat/intel/soc/agilex/include/socfpga_plat_def.h
View file

@ -34,6 +34,7 @@
#define SOCFPGA_MEMCTRL_REG_BASE 0xf8011100 #define SOCFPGA_MEMCTRL_REG_BASE 0xf8011100
#define SOCFPGA_RSTMGR_REG_BASE 0xffd11000 #define SOCFPGA_RSTMGR_REG_BASE 0xffd11000
#define SOCFPGA_SYSMGR_REG_BASE 0xffd12000 #define SOCFPGA_SYSMGR_REG_BASE 0xffd12000
#define SOCFPGA_ECC_QSPI_REG_BASE 0xffa22000
#define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000 #define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000
#define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100 #define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100

5
plat/intel/soc/common/socfpga_sip_svc.c
View file

@ -423,6 +423,7 @@ static int is_out_of_sec_range(uint64_t reg_addr)
case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */ case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */
case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */ case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */
case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */ case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */
#endif
case(SOCFPGA_ECC_QSPI(CTRL)): /* ECC_QSPI_CTRL */ case(SOCFPGA_ECC_QSPI(CTRL)): /* ECC_QSPI_CTRL */
case(SOCFPGA_ECC_QSPI(ERRINTEN)): /* ECC_QSPI_ERRINTEN */ case(SOCFPGA_ECC_QSPI(ERRINTEN)): /* ECC_QSPI_ERRINTEN */
case(SOCFPGA_ECC_QSPI(ERRINTENS)): /* ECC_QSPI_ERRINTENS */ case(SOCFPGA_ECC_QSPI(ERRINTENS)): /* ECC_QSPI_ERRINTENS */
@ -434,7 +435,7 @@ static int is_out_of_sec_range(uint64_t reg_addr)
case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */
case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */
return 0; return 0;
#endif
default: default:
break; break;
} }
@ -462,12 +463,10 @@ uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val,
} }
switch (reg_addr) { switch (reg_addr) {
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */
case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */
mmio_write_16(reg_addr, val); mmio_write_16(reg_addr, val);
break; break;
#endif
default: default:
mmio_write_32(reg_addr, val); mmio_write_32(reg_addr, val);
break; break;