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ARMv7: introduce Cortex-A5

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Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
This commit is contained in:
Etienne Carriere 2017-11-05 22:56:26 +01:00
parent e3148c2b53
commit d56a846121
2 changed files with 95 additions and 0 deletions
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20
include/lib/cpus/aarch32/cortex_a5.h Normal file
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/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CORTEX_A5_H__
#define __CORTEX_A5_H__
/*******************************************************************************
* Cortex-A8 midr with version/revision set to 0
******************************************************************************/
#define CORTEX_A5_MIDR 0x410FC050
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
#define CORTEX_A5_ACTLR_SMP_BIT (1 << 6)
#endif /* __CORTEX_A5_H__ */

75
lib/cpus/aarch32/cortex_a5.S Normal file
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/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <assert_macros.S>
#include <cortex_a5.h>
#include <cpu_macros.S>
.macro assert_cache_enabled
#if ENABLE_ASSERTIONS
ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq)
#endif
.endm
func cortex_a5_disable_smp
ldcopr r0, ACTLR
bic r0, #CORTEX_A5_ACTLR_SMP_BIT
stcopr r0, ACTLR
isb
dsb sy
bx lr
endfunc cortex_a5_disable_smp
func cortex_a5_enable_smp
ldcopr r0, ACTLR
orr r0, #CORTEX_A5_ACTLR_SMP_BIT
stcopr r0, ACTLR
isb
bx lr
endfunc cortex_a5_enable_smp
func cortex_a5_reset_func
b cortex_a5_enable_smp
endfunc cortex_a5_reset_func
func cortex_a5_core_pwr_dwn
push {r12, lr}
assert_cache_enabled
/* Flush L1 cache */
mov r0, #DC_OP_CISW
bl dcsw_op_level1
/* Exit cluster coherency */
pop {r12, lr}
b cortex_a5_disable_smp
endfunc cortex_a5_core_pwr_dwn
func cortex_a5_cluster_pwr_dwn
push {r12, lr}
assert_cache_enabled
/* Flush L1 caches */
mov r0, #DC_OP_CISW
bl dcsw_op_level1
bl plat_disable_acp
/* Exit cluster coherency */
pop {r12, lr}
b cortex_a5_disable_smp
endfunc cortex_a5_cluster_pwr_dwn
declare_cpu_ops cortex_a5, CORTEX_A5_MIDR, \
cortex_a5_reset_func, \
cortex_a5_core_pwr_dwn, \
cortex_a5_cluster_pwr_dwn