diff --git a/plat/mediatek/drivers/pmic/mt6363/mt6363_psc.c b/plat/mediatek/drivers/pmic/mt6363/mt6363_psc.c new file mode 100644 index 000000000..d53d02feb --- /dev/null +++ b/plat/mediatek/drivers/pmic/mt6363/mt6363_psc.c @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2025, Mediatek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include +#include + +#include "registers.h" + +static struct spmi_device *sdev; + +static const struct pmic_psc_reg mt6363_psc_regs[] = { + PMIC_PSC_REG(RG_PWRHOLD, MT6363_PPCCTL0, 0), + PMIC_PSC_REG(RG_CRST, MT6363_PPCCTL1, 0), + PMIC_PSC_REG(RG_SMART_RST_SDN_EN, MT6363_STRUP_CON12, 1), + PMIC_PSC_REG(RG_SMART_RST_MODE, MT6363_STRUP_CON12, 2), +}; + +static int mt6363_psc_read_field(uint32_t reg, uint32_t *val, uint32_t mask, uint32_t shift) +{ + uint8_t rdata = 0; + int ret = 0; + + if (!val) + return -EINVAL; + if (!sdev) + return -ENODEV; + ret = spmi_ext_register_readl(sdev, reg, &rdata, 1); + if (ret < 0) + return ret; + + rdata &= (mask << shift); + *val = (rdata >> shift); + + return 0; +} + +static int mt6363_psc_write_field(uint32_t reg, uint32_t val, uint32_t mask, uint32_t shift) +{ + uint8_t org = 0; + int ret = 0; + + if (!sdev) + return -ENODEV; + ret = spmi_ext_register_readl(sdev, reg, &org, 1); + if (ret < 0) + return ret; + + org &= ~(mask << shift); + org |= (val << shift); + + ret = spmi_ext_register_writel(sdev, reg, &org, 1); + return ret; +} + +static const struct pmic_psc_config mt6363_psc_config = { + .read_field = mt6363_psc_read_field, + .write_field = mt6363_psc_write_field, + .regs = mt6363_psc_regs, + .reg_size = ARRAY_SIZE(mt6363_psc_regs), +}; + +static int mt6363_psc_init(void) +{ + sdev = get_spmi_device(SPMI_MASTER_1, SPMI_SLAVE_4); + if (!sdev) + ERROR("%s: get spmi device fail\n", __func__); + return pmic_psc_register(&mt6363_psc_config); +} + +MTK_PLAT_SETUP_0_INIT(mt6363_psc_init); + +#ifdef CONFIG_MTK_PMIC_SPT_SUPPORT +static int mt6363_spt_enable(void) +{ + /* Enable PMIC Self-Protection Timer(SPT) */ + return mt6363_psc_write_field(MT6363_RG_SELFWDT_EN_ADDR, MT6363_RG_SELFWDT_EN_MASK, + MT6363_RG_SELFWDT_EN_MASK, 0); +} + +MTK_PLAT_RUNTIME_INIT(mt6363_spt_enable); +#endif diff --git a/plat/mediatek/drivers/pmic/mt6363/registers.h b/plat/mediatek/drivers/pmic/mt6363/registers.h new file mode 100644 index 000000000..32c388c38 --- /dev/null +++ b/plat/mediatek/drivers/pmic/mt6363/registers.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025, Mediatek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT6363_REGISTER_H +#define MT6363_REGISTER_H + +/* PMIC Registers for PSC */ +#define MT6363_PPCCTL0 0xA08 +#define MT6363_PPCCTL1 0xA09 +#define MT6363_STRUP_CON12 0xA0F +#define MT6363_RG_SELFWDT_EN_ADDR 0xA14 +#define MT6363_RG_SELFWDT_EN_MASK 0x1 + +#endif /* MT6363_REGISTER_H */ diff --git a/plat/mediatek/drivers/pmic/mt6363/rules.mk b/plat/mediatek/drivers/pmic/mt6363/rules.mk new file mode 100644 index 000000000..7df7cfb08 --- /dev/null +++ b/plat/mediatek/drivers/pmic/mt6363/rules.mk @@ -0,0 +1,17 @@ +# +# Copyright (c) 2025, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +#Prologue, init variable +LOCAL_DIR := $(call GET_LOCAL_DIR) + +#Define your module name +MODULE := mt6363 + +#Add your source code here +LOCAL_SRCS-y := $(LOCAL_DIR)/${PMIC_CHIP}_psc.c + +#Epilogue, build as module +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/drivers/pmic/mt8196/pmic_lowpower_init.c b/plat/mediatek/drivers/pmic/mt8196/pmic_lowpower_init.c new file mode 100644 index 000000000..f4e0734c8 --- /dev/null +++ b/plat/mediatek/drivers/pmic/mt8196/pmic_lowpower_init.c @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2025, Mediatek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include +#include +#include + +#define MASTER_ID SPMI_MASTER_1 + +struct spmi_device *lowpower_sdev[SPMI_MAX_SLAVE_ID]; + +static const uint8_t lowpower_slvid_arr[] = { + MT6363_SLAVE, + MT6373_SLAVE, + MT6316_S6_SLAVE, + MT6316_S7_SLAVE, + MT6316_S8_SLAVE, + MT6316_S15_SLAVE, +}; + +static int pmic_lowpower_init(void) +{ + uint8_t i, slvid; + + for (i = 0; i < ARRAY_SIZE(lowpower_slvid_arr); i++) { + slvid = lowpower_slvid_arr[i]; + lowpower_sdev[slvid] = get_spmi_device(MASTER_ID, slvid); + if (!lowpower_sdev[slvid]) + return -ENODEV; + } + + /* MT6363 Deep idle, SODI3 */ + /* VREQ config by SCP owner in LK2 */ + PMIC_BUCK_SET_LP(MT6363, VBUCK4, HW2, true, OP_MODE_LP, HW_LP); + PMIC_BUCK_SET_LP(MT6363, VBUCK4, RC9, true, OP_MODE_MU, HW_ON); + PMIC_BUCK_SET_LP(MT6363, VS2, HW2, true, OP_MODE_LP, HW_LP); + PMIC_BUCK_SET_LP(MT6363, VS2, RC9, true, OP_MODE_MU, HW_ON); + PMIC_BUCK_SET_LP(MT6363, VS3, HW2, true, OP_MODE_LP, HW_LP); + PMIC_LDO_SET_LP(MT6363, VSRAM_CPUB, HW2, true, OP_MODE_LP, HW_LP); + PMIC_LDO_SET_LP(MT6363, VSRAM_CPUB, RC9, true, OP_MODE_MU, HW_ON); + PMIC_LDO_SET_LP(MT6363, VSRAM_CPUL, HW2, true, OP_MODE_LP, HW_LP); + PMIC_LDO_SET_LP(MT6363, VSRAM_CPUL, RC9, true, OP_MODE_MU, HW_ON); + PMIC_LDO_SET_LP(MT6363, VSRAM_APU, RC2, true, OP_MODE_MU, HW_OFF); + PMIC_LDO_SET_LP(MT6363, VSRAM_MODEM, HW2, true, OP_MODE_LP, HW_LP); + PMIC_LDO_SET_LP(MT6363, VSRAM_MODEM, RC9, true, OP_MODE_MU, HW_ON); + PMIC_LDO_SET_LP(MT6363, VA12_1, HW2, true, OP_MODE_LP, HW_LP); + PMIC_LDO_SET_LP(MT6363, VA12_1, RC9, true, OP_MODE_MU, HW_ON); + PMIC_LDO_SET_LP(MT6363, VA12_2, HW2, true, OP_MODE_LP, HW_LP); + PMIC_LDO_SET_LP(MT6363, VA12_2, RC9, true, OP_MODE_MU, HW_ON); + PMIC_LDO_SET_LP(MT6363, VUFS18, HW2, true, OP_MODE_LP, HW_LP); + PMIC_LDO_SET_LP(MT6363, VUFS18, RC9, true, OP_MODE_MU, HW_ON); + PMIC_LDO_SET_LP(MT6363, VUFS12, HW2, true, OP_MODE_LP, HW_LP); + + /* MT6373 Deep idle, SODI3 */ + PMIC_BUCK_SET_LP(MT6373, VBUCK4, HW2, true, OP_MODE_LP, HW_OFF); + PMIC_BUCK_SET_LP(MT6373, VBUCK5, HW2, true, OP_MODE_LP, HW_OFF); + PMIC_BUCK_SET_LP(MT6373, VBUCK6, HW2, true, OP_MODE_LP, HW_LP); + PMIC_LDO_SET_LP(MT6373, VUSB, HW2, true, OP_MODE_LP, HW_LP); + + /* MT6316 Deep idle, SODI3 */ + PMIC_SLVID_BUCK_SET_LP(MT6316, S8, VBUCK1, HW2, true, OP_MODE_LP, HW_LP); + PMIC_SLVID_BUCK_SET_LP(MT6316, S6, VBUCK3, HW2, true, OP_MODE_LP, HW_ONLV); + return 0; +} + +MTK_PLAT_SETUP_0_INIT(pmic_lowpower_init); diff --git a/plat/mediatek/drivers/pmic/mt8196/pmic_shutdown_cfg.c b/plat/mediatek/drivers/pmic/mt8196/pmic_shutdown_cfg.c new file mode 100644 index 000000000..8c2bde5a2 --- /dev/null +++ b/plat/mediatek/drivers/pmic/mt8196/pmic_shutdown_cfg.c @@ -0,0 +1,291 @@ +/* + * Copyright (c) 2025, Mediatek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include +#include +#include + +#define MASTER_ID SPMI_MASTER_1 + +#ifndef MT8678_PMIC_SUPPORT +/* MT6316 will automatically disable wdt in poffs */ +#define MT6316_PMIC_RG_SHUTDOWN_SRC_SEL_ADDR 0x408 +#define MT6316_PMIC_RG_SHUTDOWN_SRC_SEL_MASK 0x1 +#define MT6316_PMIC_RG_SHUTDOWN_SRC_SEL_SHIFT 1 +#else +/* MT6319 will automatically disable wdt in poffs */ +#define MT6319_TOP_RST_MISC_CLR 0x128 +#define MT6319_PMIC_RG_SHUTDOWN_SRC_SEL_ADDR 0x138 +#define MT6319_PMIC_RG_SHUTDOWN_SRC_SEL_MASK 0x1 +#define MT6319_PMIC_RG_SHUTDOWN_SRC_SEL_SHIFT 2 +#endif + +#define MT6373_TOP_RST_MISC1_CLR 0x13B +#define MT6373_PMIC_RG_SHUTDOWN_SRC_SEL_ADDR 0x408 +#define MT6373_PMIC_RG_SHUTDOWN_SRC_SEL_MASK 0x1 +#define MT6373_PMIC_RG_SHUTDOWN_SRC_SEL_SHIFT 1 + +#define MT6685_TOP_RST_MISC_CLR 0x129 +#define MT6685_PMIC_RG_SHUTDOWN_SRC_SEL_ADDR 0x408 +#define MT6685_PMIC_RG_SHUTDOWN_SRC_SEL_MASK 0x1 +#define MT6685_PMIC_RG_SHUTDOWN_SRC_SEL_SHIFT 1 + +struct spmi_device *sdev_arr[SPMI_MAX_SLAVE_ID]; + +struct cfg_t { + uint8_t slvid; + uint32_t addr; + uint32_t shutdown_src_addr; + uint32_t shutdown_src_mask; + uint32_t shutdown_src_shift; + uint8_t val; +}; + +#ifndef MT8678_PMIC_SUPPORT +static const struct cfg_t cfg_arr[] = { + { + .slvid = SPMI_SLAVE_6, + .addr = 0, + .shutdown_src_addr = MT6316_PMIC_RG_SHUTDOWN_SRC_SEL_ADDR, + .shutdown_src_mask = MT6316_PMIC_RG_SHUTDOWN_SRC_SEL_MASK, + .shutdown_src_shift = MT6316_PMIC_RG_SHUTDOWN_SRC_SEL_SHIFT, + .val = 0x1 + }, { + .slvid = SPMI_SLAVE_7, + .addr = 0, + .shutdown_src_addr = MT6316_PMIC_RG_SHUTDOWN_SRC_SEL_ADDR, + .shutdown_src_mask = MT6316_PMIC_RG_SHUTDOWN_SRC_SEL_MASK, + .shutdown_src_shift = MT6316_PMIC_RG_SHUTDOWN_SRC_SEL_SHIFT, + .val = 0x1 + }, { + .slvid = SPMI_SLAVE_8, + .addr = 0, + .shutdown_src_addr = MT6316_PMIC_RG_SHUTDOWN_SRC_SEL_ADDR, + .shutdown_src_mask = MT6316_PMIC_RG_SHUTDOWN_SRC_SEL_MASK, + .shutdown_src_shift = MT6316_PMIC_RG_SHUTDOWN_SRC_SEL_SHIFT, + .val = 0x1 + }, { + .slvid = SPMI_SLAVE_15, + .addr = 0, + .shutdown_src_addr = MT6316_PMIC_RG_SHUTDOWN_SRC_SEL_ADDR, + .shutdown_src_mask = MT6316_PMIC_RG_SHUTDOWN_SRC_SEL_MASK, + .shutdown_src_shift = MT6316_PMIC_RG_SHUTDOWN_SRC_SEL_SHIFT, + .val = 0x1 + }, { + .slvid = SPMI_SLAVE_5, + .addr = MT6373_TOP_RST_MISC1_CLR, + .shutdown_src_addr = MT6373_PMIC_RG_SHUTDOWN_SRC_SEL_ADDR, + .shutdown_src_mask = MT6373_PMIC_RG_SHUTDOWN_SRC_SEL_MASK, + .shutdown_src_shift = MT6373_PMIC_RG_SHUTDOWN_SRC_SEL_SHIFT, + .val = 0x1 + }, { + .slvid = SPMI_SLAVE_9, + .addr = MT6685_TOP_RST_MISC_CLR, + .shutdown_src_addr = MT6685_PMIC_RG_SHUTDOWN_SRC_SEL_ADDR, + .shutdown_src_mask = MT6685_PMIC_RG_SHUTDOWN_SRC_SEL_MASK, + .shutdown_src_shift = MT6685_PMIC_RG_SHUTDOWN_SRC_SEL_SHIFT, + .val = 0x1 + } +}; +#else /* MT8678_PMIC_SUPPORT */ +static const struct cfg_t cfg_arr[] = { + { + .slvid = SPMI_SLAVE_6, + .addr = MT6319_TOP_RST_MISC_CLR, + .shutdown_src_addr = MT6319_PMIC_RG_SHUTDOWN_SRC_SEL_ADDR, + .shutdown_src_mask = MT6319_PMIC_RG_SHUTDOWN_SRC_SEL_MASK, + .shutdown_src_shift = MT6319_PMIC_RG_SHUTDOWN_SRC_SEL_SHIFT, + .val = 0x1 + }, { + .slvid = SPMI_SLAVE_7, + .addr = MT6319_TOP_RST_MISC_CLR, + .shutdown_src_addr = MT6319_PMIC_RG_SHUTDOWN_SRC_SEL_ADDR, + .shutdown_src_mask = MT6319_PMIC_RG_SHUTDOWN_SRC_SEL_MASK, + .shutdown_src_shift = MT6319_PMIC_RG_SHUTDOWN_SRC_SEL_SHIFT, + .val = 0x1 + }, { + .slvid = SPMI_SLAVE_8, + .addr = MT6319_TOP_RST_MISC_CLR, + .shutdown_src_addr = MT6319_PMIC_RG_SHUTDOWN_SRC_SEL_ADDR, + .shutdown_src_mask = MT6319_PMIC_RG_SHUTDOWN_SRC_SEL_MASK, + .shutdown_src_shift = MT6319_PMIC_RG_SHUTDOWN_SRC_SEL_SHIFT, + .val = 0x1 + }, { + .slvid = SPMI_SLAVE_15, + .addr = MT6319_TOP_RST_MISC_CLR, + .shutdown_src_addr = MT6319_PMIC_RG_SHUTDOWN_SRC_SEL_ADDR, + .shutdown_src_mask = MT6319_PMIC_RG_SHUTDOWN_SRC_SEL_MASK, + .shutdown_src_shift = MT6319_PMIC_RG_SHUTDOWN_SRC_SEL_SHIFT, + .val = 0x1 + }, { + .slvid = SPMI_SLAVE_5, + .addr = MT6373_TOP_RST_MISC1_CLR, + .shutdown_src_addr = MT6373_PMIC_RG_SHUTDOWN_SRC_SEL_ADDR, + .shutdown_src_mask = MT6373_PMIC_RG_SHUTDOWN_SRC_SEL_MASK, + .shutdown_src_shift = MT6373_PMIC_RG_SHUTDOWN_SRC_SEL_SHIFT, + .val = 0x1 + }, { + .slvid = SPMI_SLAVE_9, + .addr = MT6685_TOP_RST_MISC_CLR, + .shutdown_src_addr = MT6685_PMIC_RG_SHUTDOWN_SRC_SEL_ADDR, + .shutdown_src_mask = MT6685_PMIC_RG_SHUTDOWN_SRC_SEL_MASK, + .shutdown_src_shift = MT6685_PMIC_RG_SHUTDOWN_SRC_SEL_SHIFT, + .val = 0x1 + } +}; +#endif /* MT8678_PMIC_SUPPORT */ + +#define MT6316_TOP_ANA_KEY 0x3AA +#define MT6316_PMIC_RG_VI075_SINK_CUR_ADDR 0x994 +#define MT6316_PMIC_RG_VI075_SINK_CUR_MASK 0xF +#define MT6316_PMIC_RG_VI075_SINK_CUR_SHIFT 4 +#define MT6316_PMIC_RG_PSEQ_ELR_RSV2_ADDR 0xA2C +#define MT6316_PMIC_RG_PSEQ_ELR_RSV2_MASK 0x7 +#define MT6316_PMIC_RG_PSEQ_ELR_RSV2_SHIFT 5 +#define PSEQ_ELR_RSV2_VAL_MASK_1 0x3 +#define PSEQ_ELR_RSV2_VAL_MASK_2 0x1 +#define VI075_SINK_CUR_SOURCE_1 0x5 +#define VI075_SINK_CUR_SOURCE_2 0 +#define VI075_SINK_CUR_SOURCE_3 0xB +#define ARRAY_LENGTH_MAX 2 + +#ifndef MT8678_PMIC_SUPPORT +static void mt6316_key_lock_check(struct spmi_device *mt6316_dev, uint16_t key) +{ + int i, ret; + uint16_t rdata; + uint8_t work_val[ARRAY_LENGTH_MAX]; + uint8_t wdata[ARRAY_LENGTH_MAX]; + + for (i = 0; i < 2; i++) { + ret = spmi_ext_register_readl(mt6316_dev, key, &work_val[0], 2); + if (ret < 0) { + INFO("[%s]: read fail, addr = 0x%x, ret = %d\n" + , __func__, key, ret); + i = 0; + continue; + } + rdata = work_val[0] | (work_val[1] << 8); + + if (rdata != 0) { + INFO("[%s] lock fail, addr = 0x%x, rdata = 0x%x.\n" + , __func__, key, rdata); + wdata[0] = 0; + wdata[1] = 0; + spmi_ext_register_writel(mt6316_dev, key, &wdata[0], 2); + i = 0; + } + } +} + +static void wk_vio075_sink_cur(struct spmi_device *mt6316_dev, unsigned char en_seq_off) +{ + uint8_t rval, wval; + int ret; + uint8_t buf[ARRAY_LENGTH_MAX]; + + ret = spmi_ext_register_readl(mt6316_dev, MT6316_PMIC_RG_PSEQ_ELR_RSV2_ADDR, &rval, 1); + if (ret < 0) + return; + rval = (rval >> MT6316_PMIC_RG_PSEQ_ELR_RSV2_SHIFT) & MT6316_PMIC_RG_PSEQ_ELR_RSV2_MASK; + + if (!(rval & PSEQ_ELR_RSV2_VAL_MASK_1)) { + wval = VI075_SINK_CUR_SOURCE_1; + } else if (rval & PSEQ_ELR_RSV2_VAL_MASK_2) { + if (en_seq_off) + wval = VI075_SINK_CUR_SOURCE_2; + else + wval = VI075_SINK_CUR_SOURCE_3; + } else { + wval = VI075_SINK_CUR_SOURCE_2; + } + + buf[0] = 0xDC; + buf[1] = 0xF1; + spmi_ext_register_writel(mt6316_dev, + MT6316_TOP_ANA_KEY, + &buf[0], 2); /* unlock TOP_ANA key */ + spmi_ext_register_writel_field(mt6316_dev, + MT6316_PMIC_RG_VI075_SINK_CUR_ADDR, wval, + MT6316_PMIC_RG_VI075_SINK_CUR_MASK, + MT6316_PMIC_RG_VI075_SINK_CUR_SHIFT); + buf[0] = 0; + buf[1] = 0; + spmi_ext_register_writel(mt6316_dev, + MT6316_TOP_ANA_KEY, + &buf[0], 2); /* lock TOP_ANA key */ + mt6316_key_lock_check(mt6316_dev, MT6316_TOP_ANA_KEY); +} +#endif + +static int pmic_shutdown_cfg_init(void) +{ + uint8_t i, slvid; + + for (i = 0; i < ARRAY_SIZE(cfg_arr); i++) { + slvid = cfg_arr[i].slvid; + if (sdev_arr[slvid] != NULL) + continue; + sdev_arr[slvid] = get_spmi_device(MASTER_ID, slvid); + if (!sdev_arr[slvid]) + return -ENODEV; + } + return 0; +} +MTK_PLAT_SETUP_0_INIT(pmic_shutdown_cfg_init); + +int pmic_shutdown_cfg(void) +{ + int ret; + uint8_t i, slvid; + uint32_t addr; + uint8_t val; + + for (i = 0; i < ARRAY_SIZE(cfg_arr); i++) { + slvid = cfg_arr[i].slvid; + if (!sdev_arr[slvid]) + return -ENODEV; + /* mt6316 vio075 sink current adjustment */ + if ((slvid >= SPMI_SLAVE_6 && slvid <= SPMI_SLAVE_8) || slvid == SPMI_SLAVE_15) + wk_vio075_sink_cur(sdev_arr[slvid], 1); + addr = cfg_arr[i].addr; + val = cfg_arr[i].val; + /* Disable WDTRSTB_EN */ + if (addr) { + ret = spmi_ext_register_writel(sdev_arr[slvid], addr, &val, 1); + if (ret < 0) + return ret; + } + + /* set RG_SHUTDOWN_SRC_SEL to 1, shutdown PMIC by SPMI command */ + spmi_ext_register_writel_field(sdev_arr[slvid], + cfg_arr[i].shutdown_src_addr, 1, + cfg_arr[i].shutdown_src_mask, + cfg_arr[i].shutdown_src_shift); + } + return 1; /* 1: use spmi_command_shutdown API */ +} + +/* shutdown PMIC by SPMI command */ +int spmi_shutdown(void) +{ + struct spmi_device *mt6363_sdev = get_spmi_device(SPMI_MASTER_1, SPMI_SLAVE_4); + + if (!mt6363_sdev) + return -ENODEV; + + /* set RG_SHUTDOWN_SRC_SEL to 1 */ + spmi_ext_register_writel_field(mt6363_sdev, 0x408, 1, 0x1, 1); + spmi_command_shutdown(SPMI_MASTER_P_1, mt6363_sdev, 0x800); + spmi_command_shutdown(SPMI_MASTER_1, mt6363_sdev, 0x800); + + return 0; +} diff --git a/plat/mediatek/drivers/pmic/mt8196/pmic_swap_api.c b/plat/mediatek/drivers/pmic/mt8196/pmic_swap_api.c new file mode 100644 index 000000000..e7a02ee1d --- /dev/null +++ b/plat/mediatek/drivers/pmic/mt8196/pmic_swap_api.c @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025, Mediatek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +/* No need to check second pmic mt6373 */ +bool is_second_pmic_pp_swap(void) +{ + return false; +} diff --git a/plat/mediatek/drivers/pmic/pmic_common_swap_api.c b/plat/mediatek/drivers/pmic/pmic_common_swap_api.c new file mode 100644 index 000000000..496017c3a --- /dev/null +++ b/plat/mediatek/drivers/pmic/pmic_common_swap_api.c @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025, Mediatek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#pragma weak is_second_pmic_pp_swap + +bool is_second_pmic_pp_swap(void) +{ + return false; +} diff --git a/plat/mediatek/drivers/pmic/pmic_psc.c b/plat/mediatek/drivers/pmic/pmic_psc.c new file mode 100644 index 000000000..ff4f7e346 --- /dev/null +++ b/plat/mediatek/drivers/pmic/pmic_psc.c @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2025, Mediatek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#ifdef CONFIG_MTK_PMIC_SHUTDOWN_CFG +#include +#endif + +#define ERR_INVALID_ARGS -EINVAL +#define ERR_NOT_CONFIGURED -ENODEV + +static const struct pmic_psc_config *pmic_psc; + +static uint32_t read_pmic_psc_reg(enum pmic_psc_reg_name reg_name) +{ + uint32_t val = 0; + const struct pmic_psc_reg *reg; + + if (reg_name >= pmic_psc->reg_size) + return 0; + + reg = &pmic_psc->regs[reg_name]; + pmic_psc->read_field(reg->reg_addr, &val, reg->reg_mask, reg->reg_shift); + return val; +} + +static int set_pmic_psc_reg(enum pmic_psc_reg_name reg_name) +{ + const struct pmic_psc_reg *reg; + + if (reg_name >= pmic_psc->reg_size) + return ERR_INVALID_ARGS; + + reg = &pmic_psc->regs[reg_name]; + pmic_psc->write_field(reg->reg_addr, 1, reg->reg_mask, reg->reg_shift); + return 0; +} + +static int clr_pmic_psc_reg(enum pmic_psc_reg_name reg_name) +{ + const struct pmic_psc_reg *reg; + + if (reg_name >= pmic_psc->reg_size) + return ERR_INVALID_ARGS; + + reg = &pmic_psc->regs[reg_name]; + pmic_psc->write_field(reg->reg_addr, 0, reg->reg_mask, reg->reg_shift); + return 0; +} + +int enable_pmic_smart_reset(bool enable) +{ + if (!pmic_psc) + return ERR_NOT_CONFIGURED; + if (enable) + set_pmic_psc_reg(RG_SMART_RST_MODE); + else + clr_pmic_psc_reg(RG_SMART_RST_MODE); + return 0; +} + +int enable_pmic_smart_reset_shutdown(bool enable) +{ + if (!pmic_psc) + return ERR_NOT_CONFIGURED; + if (enable) + set_pmic_psc_reg(RG_SMART_RST_SDN_EN); + else + clr_pmic_psc_reg(RG_SMART_RST_SDN_EN); + return 0; +} + +int platform_cold_reset(void) +{ + if (!pmic_psc) + return ERR_NOT_CONFIGURED; + /* Some PMICs may not support cold reset */ + if (!pmic_psc->regs[RG_CRST].reg_addr) + return ERR_NOT_CONFIGURED; + set_pmic_psc_reg(RG_CRST); + return 0; +} + +int platform_power_hold(bool hold) +{ + int use_spmi_cmd_sdn = 0; + + if (!pmic_psc) + return ERR_NOT_CONFIGURED; + if (hold) + set_pmic_psc_reg(RG_PWRHOLD); + else { +#ifdef CONFIG_MTK_PMIC_SHUTDOWN_CFG + use_spmi_cmd_sdn = pmic_shutdown_cfg(); +#endif + if (use_spmi_cmd_sdn == 1) + spmi_shutdown(); + else + clr_pmic_psc_reg(RG_PWRHOLD); + } + return 0; +} + +int pmic_psc_register(const struct pmic_psc_config *psc) +{ + if (!psc || !psc->regs || !psc->read_field || !psc->write_field) + return ERR_INVALID_ARGS; + pmic_psc = psc; + INFO("POWER_HOLD=0x%x\n", read_pmic_psc_reg(RG_PWRHOLD)); + return 0; +} diff --git a/plat/mediatek/drivers/pmic/rules.mk b/plat/mediatek/drivers/pmic/rules.mk index e408b034f..0280df803 100644 --- a/plat/mediatek/drivers/pmic/rules.mk +++ b/plat/mediatek/drivers/pmic/rules.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# Copyright (c) 2022-2025, MediaTek Inc. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -8,8 +8,24 @@ LOCAL_DIR := $(call GET_LOCAL_DIR) MODULE := pmic +ifneq (${PMIC_CHIP}, mt6363) LOCAL_SRCS-y += ${LOCAL_DIR}/pmic.c - PLAT_INCLUDES += -I${LOCAL_DIR}/ +else +LOCAL_SRCS-y := ${LOCAL_DIR}/pmic_psc.c +LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_common_swap_api.c +LOCAL_SRCS-${CONFIG_MTK_PMIC_LOWPOWER} += ${LOCAL_DIR}/${MTK_SOC}/pmic_lowpower_init.c +LOCAL_SRCS-${CONFIG_MTK_PMIC_LOWPOWER} += ${LOCAL_DIR}/${MTK_SOC}/pmic_swap_api.c +LOCAL_SRCS-${CONFIG_MTK_PMIC_SHUTDOWN_CFG} += ${LOCAL_DIR}/${MTK_SOC}/pmic_shutdown_cfg.c +endif $(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) +$(eval $(call add_defined_option,CONFIG_MTK_PMIC_SPT_SUPPORT)) +$(eval $(call add_defined_option,CONFIG_MTK_PMIC_SHUTDOWN_CFG)) + +#Include sub rules.mk +ifneq (${PMIC_CHIP},) +SUB_RULES-y := $(LOCAL_DIR)/$(PMIC_CHIP) +#Expand sub rules.mk +$(eval $(call INCLUDE_MAKEFILE,$(SUB_RULES-y))) +endif diff --git a/plat/mediatek/include/drivers/pmic/mt6316_lowpower_reg.h b/plat/mediatek/include/drivers/pmic/mt6316_lowpower_reg.h new file mode 100644 index 000000000..fd35ac63d --- /dev/null +++ b/plat/mediatek/include/drivers/pmic/mt6316_lowpower_reg.h @@ -0,0 +1,263 @@ +/* + * Copyright (c) 2025, Mediatek Inc. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT6316_LOWPOWER_REG_H +#define MT6316_LOWPOWER_REG_H + +#define MT6316_RG_LDO_VDIG18_SW_OP_EN_ADDR 0x197 +#define MT6316_RG_LDO_VDIG18_HW0_OP_EN_ADDR 0x197 +#define MT6316_RG_LDO_VDIG18_HW2_OP_EN_ADDR 0x197 +#define MT6316_RG_LDO_VDIG18_RC0_OP_EN_ADDR 0x197 +#define MT6316_RG_LDO_VDIG18_BUCK_OP_EN_ADDR 0x197 +#define MT6316_RG_LDO_VDIG18_HW0_OP_MODE_ADDR 0x198 +#define MT6316_RG_LDO_VDIG18_HW2_OP_MODE_ADDR 0x198 +#define MT6316_RG_LDO_VDIG18_RC0_OP_MODE_ADDR 0x198 +#define MT6316_RG_LDO_VDIG18_BUCK_OP_MODE_ADDR 0x198 +#define MT6316_RG_VDIG18_PWROFF_OP_EN_ADDR 0x199 +#define MT6316_RG_LDO_VDIG12_SW_OP_EN_ADDR 0x19B +#define MT6316_RG_LDO_VDIG12_HW0_OP_EN_ADDR 0x19B +#define MT6316_RG_LDO_VDIG12_HW2_OP_EN_ADDR 0x19B +#define MT6316_RG_LDO_VDIG12_RC0_OP_EN_ADDR 0x19B +#define MT6316_RG_LDO_VDIG12_BUCK_OP_EN_ADDR 0x19B +#define MT6316_RG_LDO_VDIG12_HW0_OP_MODE_ADDR 0x19C +#define MT6316_RG_LDO_VDIG12_HW2_OP_MODE_ADDR 0x19C +#define MT6316_RG_LDO_VDIG12_RC0_OP_MODE_ADDR 0x19C +#define MT6316_RG_LDO_VDIG12_BUCK_OP_MODE_ADDR 0x19C +#define MT6316_RG_VDIG12_PWROFF_OP_EN_ADDR 0x19D +#define MT6316_RG_BUCK_VBUCK1_VOSEL_SLEEP_ADDR 0x148 +#define MT6316_RG_BUCK_VBUCK1_ONLV_EN_ADDR 0x148 +#define MT6316_RG_BUCK_VBUCK1_ONLV_EN_SHIFT 4 +#define MT6316_RG_BUCK_VBUCK1_RC0_OP_EN_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC1_OP_EN_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC2_OP_EN_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC3_OP_EN_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC4_OP_EN_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC5_OP_EN_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC6_OP_EN_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC7_OP_EN_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC8_OP_EN_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC9_OP_EN_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC10_OP_EN_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC11_OP_EN_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC12_OP_EN_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC13_OP_EN_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_HW0_OP_EN_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_HW1_OP_EN_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_HW2_OP_EN_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_HW3_OP_EN_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_SW_OP_EN_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC0_OP_CFG_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC1_OP_CFG_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC2_OP_CFG_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC3_OP_CFG_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC4_OP_CFG_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC5_OP_CFG_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC6_OP_CFG_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC7_OP_CFG_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC8_OP_CFG_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC9_OP_CFG_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC10_OP_CFG_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC11_OP_CFG_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC12_OP_CFG_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC13_OP_CFG_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_HW0_OP_CFG_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_HW1_OP_CFG_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_HW2_OP_CFG_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_HW3_OP_CFG_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC0_OP_MODE_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC1_OP_MODE_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC2_OP_MODE_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC3_OP_MODE_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC4_OP_MODE_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC5_OP_MODE_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC6_OP_MODE_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC7_OP_MODE_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC8_OP_MODE_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC9_OP_MODE_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC10_OP_MODE_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC11_OP_MODE_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC12_OP_MODE_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_RC13_OP_MODE_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_HW0_OP_MODE_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_HW1_OP_MODE_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_HW2_OP_MODE_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK1_HW3_OP_MODE_ADDR 0x149 +#define MT6316_RG_BUCK_VBUCK2_VOSEL_SLEEP_ADDR 0x150 +#define MT6316_RG_BUCK_VBUCK2_ONLV_EN_ADDR 0x150 +#define MT6316_RG_BUCK_VBUCK2_ONLV_EN_SHIFT 4 +#define MT6316_RG_BUCK_VBUCK2_RC0_OP_EN_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC1_OP_EN_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC2_OP_EN_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC3_OP_EN_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC4_OP_EN_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC5_OP_EN_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC6_OP_EN_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC7_OP_EN_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC8_OP_EN_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC9_OP_EN_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC10_OP_EN_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC11_OP_EN_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC12_OP_EN_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC13_OP_EN_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_HW0_OP_EN_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_HW1_OP_EN_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_HW2_OP_EN_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_HW3_OP_EN_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_SW_OP_EN_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC0_OP_CFG_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC1_OP_CFG_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC2_OP_CFG_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC3_OP_CFG_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC4_OP_CFG_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC5_OP_CFG_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC6_OP_CFG_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC7_OP_CFG_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC8_OP_CFG_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC9_OP_CFG_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC10_OP_CFG_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC11_OP_CFG_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC12_OP_CFG_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC13_OP_CFG_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_HW0_OP_CFG_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_HW1_OP_CFG_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_HW2_OP_CFG_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_HW3_OP_CFG_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC0_OP_MODE_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC1_OP_MODE_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC2_OP_MODE_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC3_OP_MODE_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC4_OP_MODE_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC5_OP_MODE_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC6_OP_MODE_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC7_OP_MODE_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC8_OP_MODE_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC9_OP_MODE_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC10_OP_MODE_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC11_OP_MODE_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC12_OP_MODE_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_RC13_OP_MODE_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_HW0_OP_MODE_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_HW1_OP_MODE_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_HW2_OP_MODE_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK2_HW3_OP_MODE_ADDR 0x151 +#define MT6316_RG_BUCK_VBUCK3_VOSEL_SLEEP_ADDR 0x158 +#define MT6316_RG_BUCK_VBUCK3_ONLV_EN_ADDR 0x158 +#define MT6316_RG_BUCK_VBUCK3_ONLV_EN_SHIFT 4 +#define MT6316_RG_BUCK_VBUCK3_RC0_OP_EN_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC1_OP_EN_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC2_OP_EN_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC3_OP_EN_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC4_OP_EN_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC5_OP_EN_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC6_OP_EN_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC7_OP_EN_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC8_OP_EN_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC9_OP_EN_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC10_OP_EN_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC11_OP_EN_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC12_OP_EN_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC13_OP_EN_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_HW0_OP_EN_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_HW1_OP_EN_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_HW2_OP_EN_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_HW3_OP_EN_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_SW_OP_EN_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC0_OP_CFG_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC1_OP_CFG_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC2_OP_CFG_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC3_OP_CFG_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC4_OP_CFG_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC5_OP_CFG_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC6_OP_CFG_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC7_OP_CFG_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC8_OP_CFG_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC9_OP_CFG_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC10_OP_CFG_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC11_OP_CFG_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC12_OP_CFG_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC13_OP_CFG_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_HW0_OP_CFG_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_HW1_OP_CFG_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_HW2_OP_CFG_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_HW3_OP_CFG_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC0_OP_MODE_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC1_OP_MODE_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC2_OP_MODE_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC3_OP_MODE_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC4_OP_MODE_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC5_OP_MODE_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC6_OP_MODE_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC7_OP_MODE_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC8_OP_MODE_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC9_OP_MODE_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC10_OP_MODE_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC11_OP_MODE_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC12_OP_MODE_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_RC13_OP_MODE_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_HW0_OP_MODE_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_HW1_OP_MODE_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_HW2_OP_MODE_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK3_HW3_OP_MODE_ADDR 0x159 +#define MT6316_RG_BUCK_VBUCK4_VOSEL_SLEEP_ADDR 0x160 +#define MT6316_RG_BUCK_VBUCK4_ONLV_EN_ADDR 0x160 +#define MT6316_RG_BUCK_VBUCK4_ONLV_EN_SHIFT 4 +#define MT6316_RG_BUCK_VBUCK4_RC0_OP_EN_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC1_OP_EN_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC2_OP_EN_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC3_OP_EN_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC4_OP_EN_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC5_OP_EN_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC6_OP_EN_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC7_OP_EN_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC8_OP_EN_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC9_OP_EN_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC10_OP_EN_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC11_OP_EN_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC12_OP_EN_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC13_OP_EN_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_HW0_OP_EN_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_HW1_OP_EN_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_HW2_OP_EN_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_HW3_OP_EN_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_SW_OP_EN_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC0_OP_CFG_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC1_OP_CFG_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC2_OP_CFG_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC3_OP_CFG_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC4_OP_CFG_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC5_OP_CFG_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC6_OP_CFG_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC7_OP_CFG_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC8_OP_CFG_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC9_OP_CFG_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC10_OP_CFG_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC11_OP_CFG_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC12_OP_CFG_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC13_OP_CFG_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_HW0_OP_CFG_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_HW1_OP_CFG_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_HW2_OP_CFG_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_HW3_OP_CFG_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC0_OP_MODE_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC1_OP_MODE_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC2_OP_MODE_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC3_OP_MODE_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC4_OP_MODE_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC5_OP_MODE_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC6_OP_MODE_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC7_OP_MODE_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC8_OP_MODE_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC9_OP_MODE_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC10_OP_MODE_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC11_OP_MODE_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC12_OP_MODE_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_RC13_OP_MODE_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_HW0_OP_MODE_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_HW1_OP_MODE_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_HW2_OP_MODE_ADDR 0x161 +#define MT6316_RG_BUCK_VBUCK4_HW3_OP_MODE_ADDR 0x161 + +#endif /* MT6316_LOWPOWER_REG_H */ diff --git a/plat/mediatek/include/drivers/pmic/mt6363_lowpower_reg.h b/plat/mediatek/include/drivers/pmic/mt6363_lowpower_reg.h new file mode 100644 index 000000000..9ec2ed3ac --- /dev/null +++ b/plat/mediatek/include/drivers/pmic/mt6363_lowpower_reg.h @@ -0,0 +1,2320 @@ +/* + * Copyright (c) 2025, Mediatek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT6363_LOWPOWER_REG_H +#define MT6363_LOWPOWER_REG_H + +#define MT6363_RG_BUCK_VS2_VOSEL_SLEEP_ADDR 0x1487 +#define MT6363_RG_BUCK_VS2_ONLV_EN_ADDR 0x1488 +#define MT6363_RG_BUCK_VS2_ONLV_EN_SHIFT 4 +#define MT6363_RG_BUCK_VS2_RC0_OP_EN_ADDR 0x148D +#define MT6363_RG_BUCK_VS2_RC1_OP_EN_ADDR 0x148D +#define MT6363_RG_BUCK_VS2_RC2_OP_EN_ADDR 0x148D +#define MT6363_RG_BUCK_VS2_RC3_OP_EN_ADDR 0x148D +#define MT6363_RG_BUCK_VS2_RC4_OP_EN_ADDR 0x148D +#define MT6363_RG_BUCK_VS2_RC5_OP_EN_ADDR 0x148D +#define MT6363_RG_BUCK_VS2_RC6_OP_EN_ADDR 0x148D +#define MT6363_RG_BUCK_VS2_RC7_OP_EN_ADDR 0x148D +#define MT6363_RG_BUCK_VS2_RC8_OP_EN_ADDR 0x148E +#define MT6363_RG_BUCK_VS2_RC9_OP_EN_ADDR 0x148E +#define MT6363_RG_BUCK_VS2_RC10_OP_EN_ADDR 0x148E +#define MT6363_RG_BUCK_VS2_RC11_OP_EN_ADDR 0x148E +#define MT6363_RG_BUCK_VS2_RC12_OP_EN_ADDR 0x148E +#define MT6363_RG_BUCK_VS2_RC13_OP_EN_ADDR 0x148E +#define MT6363_RG_BUCK_VS2_HW0_OP_EN_ADDR 0x148F +#define MT6363_RG_BUCK_VS2_HW1_OP_EN_ADDR 0x148F +#define MT6363_RG_BUCK_VS2_HW2_OP_EN_ADDR 0x148F +#define MT6363_RG_BUCK_VS2_HW3_OP_EN_ADDR 0x148F +#define MT6363_RG_BUCK_VS2_HW4_OP_EN_ADDR 0x148F +#define MT6363_RG_BUCK_VS2_SW_OP_EN_ADDR 0x148F +#define MT6363_RG_BUCK_VS2_RC0_OP_CFG_ADDR 0x1490 +#define MT6363_RG_BUCK_VS2_RC1_OP_CFG_ADDR 0x1490 +#define MT6363_RG_BUCK_VS2_RC2_OP_CFG_ADDR 0x1490 +#define MT6363_RG_BUCK_VS2_RC3_OP_CFG_ADDR 0x1490 +#define MT6363_RG_BUCK_VS2_RC4_OP_CFG_ADDR 0x1490 +#define MT6363_RG_BUCK_VS2_RC5_OP_CFG_ADDR 0x1490 +#define MT6363_RG_BUCK_VS2_RC6_OP_CFG_ADDR 0x1490 +#define MT6363_RG_BUCK_VS2_RC7_OP_CFG_ADDR 0x1490 +#define MT6363_RG_BUCK_VS2_RC8_OP_CFG_ADDR 0x1491 +#define MT6363_RG_BUCK_VS2_RC9_OP_CFG_ADDR 0x1491 +#define MT6363_RG_BUCK_VS2_RC10_OP_CFG_ADDR 0x1491 +#define MT6363_RG_BUCK_VS2_RC11_OP_CFG_ADDR 0x1491 +#define MT6363_RG_BUCK_VS2_RC12_OP_CFG_ADDR 0x1491 +#define MT6363_RG_BUCK_VS2_RC13_OP_CFG_ADDR 0x1491 +#define MT6363_RG_BUCK_VS2_HW0_OP_CFG_ADDR 0x1492 +#define MT6363_RG_BUCK_VS2_HW1_OP_CFG_ADDR 0x1492 +#define MT6363_RG_BUCK_VS2_HW2_OP_CFG_ADDR 0x1492 +#define MT6363_RG_BUCK_VS2_HW3_OP_CFG_ADDR 0x1492 +#define MT6363_RG_BUCK_VS2_HW4_OP_CFG_ADDR 0x1492 +#define MT6363_RG_BUCK_VS2_RC0_OP_MODE_ADDR 0x1493 +#define MT6363_RG_BUCK_VS2_RC1_OP_MODE_ADDR 0x1493 +#define MT6363_RG_BUCK_VS2_RC2_OP_MODE_ADDR 0x1493 +#define MT6363_RG_BUCK_VS2_RC3_OP_MODE_ADDR 0x1493 +#define MT6363_RG_BUCK_VS2_RC4_OP_MODE_ADDR 0x1493 +#define MT6363_RG_BUCK_VS2_RC5_OP_MODE_ADDR 0x1493 +#define MT6363_RG_BUCK_VS2_RC6_OP_MODE_ADDR 0x1493 +#define MT6363_RG_BUCK_VS2_RC7_OP_MODE_ADDR 0x1493 +#define MT6363_RG_BUCK_VS2_RC8_OP_MODE_ADDR 0x1494 +#define MT6363_RG_BUCK_VS2_RC9_OP_MODE_ADDR 0x1494 +#define MT6363_RG_BUCK_VS2_RC10_OP_MODE_ADDR 0x1494 +#define MT6363_RG_BUCK_VS2_RC11_OP_MODE_ADDR 0x1494 +#define MT6363_RG_BUCK_VS2_RC12_OP_MODE_ADDR 0x1494 +#define MT6363_RG_BUCK_VS2_RC13_OP_MODE_ADDR 0x1494 +#define MT6363_RG_BUCK_VS2_HW0_OP_MODE_ADDR 0x1495 +#define MT6363_RG_BUCK_VS2_HW1_OP_MODE_ADDR 0x1495 +#define MT6363_RG_BUCK_VS2_HW2_OP_MODE_ADDR 0x1495 +#define MT6363_RG_BUCK_VS2_HW3_OP_MODE_ADDR 0x1495 +#define MT6363_RG_BUCK_VS2_HW4_OP_MODE_ADDR 0x1495 +#define MT6363_RG_BUCK_VBUCK1_VOSEL_SLEEP_ADDR 0x1507 +#define MT6363_RG_BUCK_VBUCK1_ONLV_EN_ADDR 0x1508 +#define MT6363_RG_BUCK_VBUCK1_ONLV_EN_SHIFT 4 +#define MT6363_RG_BUCK_VBUCK1_RC0_OP_EN_ADDR 0x150D +#define MT6363_RG_BUCK_VBUCK1_RC1_OP_EN_ADDR 0x150D +#define MT6363_RG_BUCK_VBUCK1_RC2_OP_EN_ADDR 0x150D +#define MT6363_RG_BUCK_VBUCK1_RC3_OP_EN_ADDR 0x150D +#define MT6363_RG_BUCK_VBUCK1_RC4_OP_EN_ADDR 0x150D +#define MT6363_RG_BUCK_VBUCK1_RC5_OP_EN_ADDR 0x150D +#define MT6363_RG_BUCK_VBUCK1_RC6_OP_EN_ADDR 0x150D +#define MT6363_RG_BUCK_VBUCK1_RC7_OP_EN_ADDR 0x150D +#define MT6363_RG_BUCK_VBUCK1_RC8_OP_EN_ADDR 0x150E +#define MT6363_RG_BUCK_VBUCK1_RC9_OP_EN_ADDR 0x150E +#define MT6363_RG_BUCK_VBUCK1_RC10_OP_EN_ADDR 0x150E +#define MT6363_RG_BUCK_VBUCK1_RC11_OP_EN_ADDR 0x150E +#define MT6363_RG_BUCK_VBUCK1_RC12_OP_EN_ADDR 0x150E +#define MT6363_RG_BUCK_VBUCK1_RC13_OP_EN_ADDR 0x150E +#define MT6363_RG_BUCK_VBUCK1_HW0_OP_EN_ADDR 0x150F +#define MT6363_RG_BUCK_VBUCK1_HW1_OP_EN_ADDR 0x150F +#define MT6363_RG_BUCK_VBUCK1_HW2_OP_EN_ADDR 0x150F +#define MT6363_RG_BUCK_VBUCK1_HW3_OP_EN_ADDR 0x150F +#define MT6363_RG_BUCK_VBUCK1_SW_OP_EN_ADDR 0x150F +#define MT6363_RG_BUCK_VBUCK1_RC0_OP_CFG_ADDR 0x1510 +#define MT6363_RG_BUCK_VBUCK1_RC1_OP_CFG_ADDR 0x1510 +#define MT6363_RG_BUCK_VBUCK1_RC2_OP_CFG_ADDR 0x1510 +#define MT6363_RG_BUCK_VBUCK1_RC3_OP_CFG_ADDR 0x1510 +#define MT6363_RG_BUCK_VBUCK1_RC4_OP_CFG_ADDR 0x1510 +#define MT6363_RG_BUCK_VBUCK1_RC5_OP_CFG_ADDR 0x1510 +#define MT6363_RG_BUCK_VBUCK1_RC6_OP_CFG_ADDR 0x1510 +#define MT6363_RG_BUCK_VBUCK1_RC7_OP_CFG_ADDR 0x1510 +#define MT6363_RG_BUCK_VBUCK1_RC8_OP_CFG_ADDR 0x1511 +#define MT6363_RG_BUCK_VBUCK1_RC9_OP_CFG_ADDR 0x1511 +#define MT6363_RG_BUCK_VBUCK1_RC10_OP_CFG_ADDR 0x1511 +#define MT6363_RG_BUCK_VBUCK1_RC11_OP_CFG_ADDR 0x1511 +#define MT6363_RG_BUCK_VBUCK1_RC12_OP_CFG_ADDR 0x1511 +#define MT6363_RG_BUCK_VBUCK1_RC13_OP_CFG_ADDR 0x1511 +#define MT6363_RG_BUCK_VBUCK1_HW0_OP_CFG_ADDR 0x1512 +#define MT6363_RG_BUCK_VBUCK1_HW1_OP_CFG_ADDR 0x1512 +#define MT6363_RG_BUCK_VBUCK1_HW2_OP_CFG_ADDR 0x1512 +#define MT6363_RG_BUCK_VBUCK1_HW3_OP_CFG_ADDR 0x1512 +#define MT6363_RG_BUCK_VBUCK1_HW4_OP_CFG_ADDR 0x1512 +#define MT6363_RG_BUCK_VBUCK1_RC0_OP_MODE_ADDR 0x1513 +#define MT6363_RG_BUCK_VBUCK1_RC1_OP_MODE_ADDR 0x1513 +#define MT6363_RG_BUCK_VBUCK1_RC2_OP_MODE_ADDR 0x1513 +#define MT6363_RG_BUCK_VBUCK1_RC3_OP_MODE_ADDR 0x1513 +#define MT6363_RG_BUCK_VBUCK1_RC4_OP_MODE_ADDR 0x1513 +#define MT6363_RG_BUCK_VBUCK1_RC5_OP_MODE_ADDR 0x1513 +#define MT6363_RG_BUCK_VBUCK1_RC6_OP_MODE_ADDR 0x1513 +#define MT6363_RG_BUCK_VBUCK1_RC7_OP_MODE_ADDR 0x1513 +#define MT6363_RG_BUCK_VBUCK1_RC8_OP_MODE_ADDR 0x1514 +#define MT6363_RG_BUCK_VBUCK1_RC9_OP_MODE_ADDR 0x1514 +#define MT6363_RG_BUCK_VBUCK1_RC10_OP_MODE_ADDR 0x1514 +#define MT6363_RG_BUCK_VBUCK1_RC11_OP_MODE_ADDR 0x1514 +#define MT6363_RG_BUCK_VBUCK1_RC12_OP_MODE_ADDR 0x1514 +#define MT6363_RG_BUCK_VBUCK1_RC13_OP_MODE_ADDR 0x1514 +#define MT6363_RG_BUCK_VBUCK1_HW0_OP_MODE_ADDR 0x1515 +#define MT6363_RG_BUCK_VBUCK1_HW1_OP_MODE_ADDR 0x1515 +#define MT6363_RG_BUCK_VBUCK1_HW2_OP_MODE_ADDR 0x1515 +#define MT6363_RG_BUCK_VBUCK1_HW3_OP_MODE_ADDR 0x1515 +#define MT6363_RG_BUCK_VBUCK2_VOSEL_SLEEP_ADDR 0x1587 +#define MT6363_RG_BUCK_VBUCK2_ONLV_EN_ADDR 0x1588 +#define MT6363_RG_BUCK_VBUCK2_ONLV_EN_SHIFT 4 +#define MT6363_RG_BUCK_VBUCK2_RC0_OP_EN_ADDR 0x158D +#define MT6363_RG_BUCK_VBUCK2_RC1_OP_EN_ADDR 0x158D +#define MT6363_RG_BUCK_VBUCK2_RC2_OP_EN_ADDR 0x158D +#define MT6363_RG_BUCK_VBUCK2_RC3_OP_EN_ADDR 0x158D +#define MT6363_RG_BUCK_VBUCK2_RC4_OP_EN_ADDR 0x158D +#define MT6363_RG_BUCK_VBUCK2_RC5_OP_EN_ADDR 0x158D +#define MT6363_RG_BUCK_VBUCK2_RC6_OP_EN_ADDR 0x158D +#define MT6363_RG_BUCK_VBUCK2_RC7_OP_EN_ADDR 0x158D +#define MT6363_RG_BUCK_VBUCK2_RC8_OP_EN_ADDR 0x158E +#define MT6363_RG_BUCK_VBUCK2_RC9_OP_EN_ADDR 0x158E +#define MT6363_RG_BUCK_VBUCK2_RC10_OP_EN_ADDR 0x158E +#define MT6363_RG_BUCK_VBUCK2_RC11_OP_EN_ADDR 0x158E +#define MT6363_RG_BUCK_VBUCK2_RC12_OP_EN_ADDR 0x158E +#define MT6363_RG_BUCK_VBUCK2_RC13_OP_EN_ADDR 0x158E +#define MT6363_RG_BUCK_VBUCK2_HW0_OP_EN_ADDR 0x158F +#define MT6363_RG_BUCK_VBUCK2_HW1_OP_EN_ADDR 0x158F +#define MT6363_RG_BUCK_VBUCK2_HW2_OP_EN_ADDR 0x158F +#define MT6363_RG_BUCK_VBUCK2_HW3_OP_EN_ADDR 0x158F +#define MT6363_RG_BUCK_VBUCK2_SW_OP_EN_ADDR 0x158F +#define MT6363_RG_BUCK_VBUCK2_RC0_OP_CFG_ADDR 0x1590 +#define MT6363_RG_BUCK_VBUCK2_RC1_OP_CFG_ADDR 0x1590 +#define MT6363_RG_BUCK_VBUCK2_RC2_OP_CFG_ADDR 0x1590 +#define MT6363_RG_BUCK_VBUCK2_RC3_OP_CFG_ADDR 0x1590 +#define MT6363_RG_BUCK_VBUCK2_RC4_OP_CFG_ADDR 0x1590 +#define MT6363_RG_BUCK_VBUCK2_RC5_OP_CFG_ADDR 0x1590 +#define MT6363_RG_BUCK_VBUCK2_RC6_OP_CFG_ADDR 0x1590 +#define MT6363_RG_BUCK_VBUCK2_RC7_OP_CFG_ADDR 0x1590 +#define MT6363_RG_BUCK_VBUCK2_RC8_OP_CFG_ADDR 0x1591 +#define MT6363_RG_BUCK_VBUCK2_RC9_OP_CFG_ADDR 0x1591 +#define MT6363_RG_BUCK_VBUCK2_RC10_OP_CFG_ADDR 0x1591 +#define MT6363_RG_BUCK_VBUCK2_RC11_OP_CFG_ADDR 0x1591 +#define MT6363_RG_BUCK_VBUCK2_RC12_OP_CFG_ADDR 0x1591 +#define MT6363_RG_BUCK_VBUCK2_RC13_OP_CFG_ADDR 0x1591 +#define MT6363_RG_BUCK_VBUCK2_HW0_OP_CFG_ADDR 0x1592 +#define MT6363_RG_BUCK_VBUCK2_HW1_OP_CFG_ADDR 0x1592 +#define MT6363_RG_BUCK_VBUCK2_HW2_OP_CFG_ADDR 0x1592 +#define MT6363_RG_BUCK_VBUCK2_HW3_OP_CFG_ADDR 0x1592 +#define MT6363_RG_BUCK_VBUCK2_RC0_OP_MODE_ADDR 0x1593 +#define MT6363_RG_BUCK_VBUCK2_RC1_OP_MODE_ADDR 0x1593 +#define MT6363_RG_BUCK_VBUCK2_RC2_OP_MODE_ADDR 0x1593 +#define MT6363_RG_BUCK_VBUCK2_RC3_OP_MODE_ADDR 0x1593 +#define MT6363_RG_BUCK_VBUCK2_RC4_OP_MODE_ADDR 0x1593 +#define MT6363_RG_BUCK_VBUCK2_RC5_OP_MODE_ADDR 0x1593 +#define MT6363_RG_BUCK_VBUCK2_RC6_OP_MODE_ADDR 0x1593 +#define MT6363_RG_BUCK_VBUCK2_RC7_OP_MODE_ADDR 0x1593 +#define MT6363_RG_BUCK_VBUCK2_RC8_OP_MODE_ADDR 0x1594 +#define MT6363_RG_BUCK_VBUCK2_RC9_OP_MODE_ADDR 0x1594 +#define MT6363_RG_BUCK_VBUCK2_RC10_OP_MODE_ADDR 0x1594 +#define MT6363_RG_BUCK_VBUCK2_RC11_OP_MODE_ADDR 0x1594 +#define MT6363_RG_BUCK_VBUCK2_RC12_OP_MODE_ADDR 0x1594 +#define MT6363_RG_BUCK_VBUCK2_RC13_OP_MODE_ADDR 0x1594 +#define MT6363_RG_BUCK_VBUCK2_HW0_OP_MODE_ADDR 0x1595 +#define MT6363_RG_BUCK_VBUCK2_HW1_OP_MODE_ADDR 0x1595 +#define MT6363_RG_BUCK_VBUCK2_HW2_OP_MODE_ADDR 0x1595 +#define MT6363_RG_BUCK_VBUCK2_HW3_OP_MODE_ADDR 0x1595 +#define MT6363_RG_BUCK_VBUCK3_VOSEL_SLEEP_ADDR 0x1607 +#define MT6363_RG_BUCK_VBUCK3_ONLV_EN_ADDR 0x1608 +#define MT6363_RG_BUCK_VBUCK3_ONLV_EN_SHIFT 4 +#define MT6363_RG_BUCK_VBUCK3_RC0_OP_EN_ADDR 0x160D +#define MT6363_RG_BUCK_VBUCK3_RC1_OP_EN_ADDR 0x160D +#define MT6363_RG_BUCK_VBUCK3_RC2_OP_EN_ADDR 0x160D +#define MT6363_RG_BUCK_VBUCK3_RC3_OP_EN_ADDR 0x160D +#define MT6363_RG_BUCK_VBUCK3_RC4_OP_EN_ADDR 0x160D +#define MT6363_RG_BUCK_VBUCK3_RC5_OP_EN_ADDR 0x160D +#define MT6363_RG_BUCK_VBUCK3_RC6_OP_EN_ADDR 0x160D +#define MT6363_RG_BUCK_VBUCK3_RC7_OP_EN_ADDR 0x160D +#define MT6363_RG_BUCK_VBUCK3_RC8_OP_EN_ADDR 0x160E +#define MT6363_RG_BUCK_VBUCK3_RC9_OP_EN_ADDR 0x160E +#define MT6363_RG_BUCK_VBUCK3_RC10_OP_EN_ADDR 0x160E +#define MT6363_RG_BUCK_VBUCK3_RC11_OP_EN_ADDR 0x160E +#define MT6363_RG_BUCK_VBUCK3_RC12_OP_EN_ADDR 0x160E +#define MT6363_RG_BUCK_VBUCK3_RC13_OP_EN_ADDR 0x160E +#define MT6363_RG_BUCK_VBUCK3_HW0_OP_EN_ADDR 0x160F +#define MT6363_RG_BUCK_VBUCK3_HW1_OP_EN_ADDR 0x160F +#define MT6363_RG_BUCK_VBUCK3_HW2_OP_EN_ADDR 0x160F +#define MT6363_RG_BUCK_VBUCK3_HW3_OP_EN_ADDR 0x160F +#define MT6363_RG_BUCK_VBUCK3_SW_OP_EN_ADDR 0x160F +#define MT6363_RG_BUCK_VBUCK3_RC0_OP_CFG_ADDR 0x1610 +#define MT6363_RG_BUCK_VBUCK3_RC1_OP_CFG_ADDR 0x1610 +#define MT6363_RG_BUCK_VBUCK3_RC2_OP_CFG_ADDR 0x1610 +#define MT6363_RG_BUCK_VBUCK3_RC3_OP_CFG_ADDR 0x1610 +#define MT6363_RG_BUCK_VBUCK3_RC4_OP_CFG_ADDR 0x1610 +#define MT6363_RG_BUCK_VBUCK3_RC5_OP_CFG_ADDR 0x1610 +#define MT6363_RG_BUCK_VBUCK3_RC6_OP_CFG_ADDR 0x1610 +#define MT6363_RG_BUCK_VBUCK3_RC7_OP_CFG_ADDR 0x1610 +#define MT6363_RG_BUCK_VBUCK3_RC8_OP_CFG_ADDR 0x1611 +#define MT6363_RG_BUCK_VBUCK3_RC9_OP_CFG_ADDR 0x1611 +#define MT6363_RG_BUCK_VBUCK3_RC10_OP_CFG_ADDR 0x1611 +#define MT6363_RG_BUCK_VBUCK3_RC11_OP_CFG_ADDR 0x1611 +#define MT6363_RG_BUCK_VBUCK3_RC12_OP_CFG_ADDR 0x1611 +#define MT6363_RG_BUCK_VBUCK3_RC13_OP_CFG_ADDR 0x1611 +#define MT6363_RG_BUCK_VBUCK3_HW0_OP_CFG_ADDR 0x1612 +#define MT6363_RG_BUCK_VBUCK3_HW1_OP_CFG_ADDR 0x1612 +#define MT6363_RG_BUCK_VBUCK3_HW2_OP_CFG_ADDR 0x1612 +#define MT6363_RG_BUCK_VBUCK3_HW3_OP_CFG_ADDR 0x1612 +#define MT6363_RG_BUCK_VBUCK3_RC0_OP_MODE_ADDR 0x1613 +#define MT6363_RG_BUCK_VBUCK3_RC1_OP_MODE_ADDR 0x1613 +#define MT6363_RG_BUCK_VBUCK3_RC2_OP_MODE_ADDR 0x1613 +#define MT6363_RG_BUCK_VBUCK3_RC3_OP_MODE_ADDR 0x1613 +#define MT6363_RG_BUCK_VBUCK3_RC4_OP_MODE_ADDR 0x1613 +#define MT6363_RG_BUCK_VBUCK3_RC5_OP_MODE_ADDR 0x1613 +#define MT6363_RG_BUCK_VBUCK3_RC6_OP_MODE_ADDR 0x1613 +#define MT6363_RG_BUCK_VBUCK3_RC7_OP_MODE_ADDR 0x1613 +#define MT6363_RG_BUCK_VBUCK3_RC8_OP_MODE_ADDR 0x1614 +#define MT6363_RG_BUCK_VBUCK3_RC9_OP_MODE_ADDR 0x1614 +#define MT6363_RG_BUCK_VBUCK3_RC10_OP_MODE_ADDR 0x1614 +#define MT6363_RG_BUCK_VBUCK3_RC11_OP_MODE_ADDR 0x1614 +#define MT6363_RG_BUCK_VBUCK3_RC12_OP_MODE_ADDR 0x1614 +#define MT6363_RG_BUCK_VBUCK3_RC13_OP_MODE_ADDR 0x1614 +#define MT6363_RG_BUCK_VBUCK3_HW0_OP_MODE_ADDR 0x1615 +#define MT6363_RG_BUCK_VBUCK3_HW1_OP_MODE_ADDR 0x1615 +#define MT6363_RG_BUCK_VBUCK3_HW2_OP_MODE_ADDR 0x1615 +#define MT6363_RG_BUCK_VBUCK3_HW3_OP_MODE_ADDR 0x1615 +#define MT6363_RG_BUCK_VBUCK4_VOSEL_SLEEP_ADDR 0x1687 +#define MT6363_RG_BUCK_VBUCK4_ONLV_EN_ADDR 0x1688 +#define MT6363_RG_BUCK_VBUCK4_ONLV_EN_SHIFT 4 +#define MT6363_RG_BUCK_VBUCK4_RC0_OP_EN_ADDR 0x168D +#define MT6363_RG_BUCK_VBUCK4_RC1_OP_EN_ADDR 0x168D +#define MT6363_RG_BUCK_VBUCK4_RC2_OP_EN_ADDR 0x168D +#define MT6363_RG_BUCK_VBUCK4_RC3_OP_EN_ADDR 0x168D +#define MT6363_RG_BUCK_VBUCK4_RC4_OP_EN_ADDR 0x168D +#define MT6363_RG_BUCK_VBUCK4_RC5_OP_EN_ADDR 0x168D +#define MT6363_RG_BUCK_VBUCK4_RC6_OP_EN_ADDR 0x168D +#define MT6363_RG_BUCK_VBUCK4_RC7_OP_EN_ADDR 0x168D +#define MT6363_RG_BUCK_VBUCK4_RC8_OP_EN_ADDR 0x168E +#define MT6363_RG_BUCK_VBUCK4_RC9_OP_EN_ADDR 0x168E +#define MT6363_RG_BUCK_VBUCK4_RC10_OP_EN_ADDR 0x168E +#define MT6363_RG_BUCK_VBUCK4_RC11_OP_EN_ADDR 0x168E +#define MT6363_RG_BUCK_VBUCK4_RC12_OP_EN_ADDR 0x168E +#define MT6363_RG_BUCK_VBUCK4_RC13_OP_EN_ADDR 0x168E +#define MT6363_RG_BUCK_VBUCK4_HW0_OP_EN_ADDR 0x168F +#define MT6363_RG_BUCK_VBUCK4_HW1_OP_EN_ADDR 0x168F +#define MT6363_RG_BUCK_VBUCK4_HW2_OP_EN_ADDR 0x168F +#define MT6363_RG_BUCK_VBUCK4_HW3_OP_EN_ADDR 0x168F +#define MT6363_RG_BUCK_VBUCK4_SW_OP_EN_ADDR 0x168F +#define MT6363_RG_BUCK_VBUCK4_RC0_OP_CFG_ADDR 0x1690 +#define MT6363_RG_BUCK_VBUCK4_RC1_OP_CFG_ADDR 0x1690 +#define MT6363_RG_BUCK_VBUCK4_RC2_OP_CFG_ADDR 0x1690 +#define MT6363_RG_BUCK_VBUCK4_RC3_OP_CFG_ADDR 0x1690 +#define MT6363_RG_BUCK_VBUCK4_RC4_OP_CFG_ADDR 0x1690 +#define MT6363_RG_BUCK_VBUCK4_RC5_OP_CFG_ADDR 0x1690 +#define MT6363_RG_BUCK_VBUCK4_RC6_OP_CFG_ADDR 0x1690 +#define MT6363_RG_BUCK_VBUCK4_RC7_OP_CFG_ADDR 0x1690 +#define MT6363_RG_BUCK_VBUCK4_RC8_OP_CFG_ADDR 0x1691 +#define MT6363_RG_BUCK_VBUCK4_RC9_OP_CFG_ADDR 0x1691 +#define MT6363_RG_BUCK_VBUCK4_RC10_OP_CFG_ADDR 0x1691 +#define MT6363_RG_BUCK_VBUCK4_RC11_OP_CFG_ADDR 0x1691 +#define MT6363_RG_BUCK_VBUCK4_RC12_OP_CFG_ADDR 0x1691 +#define MT6363_RG_BUCK_VBUCK4_RC13_OP_CFG_ADDR 0x1691 +#define MT6363_RG_BUCK_VBUCK4_HW0_OP_CFG_ADDR 0x1692 +#define MT6363_RG_BUCK_VBUCK4_HW1_OP_CFG_ADDR 0x1692 +#define MT6363_RG_BUCK_VBUCK4_HW2_OP_CFG_ADDR 0x1692 +#define MT6363_RG_BUCK_VBUCK4_HW3_OP_CFG_ADDR 0x1692 +#define MT6363_RG_BUCK_VBUCK4_RC0_OP_MODE_ADDR 0x1693 +#define MT6363_RG_BUCK_VBUCK4_RC1_OP_MODE_ADDR 0x1693 +#define MT6363_RG_BUCK_VBUCK4_RC2_OP_MODE_ADDR 0x1693 +#define MT6363_RG_BUCK_VBUCK4_RC3_OP_MODE_ADDR 0x1693 +#define MT6363_RG_BUCK_VBUCK4_RC4_OP_MODE_ADDR 0x1693 +#define MT6363_RG_BUCK_VBUCK4_RC5_OP_MODE_ADDR 0x1693 +#define MT6363_RG_BUCK_VBUCK4_RC6_OP_MODE_ADDR 0x1693 +#define MT6363_RG_BUCK_VBUCK4_RC7_OP_MODE_ADDR 0x1693 +#define MT6363_RG_BUCK_VBUCK4_RC8_OP_MODE_ADDR 0x1694 +#define MT6363_RG_BUCK_VBUCK4_RC9_OP_MODE_ADDR 0x1694 +#define MT6363_RG_BUCK_VBUCK4_RC10_OP_MODE_ADDR 0x1694 +#define MT6363_RG_BUCK_VBUCK4_RC11_OP_MODE_ADDR 0x1694 +#define MT6363_RG_BUCK_VBUCK4_RC12_OP_MODE_ADDR 0x1694 +#define MT6363_RG_BUCK_VBUCK4_RC13_OP_MODE_ADDR 0x1694 +#define MT6363_RG_BUCK_VBUCK4_HW0_OP_MODE_ADDR 0x1695 +#define MT6363_RG_BUCK_VBUCK4_HW1_OP_MODE_ADDR 0x1695 +#define MT6363_RG_BUCK_VBUCK4_HW2_OP_MODE_ADDR 0x1695 +#define MT6363_RG_BUCK_VBUCK4_HW3_OP_MODE_ADDR 0x1695 +#define MT6363_RG_BUCK_VBUCK5_VOSEL_SLEEP_ADDR 0x1707 +#define MT6363_RG_BUCK_VBUCK5_ONLV_EN_ADDR 0x1708 +#define MT6363_RG_BUCK_VBUCK5_ONLV_EN_SHIFT 4 +#define MT6363_RG_BUCK_VBUCK5_RC0_OP_EN_ADDR 0x170D +#define MT6363_RG_BUCK_VBUCK5_RC1_OP_EN_ADDR 0x170D +#define MT6363_RG_BUCK_VBUCK5_RC2_OP_EN_ADDR 0x170D +#define MT6363_RG_BUCK_VBUCK5_RC3_OP_EN_ADDR 0x170D +#define MT6363_RG_BUCK_VBUCK5_RC4_OP_EN_ADDR 0x170D +#define MT6363_RG_BUCK_VBUCK5_RC5_OP_EN_ADDR 0x170D +#define MT6363_RG_BUCK_VBUCK5_RC6_OP_EN_ADDR 0x170D +#define MT6363_RG_BUCK_VBUCK5_RC7_OP_EN_ADDR 0x170D +#define MT6363_RG_BUCK_VBUCK5_RC8_OP_EN_ADDR 0x170E +#define MT6363_RG_BUCK_VBUCK5_RC9_OP_EN_ADDR 0x170E +#define MT6363_RG_BUCK_VBUCK5_RC10_OP_EN_ADDR 0x170E +#define MT6363_RG_BUCK_VBUCK5_RC11_OP_EN_ADDR 0x170E +#define MT6363_RG_BUCK_VBUCK5_RC12_OP_EN_ADDR 0x170E +#define MT6363_RG_BUCK_VBUCK5_RC13_OP_EN_ADDR 0x170E +#define MT6363_RG_BUCK_VBUCK5_HW0_OP_EN_ADDR 0x170F +#define MT6363_RG_BUCK_VBUCK5_HW1_OP_EN_ADDR 0x170F +#define MT6363_RG_BUCK_VBUCK5_HW2_OP_EN_ADDR 0x170F +#define MT6363_RG_BUCK_VBUCK5_HW3_OP_EN_ADDR 0x170F +#define MT6363_RG_BUCK_VBUCK5_SW_OP_EN_ADDR 0x170F +#define MT6363_RG_BUCK_VBUCK5_RC0_OP_CFG_ADDR 0x1710 +#define MT6363_RG_BUCK_VBUCK5_RC1_OP_CFG_ADDR 0x1710 +#define MT6363_RG_BUCK_VBUCK5_RC2_OP_CFG_ADDR 0x1710 +#define MT6363_RG_BUCK_VBUCK5_RC3_OP_CFG_ADDR 0x1710 +#define MT6363_RG_BUCK_VBUCK5_RC4_OP_CFG_ADDR 0x1710 +#define MT6363_RG_BUCK_VBUCK5_RC5_OP_CFG_ADDR 0x1710 +#define MT6363_RG_BUCK_VBUCK5_RC6_OP_CFG_ADDR 0x1710 +#define MT6363_RG_BUCK_VBUCK5_RC7_OP_CFG_ADDR 0x1710 +#define MT6363_RG_BUCK_VBUCK5_RC8_OP_CFG_ADDR 0x1711 +#define MT6363_RG_BUCK_VBUCK5_RC9_OP_CFG_ADDR 0x1711 +#define MT6363_RG_BUCK_VBUCK5_RC10_OP_CFG_ADDR 0x1711 +#define MT6363_RG_BUCK_VBUCK5_RC11_OP_CFG_ADDR 0x1711 +#define MT6363_RG_BUCK_VBUCK5_RC12_OP_CFG_ADDR 0x1711 +#define MT6363_RG_BUCK_VBUCK5_RC13_OP_CFG_ADDR 0x1711 +#define MT6363_RG_BUCK_VBUCK5_HW0_OP_CFG_ADDR 0x1712 +#define MT6363_RG_BUCK_VBUCK5_HW1_OP_CFG_ADDR 0x1712 +#define MT6363_RG_BUCK_VBUCK5_HW2_OP_CFG_ADDR 0x1712 +#define MT6363_RG_BUCK_VBUCK5_HW3_OP_CFG_ADDR 0x1712 +#define MT6363_RG_BUCK_VBUCK5_RC0_OP_MODE_ADDR 0x1713 +#define MT6363_RG_BUCK_VBUCK5_RC1_OP_MODE_ADDR 0x1713 +#define MT6363_RG_BUCK_VBUCK5_RC2_OP_MODE_ADDR 0x1713 +#define MT6363_RG_BUCK_VBUCK5_RC3_OP_MODE_ADDR 0x1713 +#define MT6363_RG_BUCK_VBUCK5_RC4_OP_MODE_ADDR 0x1713 +#define MT6363_RG_BUCK_VBUCK5_RC5_OP_MODE_ADDR 0x1713 +#define MT6363_RG_BUCK_VBUCK5_RC6_OP_MODE_ADDR 0x1713 +#define MT6363_RG_BUCK_VBUCK5_RC7_OP_MODE_ADDR 0x1713 +#define MT6363_RG_BUCK_VBUCK5_RC8_OP_MODE_ADDR 0x1714 +#define MT6363_RG_BUCK_VBUCK5_RC9_OP_MODE_ADDR 0x1714 +#define MT6363_RG_BUCK_VBUCK5_RC10_OP_MODE_ADDR 0x1714 +#define MT6363_RG_BUCK_VBUCK5_RC11_OP_MODE_ADDR 0x1714 +#define MT6363_RG_BUCK_VBUCK5_RC12_OP_MODE_ADDR 0x1714 +#define MT6363_RG_BUCK_VBUCK5_RC13_OP_MODE_ADDR 0x1714 +#define MT6363_RG_BUCK_VBUCK5_HW0_OP_MODE_ADDR 0x1715 +#define MT6363_RG_BUCK_VBUCK5_HW1_OP_MODE_ADDR 0x1715 +#define MT6363_RG_BUCK_VBUCK5_HW2_OP_MODE_ADDR 0x1715 +#define MT6363_RG_BUCK_VBUCK5_HW3_OP_MODE_ADDR 0x1715 +#define MT6363_RG_BUCK_VBUCK6_VOSEL_SLEEP_ADDR 0x1787 +#define MT6363_RG_BUCK_VBUCK6_ONLV_EN_ADDR 0x1788 +#define MT6363_RG_BUCK_VBUCK6_ONLV_EN_SHIFT 4 +#define MT6363_RG_BUCK_VBUCK6_RC0_OP_EN_ADDR 0x178D +#define MT6363_RG_BUCK_VBUCK6_RC1_OP_EN_ADDR 0x178D +#define MT6363_RG_BUCK_VBUCK6_RC2_OP_EN_ADDR 0x178D +#define MT6363_RG_BUCK_VBUCK6_RC3_OP_EN_ADDR 0x178D +#define MT6363_RG_BUCK_VBUCK6_RC4_OP_EN_ADDR 0x178D +#define MT6363_RG_BUCK_VBUCK6_RC5_OP_EN_ADDR 0x178D +#define MT6363_RG_BUCK_VBUCK6_RC6_OP_EN_ADDR 0x178D +#define MT6363_RG_BUCK_VBUCK6_RC7_OP_EN_ADDR 0x178D +#define MT6363_RG_BUCK_VBUCK6_RC8_OP_EN_ADDR 0x178E +#define MT6363_RG_BUCK_VBUCK6_RC9_OP_EN_ADDR 0x178E +#define MT6363_RG_BUCK_VBUCK6_RC10_OP_EN_ADDR 0x178E +#define MT6363_RG_BUCK_VBUCK6_RC11_OP_EN_ADDR 0x178E +#define MT6363_RG_BUCK_VBUCK6_RC12_OP_EN_ADDR 0x178E +#define MT6363_RG_BUCK_VBUCK6_RC13_OP_EN_ADDR 0x178E +#define MT6363_RG_BUCK_VBUCK6_HW0_OP_EN_ADDR 0x178F +#define MT6363_RG_BUCK_VBUCK6_HW1_OP_EN_ADDR 0x178F +#define MT6363_RG_BUCK_VBUCK6_HW2_OP_EN_ADDR 0x178F +#define MT6363_RG_BUCK_VBUCK6_HW3_OP_EN_ADDR 0x178F +#define MT6363_RG_BUCK_VBUCK6_SW_OP_EN_ADDR 0x178F +#define MT6363_RG_BUCK_VBUCK6_RC0_OP_CFG_ADDR 0x1790 +#define MT6363_RG_BUCK_VBUCK6_RC1_OP_CFG_ADDR 0x1790 +#define MT6363_RG_BUCK_VBUCK6_RC2_OP_CFG_ADDR 0x1790 +#define MT6363_RG_BUCK_VBUCK6_RC3_OP_CFG_ADDR 0x1790 +#define MT6363_RG_BUCK_VBUCK6_RC4_OP_CFG_ADDR 0x1790 +#define MT6363_RG_BUCK_VBUCK6_RC5_OP_CFG_ADDR 0x1790 +#define MT6363_RG_BUCK_VBUCK6_RC6_OP_CFG_ADDR 0x1790 +#define MT6363_RG_BUCK_VBUCK6_RC7_OP_CFG_ADDR 0x1790 +#define MT6363_RG_BUCK_VBUCK6_RC8_OP_CFG_ADDR 0x1791 +#define MT6363_RG_BUCK_VBUCK6_RC9_OP_CFG_ADDR 0x1791 +#define MT6363_RG_BUCK_VBUCK6_RC10_OP_CFG_ADDR 0x1791 +#define MT6363_RG_BUCK_VBUCK6_RC11_OP_CFG_ADDR 0x1791 +#define MT6363_RG_BUCK_VBUCK6_RC12_OP_CFG_ADDR 0x1791 +#define MT6363_RG_BUCK_VBUCK6_RC13_OP_CFG_ADDR 0x1791 +#define MT6363_RG_BUCK_VBUCK6_HW0_OP_CFG_ADDR 0x1792 +#define MT6363_RG_BUCK_VBUCK6_HW1_OP_CFG_ADDR 0x1792 +#define MT6363_RG_BUCK_VBUCK6_HW2_OP_CFG_ADDR 0x1792 +#define MT6363_RG_BUCK_VBUCK6_HW3_OP_CFG_ADDR 0x1792 +#define MT6363_RG_BUCK_VBUCK6_RC0_OP_MODE_ADDR 0x1793 +#define MT6363_RG_BUCK_VBUCK6_RC1_OP_MODE_ADDR 0x1793 +#define MT6363_RG_BUCK_VBUCK6_RC2_OP_MODE_ADDR 0x1793 +#define MT6363_RG_BUCK_VBUCK6_RC3_OP_MODE_ADDR 0x1793 +#define MT6363_RG_BUCK_VBUCK6_RC4_OP_MODE_ADDR 0x1793 +#define MT6363_RG_BUCK_VBUCK6_RC5_OP_MODE_ADDR 0x1793 +#define MT6363_RG_BUCK_VBUCK6_RC6_OP_MODE_ADDR 0x1793 +#define MT6363_RG_BUCK_VBUCK6_RC7_OP_MODE_ADDR 0x1793 +#define MT6363_RG_BUCK_VBUCK6_RC8_OP_MODE_ADDR 0x1794 +#define MT6363_RG_BUCK_VBUCK6_RC9_OP_MODE_ADDR 0x1794 +#define MT6363_RG_BUCK_VBUCK6_RC10_OP_MODE_ADDR 0x1794 +#define MT6363_RG_BUCK_VBUCK6_RC11_OP_MODE_ADDR 0x1794 +#define MT6363_RG_BUCK_VBUCK6_RC12_OP_MODE_ADDR 0x1794 +#define MT6363_RG_BUCK_VBUCK6_RC13_OP_MODE_ADDR 0x1794 +#define MT6363_RG_BUCK_VBUCK6_HW0_OP_MODE_ADDR 0x1795 +#define MT6363_RG_BUCK_VBUCK6_HW1_OP_MODE_ADDR 0x1795 +#define MT6363_RG_BUCK_VBUCK6_HW2_OP_MODE_ADDR 0x1795 +#define MT6363_RG_BUCK_VBUCK6_HW3_OP_MODE_ADDR 0x1795 +#define MT6363_RG_BUCK_VBUCK7_VOSEL_SLEEP_ADDR 0x1807 +#define MT6363_RG_BUCK_VBUCK7_ONLV_EN_ADDR 0x1808 +#define MT6363_RG_BUCK_VBUCK7_ONLV_EN_SHIFT 4 +#define MT6363_RG_BUCK_VBUCK7_RC0_OP_EN_ADDR 0x180D +#define MT6363_RG_BUCK_VBUCK7_RC1_OP_EN_ADDR 0x180D +#define MT6363_RG_BUCK_VBUCK7_RC2_OP_EN_ADDR 0x180D +#define MT6363_RG_BUCK_VBUCK7_RC3_OP_EN_ADDR 0x180D +#define MT6363_RG_BUCK_VBUCK7_RC4_OP_EN_ADDR 0x180D +#define MT6363_RG_BUCK_VBUCK7_RC5_OP_EN_ADDR 0x180D +#define MT6363_RG_BUCK_VBUCK7_RC6_OP_EN_ADDR 0x180D +#define MT6363_RG_BUCK_VBUCK7_RC7_OP_EN_ADDR 0x180D +#define MT6363_RG_BUCK_VBUCK7_RC8_OP_EN_ADDR 0x180E +#define MT6363_RG_BUCK_VBUCK7_RC9_OP_EN_ADDR 0x180E +#define MT6363_RG_BUCK_VBUCK7_RC10_OP_EN_ADDR 0x180E +#define MT6363_RG_BUCK_VBUCK7_RC11_OP_EN_ADDR 0x180E +#define MT6363_RG_BUCK_VBUCK7_RC12_OP_EN_ADDR 0x180E +#define MT6363_RG_BUCK_VBUCK7_RC13_OP_EN_ADDR 0x180E +#define MT6363_RG_BUCK_VBUCK7_HW0_OP_EN_ADDR 0x180F +#define MT6363_RG_BUCK_VBUCK7_HW1_OP_EN_ADDR 0x180F +#define MT6363_RG_BUCK_VBUCK7_HW2_OP_EN_ADDR 0x180F +#define MT6363_RG_BUCK_VBUCK7_HW3_OP_EN_ADDR 0x180F +#define MT6363_RG_BUCK_VBUCK7_SW_OP_EN_ADDR 0x180F +#define MT6363_RG_BUCK_VBUCK7_RC0_OP_CFG_ADDR 0x1810 +#define MT6363_RG_BUCK_VBUCK7_RC1_OP_CFG_ADDR 0x1810 +#define MT6363_RG_BUCK_VBUCK7_RC2_OP_CFG_ADDR 0x1810 +#define MT6363_RG_BUCK_VBUCK7_RC3_OP_CFG_ADDR 0x1810 +#define MT6363_RG_BUCK_VBUCK7_RC4_OP_CFG_ADDR 0x1810 +#define MT6363_RG_BUCK_VBUCK7_RC5_OP_CFG_ADDR 0x1810 +#define MT6363_RG_BUCK_VBUCK7_RC6_OP_CFG_ADDR 0x1810 +#define MT6363_RG_BUCK_VBUCK7_RC7_OP_CFG_ADDR 0x1810 +#define MT6363_RG_BUCK_VBUCK7_RC8_OP_CFG_ADDR 0x1811 +#define MT6363_RG_BUCK_VBUCK7_RC9_OP_CFG_ADDR 0x1811 +#define MT6363_RG_BUCK_VBUCK7_RC10_OP_CFG_ADDR 0x1811 +#define MT6363_RG_BUCK_VBUCK7_RC11_OP_CFG_ADDR 0x1811 +#define MT6363_RG_BUCK_VBUCK7_RC12_OP_CFG_ADDR 0x1811 +#define MT6363_RG_BUCK_VBUCK7_RC13_OP_CFG_ADDR 0x1811 +#define MT6363_RG_BUCK_VBUCK7_HW0_OP_CFG_ADDR 0x1812 +#define MT6363_RG_BUCK_VBUCK7_HW1_OP_CFG_ADDR 0x1812 +#define MT6363_RG_BUCK_VBUCK7_HW2_OP_CFG_ADDR 0x1812 +#define MT6363_RG_BUCK_VBUCK7_HW3_OP_CFG_ADDR 0x1812 +#define MT6363_RG_BUCK_VBUCK7_RC0_OP_MODE_ADDR 0x1813 +#define MT6363_RG_BUCK_VBUCK7_RC1_OP_MODE_ADDR 0x1813 +#define MT6363_RG_BUCK_VBUCK7_RC2_OP_MODE_ADDR 0x1813 +#define MT6363_RG_BUCK_VBUCK7_RC3_OP_MODE_ADDR 0x1813 +#define MT6363_RG_BUCK_VBUCK7_RC4_OP_MODE_ADDR 0x1813 +#define MT6363_RG_BUCK_VBUCK7_RC5_OP_MODE_ADDR 0x1813 +#define MT6363_RG_BUCK_VBUCK7_RC6_OP_MODE_ADDR 0x1813 +#define MT6363_RG_BUCK_VBUCK7_RC7_OP_MODE_ADDR 0x1813 +#define MT6363_RG_BUCK_VBUCK7_RC8_OP_MODE_ADDR 0x1814 +#define MT6363_RG_BUCK_VBUCK7_RC9_OP_MODE_ADDR 0x1814 +#define MT6363_RG_BUCK_VBUCK7_RC10_OP_MODE_ADDR 0x1814 +#define MT6363_RG_BUCK_VBUCK7_RC11_OP_MODE_ADDR 0x1814 +#define MT6363_RG_BUCK_VBUCK7_RC12_OP_MODE_ADDR 0x1814 +#define MT6363_RG_BUCK_VBUCK7_RC13_OP_MODE_ADDR 0x1814 +#define MT6363_RG_BUCK_VBUCK7_HW0_OP_MODE_ADDR 0x1815 +#define MT6363_RG_BUCK_VBUCK7_HW1_OP_MODE_ADDR 0x1815 +#define MT6363_RG_BUCK_VBUCK7_HW2_OP_MODE_ADDR 0x1815 +#define MT6363_RG_BUCK_VBUCK7_HW3_OP_MODE_ADDR 0x1815 +#define MT6363_RG_BUCK_VS1_VOSEL_SLEEP_ADDR 0x1887 +#define MT6363_RG_BUCK_VS1_ONLV_EN_ADDR 0x1888 +#define MT6363_RG_BUCK_VS1_ONLV_EN_SHIFT 4 +#define MT6363_RG_BUCK_VS1_RC0_OP_EN_ADDR 0x188D +#define MT6363_RG_BUCK_VS1_RC1_OP_EN_ADDR 0x188D +#define MT6363_RG_BUCK_VS1_RC2_OP_EN_ADDR 0x188D +#define MT6363_RG_BUCK_VS1_RC3_OP_EN_ADDR 0x188D +#define MT6363_RG_BUCK_VS1_RC4_OP_EN_ADDR 0x188D +#define MT6363_RG_BUCK_VS1_RC5_OP_EN_ADDR 0x188D +#define MT6363_RG_BUCK_VS1_RC6_OP_EN_ADDR 0x188D +#define MT6363_RG_BUCK_VS1_RC7_OP_EN_ADDR 0x188D +#define MT6363_RG_BUCK_VS1_RC8_OP_EN_ADDR 0x188E +#define MT6363_RG_BUCK_VS1_RC9_OP_EN_ADDR 0x188E +#define MT6363_RG_BUCK_VS1_RC10_OP_EN_ADDR 0x188E +#define MT6363_RG_BUCK_VS1_RC11_OP_EN_ADDR 0x188E +#define MT6363_RG_BUCK_VS1_RC12_OP_EN_ADDR 0x188E +#define MT6363_RG_BUCK_VS1_RC13_OP_EN_ADDR 0x188E +#define MT6363_RG_BUCK_VS1_HW0_OP_EN_ADDR 0x188F +#define MT6363_RG_BUCK_VS1_HW1_OP_EN_ADDR 0x188F +#define MT6363_RG_BUCK_VS1_HW2_OP_EN_ADDR 0x188F +#define MT6363_RG_BUCK_VS1_HW3_OP_EN_ADDR 0x188F +#define MT6363_RG_BUCK_VS1_HW4_OP_EN_ADDR 0x188F +#define MT6363_RG_BUCK_VS1_SW_OP_EN_ADDR 0x188F +#define MT6363_RG_BUCK_VS1_RC0_OP_CFG_ADDR 0x1890 +#define MT6363_RG_BUCK_VS1_RC1_OP_CFG_ADDR 0x1890 +#define MT6363_RG_BUCK_VS1_RC2_OP_CFG_ADDR 0x1890 +#define MT6363_RG_BUCK_VS1_RC3_OP_CFG_ADDR 0x1890 +#define MT6363_RG_BUCK_VS1_RC4_OP_CFG_ADDR 0x1890 +#define MT6363_RG_BUCK_VS1_RC5_OP_CFG_ADDR 0x1890 +#define MT6363_RG_BUCK_VS1_RC6_OP_CFG_ADDR 0x1890 +#define MT6363_RG_BUCK_VS1_RC7_OP_CFG_ADDR 0x1890 +#define MT6363_RG_BUCK_VS1_RC8_OP_CFG_ADDR 0x1891 +#define MT6363_RG_BUCK_VS1_RC9_OP_CFG_ADDR 0x1891 +#define MT6363_RG_BUCK_VS1_RC10_OP_CFG_ADDR 0x1891 +#define MT6363_RG_BUCK_VS1_RC11_OP_CFG_ADDR 0x1891 +#define MT6363_RG_BUCK_VS1_RC12_OP_CFG_ADDR 0x1891 +#define MT6363_RG_BUCK_VS1_RC13_OP_CFG_ADDR 0x1891 +#define MT6363_RG_BUCK_VS1_HW0_OP_CFG_ADDR 0x1892 +#define MT6363_RG_BUCK_VS1_HW1_OP_CFG_ADDR 0x1892 +#define MT6363_RG_BUCK_VS1_HW2_OP_CFG_ADDR 0x1892 +#define MT6363_RG_BUCK_VS1_HW3_OP_CFG_ADDR 0x1892 +#define MT6363_RG_BUCK_VS1_HW4_OP_CFG_ADDR 0x1892 +#define MT6363_RG_BUCK_VS1_RC0_OP_MODE_ADDR 0x1893 +#define MT6363_RG_BUCK_VS1_RC1_OP_MODE_ADDR 0x1893 +#define MT6363_RG_BUCK_VS1_RC2_OP_MODE_ADDR 0x1893 +#define MT6363_RG_BUCK_VS1_RC3_OP_MODE_ADDR 0x1893 +#define MT6363_RG_BUCK_VS1_RC4_OP_MODE_ADDR 0x1893 +#define MT6363_RG_BUCK_VS1_RC5_OP_MODE_ADDR 0x1893 +#define MT6363_RG_BUCK_VS1_RC6_OP_MODE_ADDR 0x1893 +#define MT6363_RG_BUCK_VS1_RC7_OP_MODE_ADDR 0x1893 +#define MT6363_RG_BUCK_VS1_RC8_OP_MODE_ADDR 0x1894 +#define MT6363_RG_BUCK_VS1_RC9_OP_MODE_ADDR 0x1894 +#define MT6363_RG_BUCK_VS1_RC10_OP_MODE_ADDR 0x1894 +#define MT6363_RG_BUCK_VS1_RC11_OP_MODE_ADDR 0x1894 +#define MT6363_RG_BUCK_VS1_RC12_OP_MODE_ADDR 0x1894 +#define MT6363_RG_BUCK_VS1_RC13_OP_MODE_ADDR 0x1894 +#define MT6363_RG_BUCK_VS1_HW0_OP_MODE_ADDR 0x1895 +#define MT6363_RG_BUCK_VS1_HW1_OP_MODE_ADDR 0x1895 +#define MT6363_RG_BUCK_VS1_HW2_OP_MODE_ADDR 0x1895 +#define MT6363_RG_BUCK_VS1_HW3_OP_MODE_ADDR 0x1895 +#define MT6363_RG_BUCK_VS1_HW4_OP_MODE_ADDR 0x1895 +#define MT6363_RG_BUCK_VS3_VOSEL_SLEEP_ADDR 0x1907 +#define MT6363_RG_BUCK_VS3_ONLV_EN_ADDR 0x1908 +#define MT6363_RG_BUCK_VS3_ONLV_EN_SHIFT 4 +#define MT6363_RG_BUCK_VS3_RC0_OP_EN_ADDR 0x190D +#define MT6363_RG_BUCK_VS3_RC1_OP_EN_ADDR 0x190D +#define MT6363_RG_BUCK_VS3_RC2_OP_EN_ADDR 0x190D +#define MT6363_RG_BUCK_VS3_RC3_OP_EN_ADDR 0x190D +#define MT6363_RG_BUCK_VS3_RC4_OP_EN_ADDR 0x190D +#define MT6363_RG_BUCK_VS3_RC5_OP_EN_ADDR 0x190D +#define MT6363_RG_BUCK_VS3_RC6_OP_EN_ADDR 0x190D +#define MT6363_RG_BUCK_VS3_RC7_OP_EN_ADDR 0x190D +#define MT6363_RG_BUCK_VS3_RC8_OP_EN_ADDR 0x190E +#define MT6363_RG_BUCK_VS3_RC9_OP_EN_ADDR 0x190E +#define MT6363_RG_BUCK_VS3_RC10_OP_EN_ADDR 0x190E +#define MT6363_RG_BUCK_VS3_RC11_OP_EN_ADDR 0x190E +#define MT6363_RG_BUCK_VS3_RC12_OP_EN_ADDR 0x190E +#define MT6363_RG_BUCK_VS3_RC13_OP_EN_ADDR 0x190E +#define MT6363_RG_BUCK_VS3_HW0_OP_EN_ADDR 0x190F +#define MT6363_RG_BUCK_VS3_HW1_OP_EN_ADDR 0x190F +#define MT6363_RG_BUCK_VS3_HW2_OP_EN_ADDR 0x190F +#define MT6363_RG_BUCK_VS3_HW3_OP_EN_ADDR 0x190F +#define MT6363_RG_BUCK_VS3_HW4_OP_EN_ADDR 0x190F +#define MT6363_RG_BUCK_VS3_SW_OP_EN_ADDR 0x190F +#define MT6363_RG_BUCK_VS3_RC0_OP_CFG_ADDR 0x1910 +#define MT6363_RG_BUCK_VS3_RC1_OP_CFG_ADDR 0x1910 +#define MT6363_RG_BUCK_VS3_RC2_OP_CFG_ADDR 0x1910 +#define MT6363_RG_BUCK_VS3_RC3_OP_CFG_ADDR 0x1910 +#define MT6363_RG_BUCK_VS3_RC4_OP_CFG_ADDR 0x1910 +#define MT6363_RG_BUCK_VS3_RC5_OP_CFG_ADDR 0x1910 +#define MT6363_RG_BUCK_VS3_RC6_OP_CFG_ADDR 0x1910 +#define MT6363_RG_BUCK_VS3_RC7_OP_CFG_ADDR 0x1910 +#define MT6363_RG_BUCK_VS3_RC8_OP_CFG_ADDR 0x1911 +#define MT6363_RG_BUCK_VS3_RC9_OP_CFG_ADDR 0x1911 +#define MT6363_RG_BUCK_VS3_RC10_OP_CFG_ADDR 0x1911 +#define MT6363_RG_BUCK_VS3_RC11_OP_CFG_ADDR 0x1911 +#define MT6363_RG_BUCK_VS3_RC12_OP_CFG_ADDR 0x1911 +#define MT6363_RG_BUCK_VS3_RC13_OP_CFG_ADDR 0x1911 +#define MT6363_RG_BUCK_VS3_HW0_OP_CFG_ADDR 0x1912 +#define MT6363_RG_BUCK_VS3_HW1_OP_CFG_ADDR 0x1912 +#define MT6363_RG_BUCK_VS3_HW2_OP_CFG_ADDR 0x1912 +#define MT6363_RG_BUCK_VS3_HW3_OP_CFG_ADDR 0x1912 +#define MT6363_RG_BUCK_VS3_HW4_OP_CFG_ADDR 0x1912 +#define MT6363_RG_BUCK_VS3_RC0_OP_MODE_ADDR 0x1913 +#define MT6363_RG_BUCK_VS3_RC1_OP_MODE_ADDR 0x1913 +#define MT6363_RG_BUCK_VS3_RC2_OP_MODE_ADDR 0x1913 +#define MT6363_RG_BUCK_VS3_RC3_OP_MODE_ADDR 0x1913 +#define MT6363_RG_BUCK_VS3_RC4_OP_MODE_ADDR 0x1913 +#define MT6363_RG_BUCK_VS3_RC5_OP_MODE_ADDR 0x1913 +#define MT6363_RG_BUCK_VS3_RC6_OP_MODE_ADDR 0x1913 +#define MT6363_RG_BUCK_VS3_RC7_OP_MODE_ADDR 0x1913 +#define MT6363_RG_BUCK_VS3_RC8_OP_MODE_ADDR 0x1914 +#define MT6363_RG_BUCK_VS3_RC9_OP_MODE_ADDR 0x1914 +#define MT6363_RG_BUCK_VS3_RC10_OP_MODE_ADDR 0x1914 +#define MT6363_RG_BUCK_VS3_RC11_OP_MODE_ADDR 0x1914 +#define MT6363_RG_BUCK_VS3_RC12_OP_MODE_ADDR 0x1914 +#define MT6363_RG_BUCK_VS3_RC13_OP_MODE_ADDR 0x1914 +#define MT6363_RG_BUCK_VS3_HW0_OP_MODE_ADDR 0x1915 +#define MT6363_RG_BUCK_VS3_HW1_OP_MODE_ADDR 0x1915 +#define MT6363_RG_BUCK_VS3_HW2_OP_MODE_ADDR 0x1915 +#define MT6363_RG_BUCK_VS3_HW3_OP_MODE_ADDR 0x1915 +#define MT6363_RG_BUCK_VS3_HW4_OP_MODE_ADDR 0x1915 +#define MT6363_RG_LDO_VCN15_ONLV_EN_ADDR 0x1B88 +#define MT6363_RG_LDO_VCN15_ONLV_EN_SHIFT 3 +#define MT6363_RG_LDO_VCN15_RC0_OP_EN_ADDR 0x1B8C +#define MT6363_RG_LDO_VCN15_RC1_OP_EN_ADDR 0x1B8C +#define MT6363_RG_LDO_VCN15_RC2_OP_EN_ADDR 0x1B8C +#define MT6363_RG_LDO_VCN15_RC3_OP_EN_ADDR 0x1B8C +#define MT6363_RG_LDO_VCN15_RC4_OP_EN_ADDR 0x1B8C +#define MT6363_RG_LDO_VCN15_RC5_OP_EN_ADDR 0x1B8C +#define MT6363_RG_LDO_VCN15_RC6_OP_EN_ADDR 0x1B8C +#define MT6363_RG_LDO_VCN15_RC7_OP_EN_ADDR 0x1B8C +#define MT6363_RG_LDO_VCN15_RC8_OP_EN_ADDR 0x1B8D +#define MT6363_RG_LDO_VCN15_RC9_OP_EN_ADDR 0x1B8D +#define MT6363_RG_LDO_VCN15_RC10_OP_EN_ADDR 0x1B8D +#define MT6363_RG_LDO_VCN15_RC11_OP_EN_ADDR 0x1B8D +#define MT6363_RG_LDO_VCN15_RC12_OP_EN_ADDR 0x1B8D +#define MT6363_RG_LDO_VCN15_RC13_OP_EN_ADDR 0x1B8D +#define MT6363_RG_LDO_VCN15_HW0_OP_EN_ADDR 0x1B8E +#define MT6363_RG_LDO_VCN15_HW1_OP_EN_ADDR 0x1B8E +#define MT6363_RG_LDO_VCN15_HW2_OP_EN_ADDR 0x1B8E +#define MT6363_RG_LDO_VCN15_HW3_OP_EN_ADDR 0x1B8E +#define MT6363_RG_LDO_VCN15_HW4_OP_EN_ADDR 0x1B8E +#define MT6363_RG_LDO_VCN15_HW5_OP_EN_ADDR 0x1B8E +#define MT6363_RG_LDO_VCN15_HW6_OP_EN_ADDR 0x1B8E +#define MT6363_RG_LDO_VCN15_SW_OP_EN_ADDR 0x1B8E +#define MT6363_RG_LDO_VCN15_RC0_OP_CFG_ADDR 0x1B8F +#define MT6363_RG_LDO_VCN15_RC1_OP_CFG_ADDR 0x1B8F +#define MT6363_RG_LDO_VCN15_RC2_OP_CFG_ADDR 0x1B8F +#define MT6363_RG_LDO_VCN15_RC3_OP_CFG_ADDR 0x1B8F +#define MT6363_RG_LDO_VCN15_RC4_OP_CFG_ADDR 0x1B8F +#define MT6363_RG_LDO_VCN15_RC5_OP_CFG_ADDR 0x1B8F +#define MT6363_RG_LDO_VCN15_RC6_OP_CFG_ADDR 0x1B8F +#define MT6363_RG_LDO_VCN15_RC7_OP_CFG_ADDR 0x1B8F +#define MT6363_RG_LDO_VCN15_RC8_OP_CFG_ADDR 0x1B90 +#define MT6363_RG_LDO_VCN15_RC9_OP_CFG_ADDR 0x1B90 +#define MT6363_RG_LDO_VCN15_RC10_OP_CFG_ADDR 0x1B90 +#define MT6363_RG_LDO_VCN15_RC11_OP_CFG_ADDR 0x1B90 +#define MT6363_RG_LDO_VCN15_RC12_OP_CFG_ADDR 0x1B90 +#define MT6363_RG_LDO_VCN15_RC13_OP_CFG_ADDR 0x1B90 +#define MT6363_RG_LDO_VCN15_HW0_OP_CFG_ADDR 0x1B91 +#define MT6363_RG_LDO_VCN15_HW1_OP_CFG_ADDR 0x1B91 +#define MT6363_RG_LDO_VCN15_HW2_OP_CFG_ADDR 0x1B91 +#define MT6363_RG_LDO_VCN15_HW3_OP_CFG_ADDR 0x1B91 +#define MT6363_RG_LDO_VCN15_HW4_OP_CFG_ADDR 0x1B91 +#define MT6363_RG_LDO_VCN15_HW5_OP_CFG_ADDR 0x1B91 +#define MT6363_RG_LDO_VCN15_HW6_OP_CFG_ADDR 0x1B91 +#define MT6363_RG_LDO_VCN15_SW_OP_CFG_ADDR 0x1B91 +#define MT6363_RG_LDO_VCN15_RC0_OP_MODE_ADDR 0x1B92 +#define MT6363_RG_LDO_VCN15_RC1_OP_MODE_ADDR 0x1B92 +#define MT6363_RG_LDO_VCN15_RC2_OP_MODE_ADDR 0x1B92 +#define MT6363_RG_LDO_VCN15_RC3_OP_MODE_ADDR 0x1B92 +#define MT6363_RG_LDO_VCN15_RC4_OP_MODE_ADDR 0x1B92 +#define MT6363_RG_LDO_VCN15_RC5_OP_MODE_ADDR 0x1B92 +#define MT6363_RG_LDO_VCN15_RC6_OP_MODE_ADDR 0x1B92 +#define MT6363_RG_LDO_VCN15_RC7_OP_MODE_ADDR 0x1B92 +#define MT6363_RG_LDO_VCN15_RC8_OP_MODE_ADDR 0x1B93 +#define MT6363_RG_LDO_VCN15_RC9_OP_MODE_ADDR 0x1B93 +#define MT6363_RG_LDO_VCN15_RC10_OP_MODE_ADDR 0x1B93 +#define MT6363_RG_LDO_VCN15_RC11_OP_MODE_ADDR 0x1B93 +#define MT6363_RG_LDO_VCN15_RC12_OP_MODE_ADDR 0x1B93 +#define MT6363_RG_LDO_VCN15_RC13_OP_MODE_ADDR 0x1B93 +#define MT6363_RG_LDO_VCN15_HW0_OP_MODE_ADDR 0x1B94 +#define MT6363_RG_LDO_VCN15_HW1_OP_MODE_ADDR 0x1B94 +#define MT6363_RG_LDO_VCN15_HW2_OP_MODE_ADDR 0x1B94 +#define MT6363_RG_LDO_VCN15_HW3_OP_MODE_ADDR 0x1B94 +#define MT6363_RG_LDO_VCN15_HW4_OP_MODE_ADDR 0x1B94 +#define MT6363_RG_LDO_VCN15_HW5_OP_MODE_ADDR 0x1B94 +#define MT6363_RG_LDO_VCN15_HW6_OP_MODE_ADDR 0x1B94 +#define MT6363_RG_LDO_VRF09_ONLV_EN_ADDR 0x1B96 +#define MT6363_RG_LDO_VRF09_ONLV_EN_SHIFT 3 +#define MT6363_RG_LDO_VRF09_RC0_OP_EN_ADDR 0x1B9A +#define MT6363_RG_LDO_VRF09_RC1_OP_EN_ADDR 0x1B9A +#define MT6363_RG_LDO_VRF09_RC2_OP_EN_ADDR 0x1B9A +#define MT6363_RG_LDO_VRF09_RC3_OP_EN_ADDR 0x1B9A +#define MT6363_RG_LDO_VRF09_RC4_OP_EN_ADDR 0x1B9A +#define MT6363_RG_LDO_VRF09_RC5_OP_EN_ADDR 0x1B9A +#define MT6363_RG_LDO_VRF09_RC6_OP_EN_ADDR 0x1B9A +#define MT6363_RG_LDO_VRF09_RC7_OP_EN_ADDR 0x1B9A +#define MT6363_RG_LDO_VRF09_RC8_OP_EN_ADDR 0x1B9B +#define MT6363_RG_LDO_VRF09_RC9_OP_EN_ADDR 0x1B9B +#define MT6363_RG_LDO_VRF09_RC10_OP_EN_ADDR 0x1B9B +#define MT6363_RG_LDO_VRF09_RC11_OP_EN_ADDR 0x1B9B +#define MT6363_RG_LDO_VRF09_RC12_OP_EN_ADDR 0x1B9B +#define MT6363_RG_LDO_VRF09_RC13_OP_EN_ADDR 0x1B9B +#define MT6363_RG_LDO_VRF09_HW0_OP_EN_ADDR 0x1B9C +#define MT6363_RG_LDO_VRF09_HW1_OP_EN_ADDR 0x1B9C +#define MT6363_RG_LDO_VRF09_HW2_OP_EN_ADDR 0x1B9C +#define MT6363_RG_LDO_VRF09_HW3_OP_EN_ADDR 0x1B9C +#define MT6363_RG_LDO_VRF09_HW4_OP_EN_ADDR 0x1B9C +#define MT6363_RG_LDO_VRF09_HW5_OP_EN_ADDR 0x1B9C +#define MT6363_RG_LDO_VRF09_HW6_OP_EN_ADDR 0x1B9C +#define MT6363_RG_LDO_VRF09_SW_OP_EN_ADDR 0x1B9C +#define MT6363_RG_LDO_VRF09_RC0_OP_CFG_ADDR 0x1B9D +#define MT6363_RG_LDO_VRF09_RC1_OP_CFG_ADDR 0x1B9D +#define MT6363_RG_LDO_VRF09_RC2_OP_CFG_ADDR 0x1B9D +#define MT6363_RG_LDO_VRF09_RC3_OP_CFG_ADDR 0x1B9D +#define MT6363_RG_LDO_VRF09_RC4_OP_CFG_ADDR 0x1B9D +#define MT6363_RG_LDO_VRF09_RC5_OP_CFG_ADDR 0x1B9D +#define MT6363_RG_LDO_VRF09_RC6_OP_CFG_ADDR 0x1B9D +#define MT6363_RG_LDO_VRF09_RC7_OP_CFG_ADDR 0x1B9D +#define MT6363_RG_LDO_VRF09_RC8_OP_CFG_ADDR 0x1B9E +#define MT6363_RG_LDO_VRF09_RC9_OP_CFG_ADDR 0x1B9E +#define MT6363_RG_LDO_VRF09_RC10_OP_CFG_ADDR 0x1B9E +#define MT6363_RG_LDO_VRF09_RC11_OP_CFG_ADDR 0x1B9E +#define MT6363_RG_LDO_VRF09_RC12_OP_CFG_ADDR 0x1B9E +#define MT6363_RG_LDO_VRF09_RC13_OP_CFG_ADDR 0x1B9E +#define MT6363_RG_LDO_VRF09_HW0_OP_CFG_ADDR 0x1B9F +#define MT6363_RG_LDO_VRF09_HW1_OP_CFG_ADDR 0x1B9F +#define MT6363_RG_LDO_VRF09_HW2_OP_CFG_ADDR 0x1B9F +#define MT6363_RG_LDO_VRF09_HW3_OP_CFG_ADDR 0x1B9F +#define MT6363_RG_LDO_VRF09_HW4_OP_CFG_ADDR 0x1B9F +#define MT6363_RG_LDO_VRF09_HW5_OP_CFG_ADDR 0x1B9F +#define MT6363_RG_LDO_VRF09_HW6_OP_CFG_ADDR 0x1B9F +#define MT6363_RG_LDO_VRF09_SW_OP_CFG_ADDR 0x1B9F +#define MT6363_RG_LDO_VRF09_RC0_OP_MODE_ADDR 0x1BA0 +#define MT6363_RG_LDO_VRF09_RC1_OP_MODE_ADDR 0x1BA0 +#define MT6363_RG_LDO_VRF09_RC2_OP_MODE_ADDR 0x1BA0 +#define MT6363_RG_LDO_VRF09_RC3_OP_MODE_ADDR 0x1BA0 +#define MT6363_RG_LDO_VRF09_RC4_OP_MODE_ADDR 0x1BA0 +#define MT6363_RG_LDO_VRF09_RC5_OP_MODE_ADDR 0x1BA0 +#define MT6363_RG_LDO_VRF09_RC6_OP_MODE_ADDR 0x1BA0 +#define MT6363_RG_LDO_VRF09_RC7_OP_MODE_ADDR 0x1BA0 +#define MT6363_RG_LDO_VRF09_RC8_OP_MODE_ADDR 0x1BA1 +#define MT6363_RG_LDO_VRF09_RC9_OP_MODE_ADDR 0x1BA1 +#define MT6363_RG_LDO_VRF09_RC10_OP_MODE_ADDR 0x1BA1 +#define MT6363_RG_LDO_VRF09_RC11_OP_MODE_ADDR 0x1BA1 +#define MT6363_RG_LDO_VRF09_RC12_OP_MODE_ADDR 0x1BA1 +#define MT6363_RG_LDO_VRF09_RC13_OP_MODE_ADDR 0x1BA1 +#define MT6363_RG_LDO_VRF09_HW0_OP_MODE_ADDR 0x1BA2 +#define MT6363_RG_LDO_VRF09_HW1_OP_MODE_ADDR 0x1BA2 +#define MT6363_RG_LDO_VRF09_HW2_OP_MODE_ADDR 0x1BA2 +#define MT6363_RG_LDO_VRF09_HW3_OP_MODE_ADDR 0x1BA2 +#define MT6363_RG_LDO_VRF09_HW4_OP_MODE_ADDR 0x1BA2 +#define MT6363_RG_LDO_VRF09_HW5_OP_MODE_ADDR 0x1BA2 +#define MT6363_RG_LDO_VRF09_HW6_OP_MODE_ADDR 0x1BA2 +#define MT6363_RG_LDO_VRF12_ONLV_EN_ADDR 0x1BA4 +#define MT6363_RG_LDO_VRF12_ONLV_EN_SHIFT 3 +#define MT6363_RG_LDO_VRF12_RC0_OP_EN_ADDR 0x1BA8 +#define MT6363_RG_LDO_VRF12_RC1_OP_EN_ADDR 0x1BA8 +#define MT6363_RG_LDO_VRF12_RC2_OP_EN_ADDR 0x1BA8 +#define MT6363_RG_LDO_VRF12_RC3_OP_EN_ADDR 0x1BA8 +#define MT6363_RG_LDO_VRF12_RC4_OP_EN_ADDR 0x1BA8 +#define MT6363_RG_LDO_VRF12_RC5_OP_EN_ADDR 0x1BA8 +#define MT6363_RG_LDO_VRF12_RC6_OP_EN_ADDR 0x1BA8 +#define MT6363_RG_LDO_VRF12_RC7_OP_EN_ADDR 0x1BA8 +#define MT6363_RG_LDO_VRF12_RC8_OP_EN_ADDR 0x1BA9 +#define MT6363_RG_LDO_VRF12_RC9_OP_EN_ADDR 0x1BA9 +#define MT6363_RG_LDO_VRF12_RC10_OP_EN_ADDR 0x1BA9 +#define MT6363_RG_LDO_VRF12_RC11_OP_EN_ADDR 0x1BA9 +#define MT6363_RG_LDO_VRF12_RC12_OP_EN_ADDR 0x1BA9 +#define MT6363_RG_LDO_VRF12_RC13_OP_EN_ADDR 0x1BA9 +#define MT6363_RG_LDO_VRF12_HW0_OP_EN_ADDR 0x1BAA +#define MT6363_RG_LDO_VRF12_HW1_OP_EN_ADDR 0x1BAA +#define MT6363_RG_LDO_VRF12_HW2_OP_EN_ADDR 0x1BAA +#define MT6363_RG_LDO_VRF12_HW3_OP_EN_ADDR 0x1BAA +#define MT6363_RG_LDO_VRF12_HW4_OP_EN_ADDR 0x1BAA +#define MT6363_RG_LDO_VRF12_HW5_OP_EN_ADDR 0x1BAA +#define MT6363_RG_LDO_VRF12_HW6_OP_EN_ADDR 0x1BAA +#define MT6363_RG_LDO_VRF12_SW_OP_EN_ADDR 0x1BAA +#define MT6363_RG_LDO_VRF12_RC0_OP_CFG_ADDR 0x1BAB +#define MT6363_RG_LDO_VRF12_RC1_OP_CFG_ADDR 0x1BAB +#define MT6363_RG_LDO_VRF12_RC2_OP_CFG_ADDR 0x1BAB +#define MT6363_RG_LDO_VRF12_RC3_OP_CFG_ADDR 0x1BAB +#define MT6363_RG_LDO_VRF12_RC4_OP_CFG_ADDR 0x1BAB +#define MT6363_RG_LDO_VRF12_RC5_OP_CFG_ADDR 0x1BAB +#define MT6363_RG_LDO_VRF12_RC6_OP_CFG_ADDR 0x1BAB +#define MT6363_RG_LDO_VRF12_RC7_OP_CFG_ADDR 0x1BAB +#define MT6363_RG_LDO_VRF12_RC8_OP_CFG_ADDR 0x1BAC +#define MT6363_RG_LDO_VRF12_RC9_OP_CFG_ADDR 0x1BAC +#define MT6363_RG_LDO_VRF12_RC10_OP_CFG_ADDR 0x1BAC +#define MT6363_RG_LDO_VRF12_RC11_OP_CFG_ADDR 0x1BAC +#define MT6363_RG_LDO_VRF12_RC12_OP_CFG_ADDR 0x1BAC +#define MT6363_RG_LDO_VRF12_RC13_OP_CFG_ADDR 0x1BAC +#define MT6363_RG_LDO_VRF12_HW0_OP_CFG_ADDR 0x1BAD +#define MT6363_RG_LDO_VRF12_HW1_OP_CFG_ADDR 0x1BAD +#define MT6363_RG_LDO_VRF12_HW2_OP_CFG_ADDR 0x1BAD +#define MT6363_RG_LDO_VRF12_HW3_OP_CFG_ADDR 0x1BAD +#define MT6363_RG_LDO_VRF12_HW4_OP_CFG_ADDR 0x1BAD +#define MT6363_RG_LDO_VRF12_HW5_OP_CFG_ADDR 0x1BAD +#define MT6363_RG_LDO_VRF12_HW6_OP_CFG_ADDR 0x1BAD +#define MT6363_RG_LDO_VRF12_SW_OP_CFG_ADDR 0x1BAD +#define MT6363_RG_LDO_VRF12_RC0_OP_MODE_ADDR 0x1BAE +#define MT6363_RG_LDO_VRF12_RC1_OP_MODE_ADDR 0x1BAE +#define MT6363_RG_LDO_VRF12_RC2_OP_MODE_ADDR 0x1BAE +#define MT6363_RG_LDO_VRF12_RC3_OP_MODE_ADDR 0x1BAE +#define MT6363_RG_LDO_VRF12_RC4_OP_MODE_ADDR 0x1BAE +#define MT6363_RG_LDO_VRF12_RC5_OP_MODE_ADDR 0x1BAE +#define MT6363_RG_LDO_VRF12_RC6_OP_MODE_ADDR 0x1BAE +#define MT6363_RG_LDO_VRF12_RC7_OP_MODE_ADDR 0x1BAE +#define MT6363_RG_LDO_VRF12_RC8_OP_MODE_ADDR 0x1BAF +#define MT6363_RG_LDO_VRF12_RC9_OP_MODE_ADDR 0x1BAF +#define MT6363_RG_LDO_VRF12_RC10_OP_MODE_ADDR 0x1BAF +#define MT6363_RG_LDO_VRF12_RC11_OP_MODE_ADDR 0x1BAF +#define MT6363_RG_LDO_VRF12_RC12_OP_MODE_ADDR 0x1BAF +#define MT6363_RG_LDO_VRF12_RC13_OP_MODE_ADDR 0x1BAF +#define MT6363_RG_LDO_VRF12_HW0_OP_MODE_ADDR 0x1BB0 +#define MT6363_RG_LDO_VRF12_HW1_OP_MODE_ADDR 0x1BB0 +#define MT6363_RG_LDO_VRF12_HW2_OP_MODE_ADDR 0x1BB0 +#define MT6363_RG_LDO_VRF12_HW3_OP_MODE_ADDR 0x1BB0 +#define MT6363_RG_LDO_VRF12_HW4_OP_MODE_ADDR 0x1BB0 +#define MT6363_RG_LDO_VRF12_HW5_OP_MODE_ADDR 0x1BB0 +#define MT6363_RG_LDO_VRF12_HW6_OP_MODE_ADDR 0x1BB0 +#define MT6363_RG_LDO_VRF13_ONLV_EN_ADDR 0x1BB2 +#define MT6363_RG_LDO_VRF13_ONLV_EN_SHIFT 3 +#define MT6363_RG_LDO_VRF13_RC0_OP_EN_ADDR 0x1BB6 +#define MT6363_RG_LDO_VRF13_RC1_OP_EN_ADDR 0x1BB6 +#define MT6363_RG_LDO_VRF13_RC2_OP_EN_ADDR 0x1BB6 +#define MT6363_RG_LDO_VRF13_RC3_OP_EN_ADDR 0x1BB6 +#define MT6363_RG_LDO_VRF13_RC4_OP_EN_ADDR 0x1BB6 +#define MT6363_RG_LDO_VRF13_RC5_OP_EN_ADDR 0x1BB6 +#define MT6363_RG_LDO_VRF13_RC6_OP_EN_ADDR 0x1BB6 +#define MT6363_RG_LDO_VRF13_RC7_OP_EN_ADDR 0x1BB6 +#define MT6363_RG_LDO_VRF13_RC8_OP_EN_ADDR 0x1BB7 +#define MT6363_RG_LDO_VRF13_RC9_OP_EN_ADDR 0x1BB7 +#define MT6363_RG_LDO_VRF13_RC10_OP_EN_ADDR 0x1BB7 +#define MT6363_RG_LDO_VRF13_RC11_OP_EN_ADDR 0x1BB7 +#define MT6363_RG_LDO_VRF13_RC12_OP_EN_ADDR 0x1BB7 +#define MT6363_RG_LDO_VRF13_RC13_OP_EN_ADDR 0x1BB7 +#define MT6363_RG_LDO_VRF13_HW0_OP_EN_ADDR 0x1BB8 +#define MT6363_RG_LDO_VRF13_HW1_OP_EN_ADDR 0x1BB8 +#define MT6363_RG_LDO_VRF13_HW2_OP_EN_ADDR 0x1BB8 +#define MT6363_RG_LDO_VRF13_HW3_OP_EN_ADDR 0x1BB8 +#define MT6363_RG_LDO_VRF13_HW4_OP_EN_ADDR 0x1BB8 +#define MT6363_RG_LDO_VRF13_HW5_OP_EN_ADDR 0x1BB8 +#define MT6363_RG_LDO_VRF13_HW6_OP_EN_ADDR 0x1BB8 +#define MT6363_RG_LDO_VRF13_SW_OP_EN_ADDR 0x1BB8 +#define MT6363_RG_LDO_VRF13_RC0_OP_CFG_ADDR 0x1BB9 +#define MT6363_RG_LDO_VRF13_RC1_OP_CFG_ADDR 0x1BB9 +#define MT6363_RG_LDO_VRF13_RC2_OP_CFG_ADDR 0x1BB9 +#define MT6363_RG_LDO_VRF13_RC3_OP_CFG_ADDR 0x1BB9 +#define MT6363_RG_LDO_VRF13_RC4_OP_CFG_ADDR 0x1BB9 +#define MT6363_RG_LDO_VRF13_RC5_OP_CFG_ADDR 0x1BB9 +#define MT6363_RG_LDO_VRF13_RC6_OP_CFG_ADDR 0x1BB9 +#define MT6363_RG_LDO_VRF13_RC7_OP_CFG_ADDR 0x1BB9 +#define MT6363_RG_LDO_VRF13_RC8_OP_CFG_ADDR 0x1BBA +#define MT6363_RG_LDO_VRF13_RC9_OP_CFG_ADDR 0x1BBA +#define MT6363_RG_LDO_VRF13_RC10_OP_CFG_ADDR 0x1BBA +#define MT6363_RG_LDO_VRF13_RC11_OP_CFG_ADDR 0x1BBA +#define MT6363_RG_LDO_VRF13_RC12_OP_CFG_ADDR 0x1BBA +#define MT6363_RG_LDO_VRF13_RC13_OP_CFG_ADDR 0x1BBA +#define MT6363_RG_LDO_VRF13_HW0_OP_CFG_ADDR 0x1BBB +#define MT6363_RG_LDO_VRF13_HW1_OP_CFG_ADDR 0x1BBB +#define MT6363_RG_LDO_VRF13_HW2_OP_CFG_ADDR 0x1BBB +#define MT6363_RG_LDO_VRF13_HW3_OP_CFG_ADDR 0x1BBB +#define MT6363_RG_LDO_VRF13_HW4_OP_CFG_ADDR 0x1BBB +#define MT6363_RG_LDO_VRF13_HW5_OP_CFG_ADDR 0x1BBB +#define MT6363_RG_LDO_VRF13_HW6_OP_CFG_ADDR 0x1BBB +#define MT6363_RG_LDO_VRF13_SW_OP_CFG_ADDR 0x1BBB +#define MT6363_RG_LDO_VRF13_RC0_OP_MODE_ADDR 0x1BBC +#define MT6363_RG_LDO_VRF13_RC1_OP_MODE_ADDR 0x1BBC +#define MT6363_RG_LDO_VRF13_RC2_OP_MODE_ADDR 0x1BBC +#define MT6363_RG_LDO_VRF13_RC3_OP_MODE_ADDR 0x1BBC +#define MT6363_RG_LDO_VRF13_RC4_OP_MODE_ADDR 0x1BBC +#define MT6363_RG_LDO_VRF13_RC5_OP_MODE_ADDR 0x1BBC +#define MT6363_RG_LDO_VRF13_RC6_OP_MODE_ADDR 0x1BBC +#define MT6363_RG_LDO_VRF13_RC7_OP_MODE_ADDR 0x1BBC +#define MT6363_RG_LDO_VRF13_RC8_OP_MODE_ADDR 0x1BBD +#define MT6363_RG_LDO_VRF13_RC9_OP_MODE_ADDR 0x1BBD +#define MT6363_RG_LDO_VRF13_RC10_OP_MODE_ADDR 0x1BBD +#define MT6363_RG_LDO_VRF13_RC11_OP_MODE_ADDR 0x1BBD +#define MT6363_RG_LDO_VRF13_RC12_OP_MODE_ADDR 0x1BBD +#define MT6363_RG_LDO_VRF13_RC13_OP_MODE_ADDR 0x1BBD +#define MT6363_RG_LDO_VRF13_HW0_OP_MODE_ADDR 0x1BBE +#define MT6363_RG_LDO_VRF13_HW1_OP_MODE_ADDR 0x1BBE +#define MT6363_RG_LDO_VRF13_HW2_OP_MODE_ADDR 0x1BBE +#define MT6363_RG_LDO_VRF13_HW3_OP_MODE_ADDR 0x1BBE +#define MT6363_RG_LDO_VRF13_HW4_OP_MODE_ADDR 0x1BBE +#define MT6363_RG_LDO_VRF13_HW5_OP_MODE_ADDR 0x1BBE +#define MT6363_RG_LDO_VRF13_HW6_OP_MODE_ADDR 0x1BBE +#define MT6363_RG_LDO_VRF18_ONLV_EN_ADDR 0x1BC0 +#define MT6363_RG_LDO_VRF18_ONLV_EN_SHIFT 3 +#define MT6363_RG_LDO_VRF18_RC0_OP_EN_ADDR 0x1BC4 +#define MT6363_RG_LDO_VRF18_RC1_OP_EN_ADDR 0x1BC4 +#define MT6363_RG_LDO_VRF18_RC2_OP_EN_ADDR 0x1BC4 +#define MT6363_RG_LDO_VRF18_RC3_OP_EN_ADDR 0x1BC4 +#define MT6363_RG_LDO_VRF18_RC4_OP_EN_ADDR 0x1BC4 +#define MT6363_RG_LDO_VRF18_RC5_OP_EN_ADDR 0x1BC4 +#define MT6363_RG_LDO_VRF18_RC6_OP_EN_ADDR 0x1BC4 +#define MT6363_RG_LDO_VRF18_RC7_OP_EN_ADDR 0x1BC4 +#define MT6363_RG_LDO_VRF18_RC8_OP_EN_ADDR 0x1BC5 +#define MT6363_RG_LDO_VRF18_RC9_OP_EN_ADDR 0x1BC5 +#define MT6363_RG_LDO_VRF18_RC10_OP_EN_ADDR 0x1BC5 +#define MT6363_RG_LDO_VRF18_RC11_OP_EN_ADDR 0x1BC5 +#define MT6363_RG_LDO_VRF18_RC12_OP_EN_ADDR 0x1BC5 +#define MT6363_RG_LDO_VRF18_RC13_OP_EN_ADDR 0x1BC5 +#define MT6363_RG_LDO_VRF18_HW0_OP_EN_ADDR 0x1BC6 +#define MT6363_RG_LDO_VRF18_HW1_OP_EN_ADDR 0x1BC6 +#define MT6363_RG_LDO_VRF18_HW2_OP_EN_ADDR 0x1BC6 +#define MT6363_RG_LDO_VRF18_HW3_OP_EN_ADDR 0x1BC6 +#define MT6363_RG_LDO_VRF18_HW4_OP_EN_ADDR 0x1BC6 +#define MT6363_RG_LDO_VRF18_HW5_OP_EN_ADDR 0x1BC6 +#define MT6363_RG_LDO_VRF18_HW6_OP_EN_ADDR 0x1BC6 +#define MT6363_RG_LDO_VRF18_SW_OP_EN_ADDR 0x1BC6 +#define MT6363_RG_LDO_VRF18_RC0_OP_CFG_ADDR 0x1BC7 +#define MT6363_RG_LDO_VRF18_RC1_OP_CFG_ADDR 0x1BC7 +#define MT6363_RG_LDO_VRF18_RC2_OP_CFG_ADDR 0x1BC7 +#define MT6363_RG_LDO_VRF18_RC3_OP_CFG_ADDR 0x1BC7 +#define MT6363_RG_LDO_VRF18_RC4_OP_CFG_ADDR 0x1BC7 +#define MT6363_RG_LDO_VRF18_RC5_OP_CFG_ADDR 0x1BC7 +#define MT6363_RG_LDO_VRF18_RC6_OP_CFG_ADDR 0x1BC7 +#define MT6363_RG_LDO_VRF18_RC7_OP_CFG_ADDR 0x1BC7 +#define MT6363_RG_LDO_VRF18_RC8_OP_CFG_ADDR 0x1BC8 +#define MT6363_RG_LDO_VRF18_RC9_OP_CFG_ADDR 0x1BC8 +#define MT6363_RG_LDO_VRF18_RC10_OP_CFG_ADDR 0x1BC8 +#define MT6363_RG_LDO_VRF18_RC11_OP_CFG_ADDR 0x1BC8 +#define MT6363_RG_LDO_VRF18_RC12_OP_CFG_ADDR 0x1BC8 +#define MT6363_RG_LDO_VRF18_RC13_OP_CFG_ADDR 0x1BC8 +#define MT6363_RG_LDO_VRF18_HW0_OP_CFG_ADDR 0x1BC9 +#define MT6363_RG_LDO_VRF18_HW1_OP_CFG_ADDR 0x1BC9 +#define MT6363_RG_LDO_VRF18_HW2_OP_CFG_ADDR 0x1BC9 +#define MT6363_RG_LDO_VRF18_HW3_OP_CFG_ADDR 0x1BC9 +#define MT6363_RG_LDO_VRF18_HW4_OP_CFG_ADDR 0x1BC9 +#define MT6363_RG_LDO_VRF18_HW5_OP_CFG_ADDR 0x1BC9 +#define MT6363_RG_LDO_VRF18_HW6_OP_CFG_ADDR 0x1BC9 +#define MT6363_RG_LDO_VRF18_SW_OP_CFG_ADDR 0x1BC9 +#define MT6363_RG_LDO_VRF18_RC0_OP_MODE_ADDR 0x1BCA +#define MT6363_RG_LDO_VRF18_RC1_OP_MODE_ADDR 0x1BCA +#define MT6363_RG_LDO_VRF18_RC2_OP_MODE_ADDR 0x1BCA +#define MT6363_RG_LDO_VRF18_RC3_OP_MODE_ADDR 0x1BCA +#define MT6363_RG_LDO_VRF18_RC4_OP_MODE_ADDR 0x1BCA +#define MT6363_RG_LDO_VRF18_RC5_OP_MODE_ADDR 0x1BCA +#define MT6363_RG_LDO_VRF18_RC6_OP_MODE_ADDR 0x1BCA +#define MT6363_RG_LDO_VRF18_RC7_OP_MODE_ADDR 0x1BCA +#define MT6363_RG_LDO_VRF18_RC8_OP_MODE_ADDR 0x1BCB +#define MT6363_RG_LDO_VRF18_RC9_OP_MODE_ADDR 0x1BCB +#define MT6363_RG_LDO_VRF18_RC10_OP_MODE_ADDR 0x1BCB +#define MT6363_RG_LDO_VRF18_RC11_OP_MODE_ADDR 0x1BCB +#define MT6363_RG_LDO_VRF18_RC12_OP_MODE_ADDR 0x1BCB +#define MT6363_RG_LDO_VRF18_RC13_OP_MODE_ADDR 0x1BCB +#define MT6363_RG_LDO_VRF18_HW0_OP_MODE_ADDR 0x1BCC +#define MT6363_RG_LDO_VRF18_HW1_OP_MODE_ADDR 0x1BCC +#define MT6363_RG_LDO_VRF18_HW2_OP_MODE_ADDR 0x1BCC +#define MT6363_RG_LDO_VRF18_HW3_OP_MODE_ADDR 0x1BCC +#define MT6363_RG_LDO_VRF18_HW4_OP_MODE_ADDR 0x1BCC +#define MT6363_RG_LDO_VRF18_HW5_OP_MODE_ADDR 0x1BCC +#define MT6363_RG_LDO_VRF18_HW6_OP_MODE_ADDR 0x1BCC +#define MT6363_RG_LDO_VRFIO18_ONLV_EN_ADDR 0x1BCE +#define MT6363_RG_LDO_VRFIO18_ONLV_EN_SHIFT 3 +#define MT6363_RG_LDO_VRFIO18_RC0_OP_EN_ADDR 0x1BD2 +#define MT6363_RG_LDO_VRFIO18_RC1_OP_EN_ADDR 0x1BD2 +#define MT6363_RG_LDO_VRFIO18_RC2_OP_EN_ADDR 0x1BD2 +#define MT6363_RG_LDO_VRFIO18_RC3_OP_EN_ADDR 0x1BD2 +#define MT6363_RG_LDO_VRFIO18_RC4_OP_EN_ADDR 0x1BD2 +#define MT6363_RG_LDO_VRFIO18_RC5_OP_EN_ADDR 0x1BD2 +#define MT6363_RG_LDO_VRFIO18_RC6_OP_EN_ADDR 0x1BD2 +#define MT6363_RG_LDO_VRFIO18_RC7_OP_EN_ADDR 0x1BD2 +#define MT6363_RG_LDO_VRFIO18_RC8_OP_EN_ADDR 0x1BD3 +#define MT6363_RG_LDO_VRFIO18_RC9_OP_EN_ADDR 0x1BD3 +#define MT6363_RG_LDO_VRFIO18_RC10_OP_EN_ADDR 0x1BD3 +#define MT6363_RG_LDO_VRFIO18_RC11_OP_EN_ADDR 0x1BD3 +#define MT6363_RG_LDO_VRFIO18_RC12_OP_EN_ADDR 0x1BD3 +#define MT6363_RG_LDO_VRFIO18_RC13_OP_EN_ADDR 0x1BD3 +#define MT6363_RG_LDO_VRFIO18_HW0_OP_EN_ADDR 0x1BD4 +#define MT6363_RG_LDO_VRFIO18_HW1_OP_EN_ADDR 0x1BD4 +#define MT6363_RG_LDO_VRFIO18_HW2_OP_EN_ADDR 0x1BD4 +#define MT6363_RG_LDO_VRFIO18_HW3_OP_EN_ADDR 0x1BD4 +#define MT6363_RG_LDO_VRFIO18_HW4_OP_EN_ADDR 0x1BD4 +#define MT6363_RG_LDO_VRFIO18_HW5_OP_EN_ADDR 0x1BD4 +#define MT6363_RG_LDO_VRFIO18_HW6_OP_EN_ADDR 0x1BD4 +#define MT6363_RG_LDO_VRFIO18_SW_OP_EN_ADDR 0x1BD4 +#define MT6363_RG_LDO_VRFIO18_RC0_OP_CFG_ADDR 0x1BD5 +#define MT6363_RG_LDO_VRFIO18_RC1_OP_CFG_ADDR 0x1BD5 +#define MT6363_RG_LDO_VRFIO18_RC2_OP_CFG_ADDR 0x1BD5 +#define MT6363_RG_LDO_VRFIO18_RC3_OP_CFG_ADDR 0x1BD5 +#define MT6363_RG_LDO_VRFIO18_RC4_OP_CFG_ADDR 0x1BD5 +#define MT6363_RG_LDO_VRFIO18_RC5_OP_CFG_ADDR 0x1BD5 +#define MT6363_RG_LDO_VRFIO18_RC6_OP_CFG_ADDR 0x1BD5 +#define MT6363_RG_LDO_VRFIO18_RC7_OP_CFG_ADDR 0x1BD5 +#define MT6363_RG_LDO_VRFIO18_RC8_OP_CFG_ADDR 0x1BD6 +#define MT6363_RG_LDO_VRFIO18_RC9_OP_CFG_ADDR 0x1BD6 +#define MT6363_RG_LDO_VRFIO18_RC10_OP_CFG_ADDR 0x1BD6 +#define MT6363_RG_LDO_VRFIO18_RC11_OP_CFG_ADDR 0x1BD6 +#define MT6363_RG_LDO_VRFIO18_RC12_OP_CFG_ADDR 0x1BD6 +#define MT6363_RG_LDO_VRFIO18_RC13_OP_CFG_ADDR 0x1BD6 +#define MT6363_RG_LDO_VRFIO18_HW0_OP_CFG_ADDR 0x1BD7 +#define MT6363_RG_LDO_VRFIO18_HW1_OP_CFG_ADDR 0x1BD7 +#define MT6363_RG_LDO_VRFIO18_HW2_OP_CFG_ADDR 0x1BD7 +#define MT6363_RG_LDO_VRFIO18_HW3_OP_CFG_ADDR 0x1BD7 +#define MT6363_RG_LDO_VRFIO18_HW4_OP_CFG_ADDR 0x1BD7 +#define MT6363_RG_LDO_VRFIO18_HW5_OP_CFG_ADDR 0x1BD7 +#define MT6363_RG_LDO_VRFIO18_HW6_OP_CFG_ADDR 0x1BD7 +#define MT6363_RG_LDO_VRFIO18_SW_OP_CFG_ADDR 0x1BD7 +#define MT6363_RG_LDO_VRFIO18_RC0_OP_MODE_ADDR 0x1BD8 +#define MT6363_RG_LDO_VRFIO18_RC1_OP_MODE_ADDR 0x1BD8 +#define MT6363_RG_LDO_VRFIO18_RC2_OP_MODE_ADDR 0x1BD8 +#define MT6363_RG_LDO_VRFIO18_RC3_OP_MODE_ADDR 0x1BD8 +#define MT6363_RG_LDO_VRFIO18_RC4_OP_MODE_ADDR 0x1BD8 +#define MT6363_RG_LDO_VRFIO18_RC5_OP_MODE_ADDR 0x1BD8 +#define MT6363_RG_LDO_VRFIO18_RC6_OP_MODE_ADDR 0x1BD8 +#define MT6363_RG_LDO_VRFIO18_RC7_OP_MODE_ADDR 0x1BD8 +#define MT6363_RG_LDO_VRFIO18_RC8_OP_MODE_ADDR 0x1BD9 +#define MT6363_RG_LDO_VRFIO18_RC9_OP_MODE_ADDR 0x1BD9 +#define MT6363_RG_LDO_VRFIO18_RC10_OP_MODE_ADDR 0x1BD9 +#define MT6363_RG_LDO_VRFIO18_RC11_OP_MODE_ADDR 0x1BD9 +#define MT6363_RG_LDO_VRFIO18_RC12_OP_MODE_ADDR 0x1BD9 +#define MT6363_RG_LDO_VRFIO18_RC13_OP_MODE_ADDR 0x1BD9 +#define MT6363_RG_LDO_VRFIO18_HW0_OP_MODE_ADDR 0x1BDA +#define MT6363_RG_LDO_VRFIO18_HW1_OP_MODE_ADDR 0x1BDA +#define MT6363_RG_LDO_VRFIO18_HW2_OP_MODE_ADDR 0x1BDA +#define MT6363_RG_LDO_VRFIO18_HW3_OP_MODE_ADDR 0x1BDA +#define MT6363_RG_LDO_VRFIO18_HW4_OP_MODE_ADDR 0x1BDA +#define MT6363_RG_LDO_VRFIO18_HW5_OP_MODE_ADDR 0x1BDA +#define MT6363_RG_LDO_VRFIO18_HW6_OP_MODE_ADDR 0x1BDA +#define MT6363_RG_LDO_VTREF18_ONLV_EN_ADDR 0x1C08 +#define MT6363_RG_LDO_VTREF18_ONLV_EN_SHIFT 3 +#define MT6363_RG_LDO_VTREF18_RC0_OP_EN_ADDR 0x1C0C +#define MT6363_RG_LDO_VTREF18_RC1_OP_EN_ADDR 0x1C0C +#define MT6363_RG_LDO_VTREF18_RC2_OP_EN_ADDR 0x1C0C +#define MT6363_RG_LDO_VTREF18_RC3_OP_EN_ADDR 0x1C0C +#define MT6363_RG_LDO_VTREF18_RC4_OP_EN_ADDR 0x1C0C +#define MT6363_RG_LDO_VTREF18_RC5_OP_EN_ADDR 0x1C0C +#define MT6363_RG_LDO_VTREF18_RC6_OP_EN_ADDR 0x1C0C +#define MT6363_RG_LDO_VTREF18_RC7_OP_EN_ADDR 0x1C0C +#define MT6363_RG_LDO_VTREF18_RC8_OP_EN_ADDR 0x1C0D +#define MT6363_RG_LDO_VTREF18_RC9_OP_EN_ADDR 0x1C0D +#define MT6363_RG_LDO_VTREF18_RC10_OP_EN_ADDR 0x1C0D +#define MT6363_RG_LDO_VTREF18_RC11_OP_EN_ADDR 0x1C0D +#define MT6363_RG_LDO_VTREF18_RC12_OP_EN_ADDR 0x1C0D +#define MT6363_RG_LDO_VTREF18_RC13_OP_EN_ADDR 0x1C0D +#define MT6363_RG_LDO_VTREF18_HW0_OP_EN_ADDR 0x1C0E +#define MT6363_RG_LDO_VTREF18_HW1_OP_EN_ADDR 0x1C0E +#define MT6363_RG_LDO_VTREF18_HW2_OP_EN_ADDR 0x1C0E +#define MT6363_RG_LDO_VTREF18_HW3_OP_EN_ADDR 0x1C0E +#define MT6363_RG_LDO_VTREF18_HW4_OP_EN_ADDR 0x1C0E +#define MT6363_RG_LDO_VTREF18_HW5_OP_EN_ADDR 0x1C0E +#define MT6363_RG_LDO_VTREF18_HW6_OP_EN_ADDR 0x1C0E +#define MT6363_RG_LDO_VTREF18_SW_OP_EN_ADDR 0x1C0E +#define MT6363_RG_LDO_VTREF18_RC0_OP_CFG_ADDR 0x1C0F +#define MT6363_RG_LDO_VTREF18_RC1_OP_CFG_ADDR 0x1C0F +#define MT6363_RG_LDO_VTREF18_RC2_OP_CFG_ADDR 0x1C0F +#define MT6363_RG_LDO_VTREF18_RC3_OP_CFG_ADDR 0x1C0F +#define MT6363_RG_LDO_VTREF18_RC4_OP_CFG_ADDR 0x1C0F +#define MT6363_RG_LDO_VTREF18_RC5_OP_CFG_ADDR 0x1C0F +#define MT6363_RG_LDO_VTREF18_RC6_OP_CFG_ADDR 0x1C0F +#define MT6363_RG_LDO_VTREF18_RC7_OP_CFG_ADDR 0x1C0F +#define MT6363_RG_LDO_VTREF18_RC8_OP_CFG_ADDR 0x1C10 +#define MT6363_RG_LDO_VTREF18_RC9_OP_CFG_ADDR 0x1C10 +#define MT6363_RG_LDO_VTREF18_RC10_OP_CFG_ADDR 0x1C10 +#define MT6363_RG_LDO_VTREF18_RC11_OP_CFG_ADDR 0x1C10 +#define MT6363_RG_LDO_VTREF18_RC12_OP_CFG_ADDR 0x1C10 +#define MT6363_RG_LDO_VTREF18_RC13_OP_CFG_ADDR 0x1C10 +#define MT6363_RG_LDO_VTREF18_HW0_OP_CFG_ADDR 0x1C11 +#define MT6363_RG_LDO_VTREF18_HW1_OP_CFG_ADDR 0x1C11 +#define MT6363_RG_LDO_VTREF18_HW2_OP_CFG_ADDR 0x1C11 +#define MT6363_RG_LDO_VTREF18_HW3_OP_CFG_ADDR 0x1C11 +#define MT6363_RG_LDO_VTREF18_HW4_OP_CFG_ADDR 0x1C11 +#define MT6363_RG_LDO_VTREF18_HW5_OP_CFG_ADDR 0x1C11 +#define MT6363_RG_LDO_VTREF18_HW6_OP_CFG_ADDR 0x1C11 +#define MT6363_RG_LDO_VTREF18_SW_OP_CFG_ADDR 0x1C11 +#define MT6363_RG_LDO_VTREF18_RC0_OP_MODE_ADDR 0x1C12 +#define MT6363_RG_LDO_VTREF18_RC1_OP_MODE_ADDR 0x1C12 +#define MT6363_RG_LDO_VTREF18_RC2_OP_MODE_ADDR 0x1C12 +#define MT6363_RG_LDO_VTREF18_RC3_OP_MODE_ADDR 0x1C12 +#define MT6363_RG_LDO_VTREF18_RC4_OP_MODE_ADDR 0x1C12 +#define MT6363_RG_LDO_VTREF18_RC5_OP_MODE_ADDR 0x1C12 +#define MT6363_RG_LDO_VTREF18_RC6_OP_MODE_ADDR 0x1C12 +#define MT6363_RG_LDO_VTREF18_RC7_OP_MODE_ADDR 0x1C12 +#define MT6363_RG_LDO_VTREF18_RC8_OP_MODE_ADDR 0x1C13 +#define MT6363_RG_LDO_VTREF18_RC9_OP_MODE_ADDR 0x1C13 +#define MT6363_RG_LDO_VTREF18_RC10_OP_MODE_ADDR 0x1C13 +#define MT6363_RG_LDO_VTREF18_RC11_OP_MODE_ADDR 0x1C13 +#define MT6363_RG_LDO_VTREF18_RC12_OP_MODE_ADDR 0x1C13 +#define MT6363_RG_LDO_VTREF18_RC13_OP_MODE_ADDR 0x1C13 +#define MT6363_RG_LDO_VTREF18_HW0_OP_MODE_ADDR 0x1C14 +#define MT6363_RG_LDO_VTREF18_HW1_OP_MODE_ADDR 0x1C14 +#define MT6363_RG_LDO_VTREF18_HW2_OP_MODE_ADDR 0x1C14 +#define MT6363_RG_LDO_VTREF18_HW3_OP_MODE_ADDR 0x1C14 +#define MT6363_RG_LDO_VTREF18_HW4_OP_MODE_ADDR 0x1C14 +#define MT6363_RG_LDO_VTREF18_HW5_OP_MODE_ADDR 0x1C14 +#define MT6363_RG_LDO_VTREF18_HW6_OP_MODE_ADDR 0x1C14 +#define MT6363_RG_LDO_VAUX18_ONLV_EN_ADDR 0x1C16 +#define MT6363_RG_LDO_VAUX18_ONLV_EN_SHIFT 3 +#define MT6363_RG_LDO_VAUX18_RC0_OP_EN_ADDR 0x1C1A +#define MT6363_RG_LDO_VAUX18_RC1_OP_EN_ADDR 0x1C1A +#define MT6363_RG_LDO_VAUX18_RC2_OP_EN_ADDR 0x1C1A +#define MT6363_RG_LDO_VAUX18_RC3_OP_EN_ADDR 0x1C1A +#define MT6363_RG_LDO_VAUX18_RC4_OP_EN_ADDR 0x1C1A +#define MT6363_RG_LDO_VAUX18_RC5_OP_EN_ADDR 0x1C1A +#define MT6363_RG_LDO_VAUX18_RC6_OP_EN_ADDR 0x1C1A +#define MT6363_RG_LDO_VAUX18_RC7_OP_EN_ADDR 0x1C1A +#define MT6363_RG_LDO_VAUX18_RC8_OP_EN_ADDR 0x1C1B +#define MT6363_RG_LDO_VAUX18_RC9_OP_EN_ADDR 0x1C1B +#define MT6363_RG_LDO_VAUX18_RC10_OP_EN_ADDR 0x1C1B +#define MT6363_RG_LDO_VAUX18_RC11_OP_EN_ADDR 0x1C1B +#define MT6363_RG_LDO_VAUX18_RC12_OP_EN_ADDR 0x1C1B +#define MT6363_RG_LDO_VAUX18_RC13_OP_EN_ADDR 0x1C1B +#define MT6363_RG_LDO_VAUX18_HW0_OP_EN_ADDR 0x1C1C +#define MT6363_RG_LDO_VAUX18_HW1_OP_EN_ADDR 0x1C1C +#define MT6363_RG_LDO_VAUX18_HW2_OP_EN_ADDR 0x1C1C +#define MT6363_RG_LDO_VAUX18_HW3_OP_EN_ADDR 0x1C1C +#define MT6363_RG_LDO_VAUX18_HW4_OP_EN_ADDR 0x1C1C +#define MT6363_RG_LDO_VAUX18_HW5_OP_EN_ADDR 0x1C1C +#define MT6363_RG_LDO_VAUX18_HW6_OP_EN_ADDR 0x1C1C +#define MT6363_RG_LDO_VAUX18_SW_OP_EN_ADDR 0x1C1C +#define MT6363_RG_LDO_VAUX18_RC0_OP_CFG_ADDR 0x1C1D +#define MT6363_RG_LDO_VAUX18_RC1_OP_CFG_ADDR 0x1C1D +#define MT6363_RG_LDO_VAUX18_RC2_OP_CFG_ADDR 0x1C1D +#define MT6363_RG_LDO_VAUX18_RC3_OP_CFG_ADDR 0x1C1D +#define MT6363_RG_LDO_VAUX18_RC4_OP_CFG_ADDR 0x1C1D +#define MT6363_RG_LDO_VAUX18_RC5_OP_CFG_ADDR 0x1C1D +#define MT6363_RG_LDO_VAUX18_RC6_OP_CFG_ADDR 0x1C1D +#define MT6363_RG_LDO_VAUX18_RC7_OP_CFG_ADDR 0x1C1D +#define MT6363_RG_LDO_VAUX18_RC8_OP_CFG_ADDR 0x1C1E +#define MT6363_RG_LDO_VAUX18_RC9_OP_CFG_ADDR 0x1C1E +#define MT6363_RG_LDO_VAUX18_RC10_OP_CFG_ADDR 0x1C1E +#define MT6363_RG_LDO_VAUX18_RC11_OP_CFG_ADDR 0x1C1E +#define MT6363_RG_LDO_VAUX18_RC12_OP_CFG_ADDR 0x1C1E +#define MT6363_RG_LDO_VAUX18_RC13_OP_CFG_ADDR 0x1C1E +#define MT6363_RG_LDO_VAUX18_HW0_OP_CFG_ADDR 0x1C1F +#define MT6363_RG_LDO_VAUX18_HW1_OP_CFG_ADDR 0x1C1F +#define MT6363_RG_LDO_VAUX18_HW2_OP_CFG_ADDR 0x1C1F +#define MT6363_RG_LDO_VAUX18_HW3_OP_CFG_ADDR 0x1C1F +#define MT6363_RG_LDO_VAUX18_HW4_OP_CFG_ADDR 0x1C1F +#define MT6363_RG_LDO_VAUX18_HW5_OP_CFG_ADDR 0x1C1F +#define MT6363_RG_LDO_VAUX18_HW6_OP_CFG_ADDR 0x1C1F +#define MT6363_RG_LDO_VAUX18_SW_OP_CFG_ADDR 0x1C1F +#define MT6363_RG_LDO_VAUX18_RC0_OP_MODE_ADDR 0x1C20 +#define MT6363_RG_LDO_VAUX18_RC1_OP_MODE_ADDR 0x1C20 +#define MT6363_RG_LDO_VAUX18_RC2_OP_MODE_ADDR 0x1C20 +#define MT6363_RG_LDO_VAUX18_RC3_OP_MODE_ADDR 0x1C20 +#define MT6363_RG_LDO_VAUX18_RC4_OP_MODE_ADDR 0x1C20 +#define MT6363_RG_LDO_VAUX18_RC5_OP_MODE_ADDR 0x1C20 +#define MT6363_RG_LDO_VAUX18_RC6_OP_MODE_ADDR 0x1C20 +#define MT6363_RG_LDO_VAUX18_RC7_OP_MODE_ADDR 0x1C20 +#define MT6363_RG_LDO_VAUX18_RC8_OP_MODE_ADDR 0x1C21 +#define MT6363_RG_LDO_VAUX18_RC9_OP_MODE_ADDR 0x1C21 +#define MT6363_RG_LDO_VAUX18_RC10_OP_MODE_ADDR 0x1C21 +#define MT6363_RG_LDO_VAUX18_RC11_OP_MODE_ADDR 0x1C21 +#define MT6363_RG_LDO_VAUX18_RC12_OP_MODE_ADDR 0x1C21 +#define MT6363_RG_LDO_VAUX18_RC13_OP_MODE_ADDR 0x1C21 +#define MT6363_RG_LDO_VAUX18_HW0_OP_MODE_ADDR 0x1C22 +#define MT6363_RG_LDO_VAUX18_HW1_OP_MODE_ADDR 0x1C22 +#define MT6363_RG_LDO_VAUX18_HW2_OP_MODE_ADDR 0x1C22 +#define MT6363_RG_LDO_VAUX18_HW3_OP_MODE_ADDR 0x1C22 +#define MT6363_RG_LDO_VAUX18_HW4_OP_MODE_ADDR 0x1C22 +#define MT6363_RG_LDO_VAUX18_HW5_OP_MODE_ADDR 0x1C22 +#define MT6363_RG_LDO_VAUX18_HW6_OP_MODE_ADDR 0x1C22 +#define MT6363_RG_LDO_VEMC_ONLV_EN_ADDR 0x1C24 +#define MT6363_RG_LDO_VEMC_ONLV_EN_SHIFT 3 +#define MT6363_RG_LDO_VEMC_RC0_OP_EN_ADDR 0x1C28 +#define MT6363_RG_LDO_VEMC_RC1_OP_EN_ADDR 0x1C28 +#define MT6363_RG_LDO_VEMC_RC2_OP_EN_ADDR 0x1C28 +#define MT6363_RG_LDO_VEMC_RC3_OP_EN_ADDR 0x1C28 +#define MT6363_RG_LDO_VEMC_RC4_OP_EN_ADDR 0x1C28 +#define MT6363_RG_LDO_VEMC_RC5_OP_EN_ADDR 0x1C28 +#define MT6363_RG_LDO_VEMC_RC6_OP_EN_ADDR 0x1C28 +#define MT6363_RG_LDO_VEMC_RC7_OP_EN_ADDR 0x1C28 +#define MT6363_RG_LDO_VEMC_RC8_OP_EN_ADDR 0x1C29 +#define MT6363_RG_LDO_VEMC_RC9_OP_EN_ADDR 0x1C29 +#define MT6363_RG_LDO_VEMC_RC10_OP_EN_ADDR 0x1C29 +#define MT6363_RG_LDO_VEMC_RC11_OP_EN_ADDR 0x1C29 +#define MT6363_RG_LDO_VEMC_RC12_OP_EN_ADDR 0x1C29 +#define MT6363_RG_LDO_VEMC_RC13_OP_EN_ADDR 0x1C29 +#define MT6363_RG_LDO_VEMC_HW0_OP_EN_ADDR 0x1C2A +#define MT6363_RG_LDO_VEMC_HW1_OP_EN_ADDR 0x1C2A +#define MT6363_RG_LDO_VEMC_HW2_OP_EN_ADDR 0x1C2A +#define MT6363_RG_LDO_VEMC_HW3_OP_EN_ADDR 0x1C2A +#define MT6363_RG_LDO_VEMC_HW4_OP_EN_ADDR 0x1C2A +#define MT6363_RG_LDO_VEMC_HW5_OP_EN_ADDR 0x1C2A +#define MT6363_RG_LDO_VEMC_HW6_OP_EN_ADDR 0x1C2A +#define MT6363_RG_LDO_VEMC_SW_OP_EN_ADDR 0x1C2A +#define MT6363_RG_LDO_VEMC_RC0_OP_CFG_ADDR 0x1C2B +#define MT6363_RG_LDO_VEMC_RC1_OP_CFG_ADDR 0x1C2B +#define MT6363_RG_LDO_VEMC_RC2_OP_CFG_ADDR 0x1C2B +#define MT6363_RG_LDO_VEMC_RC3_OP_CFG_ADDR 0x1C2B +#define MT6363_RG_LDO_VEMC_RC4_OP_CFG_ADDR 0x1C2B +#define MT6363_RG_LDO_VEMC_RC5_OP_CFG_ADDR 0x1C2B +#define MT6363_RG_LDO_VEMC_RC6_OP_CFG_ADDR 0x1C2B +#define MT6363_RG_LDO_VEMC_RC7_OP_CFG_ADDR 0x1C2B +#define MT6363_RG_LDO_VEMC_RC8_OP_CFG_ADDR 0x1C2C +#define MT6363_RG_LDO_VEMC_RC9_OP_CFG_ADDR 0x1C2C +#define MT6363_RG_LDO_VEMC_RC10_OP_CFG_ADDR 0x1C2C +#define MT6363_RG_LDO_VEMC_RC11_OP_CFG_ADDR 0x1C2C +#define MT6363_RG_LDO_VEMC_RC12_OP_CFG_ADDR 0x1C2C +#define MT6363_RG_LDO_VEMC_RC13_OP_CFG_ADDR 0x1C2C +#define MT6363_RG_LDO_VEMC_HW0_OP_CFG_ADDR 0x1C2D +#define MT6363_RG_LDO_VEMC_HW1_OP_CFG_ADDR 0x1C2D +#define MT6363_RG_LDO_VEMC_HW2_OP_CFG_ADDR 0x1C2D +#define MT6363_RG_LDO_VEMC_HW3_OP_CFG_ADDR 0x1C2D +#define MT6363_RG_LDO_VEMC_HW4_OP_CFG_ADDR 0x1C2D +#define MT6363_RG_LDO_VEMC_HW5_OP_CFG_ADDR 0x1C2D +#define MT6363_RG_LDO_VEMC_HW6_OP_CFG_ADDR 0x1C2D +#define MT6363_RG_LDO_VEMC_SW_OP_CFG_ADDR 0x1C2D +#define MT6363_RG_LDO_VEMC_RC0_OP_MODE_ADDR 0x1C2E +#define MT6363_RG_LDO_VEMC_RC1_OP_MODE_ADDR 0x1C2E +#define MT6363_RG_LDO_VEMC_RC2_OP_MODE_ADDR 0x1C2E +#define MT6363_RG_LDO_VEMC_RC3_OP_MODE_ADDR 0x1C2E +#define MT6363_RG_LDO_VEMC_RC4_OP_MODE_ADDR 0x1C2E +#define MT6363_RG_LDO_VEMC_RC5_OP_MODE_ADDR 0x1C2E +#define MT6363_RG_LDO_VEMC_RC6_OP_MODE_ADDR 0x1C2E +#define MT6363_RG_LDO_VEMC_RC7_OP_MODE_ADDR 0x1C2E +#define MT6363_RG_LDO_VEMC_RC8_OP_MODE_ADDR 0x1C2F +#define MT6363_RG_LDO_VEMC_RC9_OP_MODE_ADDR 0x1C2F +#define MT6363_RG_LDO_VEMC_RC10_OP_MODE_ADDR 0x1C2F +#define MT6363_RG_LDO_VEMC_RC11_OP_MODE_ADDR 0x1C2F +#define MT6363_RG_LDO_VEMC_RC12_OP_MODE_ADDR 0x1C2F +#define MT6363_RG_LDO_VEMC_RC13_OP_MODE_ADDR 0x1C2F +#define MT6363_RG_LDO_VEMC_HW0_OP_MODE_ADDR 0x1C30 +#define MT6363_RG_LDO_VEMC_HW1_OP_MODE_ADDR 0x1C30 +#define MT6363_RG_LDO_VEMC_HW2_OP_MODE_ADDR 0x1C30 +#define MT6363_RG_LDO_VEMC_HW3_OP_MODE_ADDR 0x1C30 +#define MT6363_RG_LDO_VEMC_HW4_OP_MODE_ADDR 0x1C30 +#define MT6363_RG_LDO_VEMC_HW5_OP_MODE_ADDR 0x1C30 +#define MT6363_RG_LDO_VEMC_HW6_OP_MODE_ADDR 0x1C30 +#define MT6363_RG_LDO_VUFS12_ONLV_EN_ADDR 0x1C32 +#define MT6363_RG_LDO_VUFS12_ONLV_EN_SHIFT 3 +#define MT6363_RG_LDO_VUFS12_RC0_OP_EN_ADDR 0x1C36 +#define MT6363_RG_LDO_VUFS12_RC1_OP_EN_ADDR 0x1C36 +#define MT6363_RG_LDO_VUFS12_RC2_OP_EN_ADDR 0x1C36 +#define MT6363_RG_LDO_VUFS12_RC3_OP_EN_ADDR 0x1C36 +#define MT6363_RG_LDO_VUFS12_RC4_OP_EN_ADDR 0x1C36 +#define MT6363_RG_LDO_VUFS12_RC5_OP_EN_ADDR 0x1C36 +#define MT6363_RG_LDO_VUFS12_RC6_OP_EN_ADDR 0x1C36 +#define MT6363_RG_LDO_VUFS12_RC7_OP_EN_ADDR 0x1C36 +#define MT6363_RG_LDO_VUFS12_RC8_OP_EN_ADDR 0x1C37 +#define MT6363_RG_LDO_VUFS12_RC9_OP_EN_ADDR 0x1C37 +#define MT6363_RG_LDO_VUFS12_RC10_OP_EN_ADDR 0x1C37 +#define MT6363_RG_LDO_VUFS12_RC11_OP_EN_ADDR 0x1C37 +#define MT6363_RG_LDO_VUFS12_RC12_OP_EN_ADDR 0x1C37 +#define MT6363_RG_LDO_VUFS12_RC13_OP_EN_ADDR 0x1C37 +#define MT6363_RG_LDO_VUFS12_HW0_OP_EN_ADDR 0x1C38 +#define MT6363_RG_LDO_VUFS12_HW1_OP_EN_ADDR 0x1C38 +#define MT6363_RG_LDO_VUFS12_HW2_OP_EN_ADDR 0x1C38 +#define MT6363_RG_LDO_VUFS12_HW3_OP_EN_ADDR 0x1C38 +#define MT6363_RG_LDO_VUFS12_HW4_OP_EN_ADDR 0x1C38 +#define MT6363_RG_LDO_VUFS12_HW5_OP_EN_ADDR 0x1C38 +#define MT6363_RG_LDO_VUFS12_HW6_OP_EN_ADDR 0x1C38 +#define MT6363_RG_LDO_VUFS12_SW_OP_EN_ADDR 0x1C38 +#define MT6363_RG_LDO_VUFS12_RC0_OP_CFG_ADDR 0x1C39 +#define MT6363_RG_LDO_VUFS12_RC1_OP_CFG_ADDR 0x1C39 +#define MT6363_RG_LDO_VUFS12_RC2_OP_CFG_ADDR 0x1C39 +#define MT6363_RG_LDO_VUFS12_RC3_OP_CFG_ADDR 0x1C39 +#define MT6363_RG_LDO_VUFS12_RC4_OP_CFG_ADDR 0x1C39 +#define MT6363_RG_LDO_VUFS12_RC5_OP_CFG_ADDR 0x1C39 +#define MT6363_RG_LDO_VUFS12_RC6_OP_CFG_ADDR 0x1C39 +#define MT6363_RG_LDO_VUFS12_RC7_OP_CFG_ADDR 0x1C39 +#define MT6363_RG_LDO_VUFS12_RC8_OP_CFG_ADDR 0x1C3A +#define MT6363_RG_LDO_VUFS12_RC9_OP_CFG_ADDR 0x1C3A +#define MT6363_RG_LDO_VUFS12_RC10_OP_CFG_ADDR 0x1C3A +#define MT6363_RG_LDO_VUFS12_RC11_OP_CFG_ADDR 0x1C3A +#define MT6363_RG_LDO_VUFS12_RC12_OP_CFG_ADDR 0x1C3A +#define MT6363_RG_LDO_VUFS12_RC13_OP_CFG_ADDR 0x1C3A +#define MT6363_RG_LDO_VUFS12_HW0_OP_CFG_ADDR 0x1C3B +#define MT6363_RG_LDO_VUFS12_HW1_OP_CFG_ADDR 0x1C3B +#define MT6363_RG_LDO_VUFS12_HW2_OP_CFG_ADDR 0x1C3B +#define MT6363_RG_LDO_VUFS12_HW3_OP_CFG_ADDR 0x1C3B +#define MT6363_RG_LDO_VUFS12_HW4_OP_CFG_ADDR 0x1C3B +#define MT6363_RG_LDO_VUFS12_HW5_OP_CFG_ADDR 0x1C3B +#define MT6363_RG_LDO_VUFS12_HW6_OP_CFG_ADDR 0x1C3B +#define MT6363_RG_LDO_VUFS12_SW_OP_CFG_ADDR 0x1C3B +#define MT6363_RG_LDO_VUFS12_RC0_OP_MODE_ADDR 0x1C3C +#define MT6363_RG_LDO_VUFS12_RC1_OP_MODE_ADDR 0x1C3C +#define MT6363_RG_LDO_VUFS12_RC2_OP_MODE_ADDR 0x1C3C +#define MT6363_RG_LDO_VUFS12_RC3_OP_MODE_ADDR 0x1C3C +#define MT6363_RG_LDO_VUFS12_RC4_OP_MODE_ADDR 0x1C3C +#define MT6363_RG_LDO_VUFS12_RC5_OP_MODE_ADDR 0x1C3C +#define MT6363_RG_LDO_VUFS12_RC6_OP_MODE_ADDR 0x1C3C +#define MT6363_RG_LDO_VUFS12_RC7_OP_MODE_ADDR 0x1C3C +#define MT6363_RG_LDO_VUFS12_RC8_OP_MODE_ADDR 0x1C3D +#define MT6363_RG_LDO_VUFS12_RC9_OP_MODE_ADDR 0x1C3D +#define MT6363_RG_LDO_VUFS12_RC10_OP_MODE_ADDR 0x1C3D +#define MT6363_RG_LDO_VUFS12_RC11_OP_MODE_ADDR 0x1C3D +#define MT6363_RG_LDO_VUFS12_RC12_OP_MODE_ADDR 0x1C3D +#define MT6363_RG_LDO_VUFS12_RC13_OP_MODE_ADDR 0x1C3D +#define MT6363_RG_LDO_VUFS12_HW0_OP_MODE_ADDR 0x1C3E +#define MT6363_RG_LDO_VUFS12_HW1_OP_MODE_ADDR 0x1C3E +#define MT6363_RG_LDO_VUFS12_HW2_OP_MODE_ADDR 0x1C3E +#define MT6363_RG_LDO_VUFS12_HW3_OP_MODE_ADDR 0x1C3E +#define MT6363_RG_LDO_VUFS12_HW4_OP_MODE_ADDR 0x1C3E +#define MT6363_RG_LDO_VUFS12_HW5_OP_MODE_ADDR 0x1C3E +#define MT6363_RG_LDO_VUFS12_HW6_OP_MODE_ADDR 0x1C3E +#define MT6363_RG_LDO_VUFS18_ONLV_EN_ADDR 0x1C40 +#define MT6363_RG_LDO_VUFS18_ONLV_EN_SHIFT 3 +#define MT6363_RG_LDO_VUFS18_RC0_OP_EN_ADDR 0x1C44 +#define MT6363_RG_LDO_VUFS18_RC1_OP_EN_ADDR 0x1C44 +#define MT6363_RG_LDO_VUFS18_RC2_OP_EN_ADDR 0x1C44 +#define MT6363_RG_LDO_VUFS18_RC3_OP_EN_ADDR 0x1C44 +#define MT6363_RG_LDO_VUFS18_RC4_OP_EN_ADDR 0x1C44 +#define MT6363_RG_LDO_VUFS18_RC5_OP_EN_ADDR 0x1C44 +#define MT6363_RG_LDO_VUFS18_RC6_OP_EN_ADDR 0x1C44 +#define MT6363_RG_LDO_VUFS18_RC7_OP_EN_ADDR 0x1C44 +#define MT6363_RG_LDO_VUFS18_RC8_OP_EN_ADDR 0x1C45 +#define MT6363_RG_LDO_VUFS18_RC9_OP_EN_ADDR 0x1C45 +#define MT6363_RG_LDO_VUFS18_RC10_OP_EN_ADDR 0x1C45 +#define MT6363_RG_LDO_VUFS18_RC11_OP_EN_ADDR 0x1C45 +#define MT6363_RG_LDO_VUFS18_RC12_OP_EN_ADDR 0x1C45 +#define MT6363_RG_LDO_VUFS18_RC13_OP_EN_ADDR 0x1C45 +#define MT6363_RG_LDO_VUFS18_HW0_OP_EN_ADDR 0x1C46 +#define MT6363_RG_LDO_VUFS18_HW1_OP_EN_ADDR 0x1C46 +#define MT6363_RG_LDO_VUFS18_HW2_OP_EN_ADDR 0x1C46 +#define MT6363_RG_LDO_VUFS18_HW3_OP_EN_ADDR 0x1C46 +#define MT6363_RG_LDO_VUFS18_HW4_OP_EN_ADDR 0x1C46 +#define MT6363_RG_LDO_VUFS18_HW5_OP_EN_ADDR 0x1C46 +#define MT6363_RG_LDO_VUFS18_HW6_OP_EN_ADDR 0x1C46 +#define MT6363_RG_LDO_VUFS18_SW_OP_EN_ADDR 0x1C46 +#define MT6363_RG_LDO_VUFS18_RC0_OP_CFG_ADDR 0x1C47 +#define MT6363_RG_LDO_VUFS18_RC1_OP_CFG_ADDR 0x1C47 +#define MT6363_RG_LDO_VUFS18_RC2_OP_CFG_ADDR 0x1C47 +#define MT6363_RG_LDO_VUFS18_RC3_OP_CFG_ADDR 0x1C47 +#define MT6363_RG_LDO_VUFS18_RC4_OP_CFG_ADDR 0x1C47 +#define MT6363_RG_LDO_VUFS18_RC5_OP_CFG_ADDR 0x1C47 +#define MT6363_RG_LDO_VUFS18_RC6_OP_CFG_ADDR 0x1C47 +#define MT6363_RG_LDO_VUFS18_RC7_OP_CFG_ADDR 0x1C47 +#define MT6363_RG_LDO_VUFS18_RC8_OP_CFG_ADDR 0x1C48 +#define MT6363_RG_LDO_VUFS18_RC9_OP_CFG_ADDR 0x1C48 +#define MT6363_RG_LDO_VUFS18_RC10_OP_CFG_ADDR 0x1C48 +#define MT6363_RG_LDO_VUFS18_RC11_OP_CFG_ADDR 0x1C48 +#define MT6363_RG_LDO_VUFS18_RC12_OP_CFG_ADDR 0x1C48 +#define MT6363_RG_LDO_VUFS18_RC13_OP_CFG_ADDR 0x1C48 +#define MT6363_RG_LDO_VUFS18_HW0_OP_CFG_ADDR 0x1C49 +#define MT6363_RG_LDO_VUFS18_HW1_OP_CFG_ADDR 0x1C49 +#define MT6363_RG_LDO_VUFS18_HW2_OP_CFG_ADDR 0x1C49 +#define MT6363_RG_LDO_VUFS18_HW3_OP_CFG_ADDR 0x1C49 +#define MT6363_RG_LDO_VUFS18_HW4_OP_CFG_ADDR 0x1C49 +#define MT6363_RG_LDO_VUFS18_HW5_OP_CFG_ADDR 0x1C49 +#define MT6363_RG_LDO_VUFS18_HW6_OP_CFG_ADDR 0x1C49 +#define MT6363_RG_LDO_VUFS18_SW_OP_CFG_ADDR 0x1C49 +#define MT6363_RG_LDO_VUFS18_RC0_OP_MODE_ADDR 0x1C4A +#define MT6363_RG_LDO_VUFS18_RC1_OP_MODE_ADDR 0x1C4A +#define MT6363_RG_LDO_VUFS18_RC2_OP_MODE_ADDR 0x1C4A +#define MT6363_RG_LDO_VUFS18_RC3_OP_MODE_ADDR 0x1C4A +#define MT6363_RG_LDO_VUFS18_RC4_OP_MODE_ADDR 0x1C4A +#define MT6363_RG_LDO_VUFS18_RC5_OP_MODE_ADDR 0x1C4A +#define MT6363_RG_LDO_VUFS18_RC6_OP_MODE_ADDR 0x1C4A +#define MT6363_RG_LDO_VUFS18_RC7_OP_MODE_ADDR 0x1C4A +#define MT6363_RG_LDO_VUFS18_RC8_OP_MODE_ADDR 0x1C4B +#define MT6363_RG_LDO_VUFS18_RC9_OP_MODE_ADDR 0x1C4B +#define MT6363_RG_LDO_VUFS18_RC10_OP_MODE_ADDR 0x1C4B +#define MT6363_RG_LDO_VUFS18_RC11_OP_MODE_ADDR 0x1C4B +#define MT6363_RG_LDO_VUFS18_RC12_OP_MODE_ADDR 0x1C4B +#define MT6363_RG_LDO_VUFS18_RC13_OP_MODE_ADDR 0x1C4B +#define MT6363_RG_LDO_VUFS18_HW0_OP_MODE_ADDR 0x1C4C +#define MT6363_RG_LDO_VUFS18_HW1_OP_MODE_ADDR 0x1C4C +#define MT6363_RG_LDO_VUFS18_HW2_OP_MODE_ADDR 0x1C4C +#define MT6363_RG_LDO_VUFS18_HW3_OP_MODE_ADDR 0x1C4C +#define MT6363_RG_LDO_VUFS18_HW4_OP_MODE_ADDR 0x1C4C +#define MT6363_RG_LDO_VUFS18_HW5_OP_MODE_ADDR 0x1C4C +#define MT6363_RG_LDO_VUFS18_HW6_OP_MODE_ADDR 0x1C4C +#define MT6363_RG_LDO_VIO18_ONLV_EN_ADDR 0x1C4E +#define MT6363_RG_LDO_VIO18_ONLV_EN_SHIFT 3 +#define MT6363_RG_LDO_VIO18_RC0_OP_EN_ADDR 0x1C52 +#define MT6363_RG_LDO_VIO18_RC1_OP_EN_ADDR 0x1C52 +#define MT6363_RG_LDO_VIO18_RC2_OP_EN_ADDR 0x1C52 +#define MT6363_RG_LDO_VIO18_RC3_OP_EN_ADDR 0x1C52 +#define MT6363_RG_LDO_VIO18_RC4_OP_EN_ADDR 0x1C52 +#define MT6363_RG_LDO_VIO18_RC5_OP_EN_ADDR 0x1C52 +#define MT6363_RG_LDO_VIO18_RC6_OP_EN_ADDR 0x1C52 +#define MT6363_RG_LDO_VIO18_RC7_OP_EN_ADDR 0x1C52 +#define MT6363_RG_LDO_VIO18_RC8_OP_EN_ADDR 0x1C53 +#define MT6363_RG_LDO_VIO18_RC9_OP_EN_ADDR 0x1C53 +#define MT6363_RG_LDO_VIO18_RC10_OP_EN_ADDR 0x1C53 +#define MT6363_RG_LDO_VIO18_RC11_OP_EN_ADDR 0x1C53 +#define MT6363_RG_LDO_VIO18_RC12_OP_EN_ADDR 0x1C53 +#define MT6363_RG_LDO_VIO18_RC13_OP_EN_ADDR 0x1C53 +#define MT6363_RG_LDO_VIO18_HW0_OP_EN_ADDR 0x1C54 +#define MT6363_RG_LDO_VIO18_HW1_OP_EN_ADDR 0x1C54 +#define MT6363_RG_LDO_VIO18_HW2_OP_EN_ADDR 0x1C54 +#define MT6363_RG_LDO_VIO18_HW3_OP_EN_ADDR 0x1C54 +#define MT6363_RG_LDO_VIO18_HW4_OP_EN_ADDR 0x1C54 +#define MT6363_RG_LDO_VIO18_HW5_OP_EN_ADDR 0x1C54 +#define MT6363_RG_LDO_VIO18_HW6_OP_EN_ADDR 0x1C54 +#define MT6363_RG_LDO_VIO18_SW_OP_EN_ADDR 0x1C54 +#define MT6363_RG_LDO_VIO18_RC0_OP_CFG_ADDR 0x1C55 +#define MT6363_RG_LDO_VIO18_RC1_OP_CFG_ADDR 0x1C55 +#define MT6363_RG_LDO_VIO18_RC2_OP_CFG_ADDR 0x1C55 +#define MT6363_RG_LDO_VIO18_RC3_OP_CFG_ADDR 0x1C55 +#define MT6363_RG_LDO_VIO18_RC4_OP_CFG_ADDR 0x1C55 +#define MT6363_RG_LDO_VIO18_RC5_OP_CFG_ADDR 0x1C55 +#define MT6363_RG_LDO_VIO18_RC6_OP_CFG_ADDR 0x1C55 +#define MT6363_RG_LDO_VIO18_RC7_OP_CFG_ADDR 0x1C55 +#define MT6363_RG_LDO_VIO18_RC8_OP_CFG_ADDR 0x1C56 +#define MT6363_RG_LDO_VIO18_RC9_OP_CFG_ADDR 0x1C56 +#define MT6363_RG_LDO_VIO18_RC10_OP_CFG_ADDR 0x1C56 +#define MT6363_RG_LDO_VIO18_RC11_OP_CFG_ADDR 0x1C56 +#define MT6363_RG_LDO_VIO18_RC12_OP_CFG_ADDR 0x1C56 +#define MT6363_RG_LDO_VIO18_RC13_OP_CFG_ADDR 0x1C56 +#define MT6363_RG_LDO_VIO18_HW0_OP_CFG_ADDR 0x1C57 +#define MT6363_RG_LDO_VIO18_HW1_OP_CFG_ADDR 0x1C57 +#define MT6363_RG_LDO_VIO18_HW2_OP_CFG_ADDR 0x1C57 +#define MT6363_RG_LDO_VIO18_HW3_OP_CFG_ADDR 0x1C57 +#define MT6363_RG_LDO_VIO18_HW4_OP_CFG_ADDR 0x1C57 +#define MT6363_RG_LDO_VIO18_HW5_OP_CFG_ADDR 0x1C57 +#define MT6363_RG_LDO_VIO18_HW6_OP_CFG_ADDR 0x1C57 +#define MT6363_RG_LDO_VIO18_SW_OP_CFG_ADDR 0x1C57 +#define MT6363_RG_LDO_VIO18_RC0_OP_MODE_ADDR 0x1C58 +#define MT6363_RG_LDO_VIO18_RC1_OP_MODE_ADDR 0x1C58 +#define MT6363_RG_LDO_VIO18_RC2_OP_MODE_ADDR 0x1C58 +#define MT6363_RG_LDO_VIO18_RC3_OP_MODE_ADDR 0x1C58 +#define MT6363_RG_LDO_VIO18_RC4_OP_MODE_ADDR 0x1C58 +#define MT6363_RG_LDO_VIO18_RC5_OP_MODE_ADDR 0x1C58 +#define MT6363_RG_LDO_VIO18_RC6_OP_MODE_ADDR 0x1C58 +#define MT6363_RG_LDO_VIO18_RC7_OP_MODE_ADDR 0x1C58 +#define MT6363_RG_LDO_VIO18_RC8_OP_MODE_ADDR 0x1C59 +#define MT6363_RG_LDO_VIO18_RC9_OP_MODE_ADDR 0x1C59 +#define MT6363_RG_LDO_VIO18_RC10_OP_MODE_ADDR 0x1C59 +#define MT6363_RG_LDO_VIO18_RC11_OP_MODE_ADDR 0x1C59 +#define MT6363_RG_LDO_VIO18_RC12_OP_MODE_ADDR 0x1C59 +#define MT6363_RG_LDO_VIO18_RC13_OP_MODE_ADDR 0x1C59 +#define MT6363_RG_LDO_VIO18_HW0_OP_MODE_ADDR 0x1C5A +#define MT6363_RG_LDO_VIO18_HW1_OP_MODE_ADDR 0x1C5A +#define MT6363_RG_LDO_VIO18_HW2_OP_MODE_ADDR 0x1C5A +#define MT6363_RG_LDO_VIO18_HW3_OP_MODE_ADDR 0x1C5A +#define MT6363_RG_LDO_VIO18_HW4_OP_MODE_ADDR 0x1C5A +#define MT6363_RG_LDO_VIO18_HW5_OP_MODE_ADDR 0x1C5A +#define MT6363_RG_LDO_VIO18_HW6_OP_MODE_ADDR 0x1C5A +#define MT6363_RG_LDO_VIO075_ONLV_EN_ADDR 0x1C88 +#define MT6363_RG_LDO_VIO075_ONLV_EN_SHIFT 3 +#define MT6363_RG_LDO_VIO075_RC0_OP_EN_ADDR 0x1C8C +#define MT6363_RG_LDO_VIO075_RC1_OP_EN_ADDR 0x1C8C +#define MT6363_RG_LDO_VIO075_RC2_OP_EN_ADDR 0x1C8C +#define MT6363_RG_LDO_VIO075_RC3_OP_EN_ADDR 0x1C8C +#define MT6363_RG_LDO_VIO075_RC4_OP_EN_ADDR 0x1C8C +#define MT6363_RG_LDO_VIO075_RC5_OP_EN_ADDR 0x1C8C +#define MT6363_RG_LDO_VIO075_RC6_OP_EN_ADDR 0x1C8C +#define MT6363_RG_LDO_VIO075_RC7_OP_EN_ADDR 0x1C8C +#define MT6363_RG_LDO_VIO075_RC8_OP_EN_ADDR 0x1C8D +#define MT6363_RG_LDO_VIO075_RC9_OP_EN_ADDR 0x1C8D +#define MT6363_RG_LDO_VIO075_RC10_OP_EN_ADDR 0x1C8D +#define MT6363_RG_LDO_VIO075_RC11_OP_EN_ADDR 0x1C8D +#define MT6363_RG_LDO_VIO075_RC12_OP_EN_ADDR 0x1C8D +#define MT6363_RG_LDO_VIO075_RC13_OP_EN_ADDR 0x1C8D +#define MT6363_RG_LDO_VIO075_HW0_OP_EN_ADDR 0x1C8E +#define MT6363_RG_LDO_VIO075_HW1_OP_EN_ADDR 0x1C8E +#define MT6363_RG_LDO_VIO075_HW2_OP_EN_ADDR 0x1C8E +#define MT6363_RG_LDO_VIO075_HW3_OP_EN_ADDR 0x1C8E +#define MT6363_RG_LDO_VIO075_HW4_OP_EN_ADDR 0x1C8E +#define MT6363_RG_LDO_VIO075_HW5_OP_EN_ADDR 0x1C8E +#define MT6363_RG_LDO_VIO075_HW6_OP_EN_ADDR 0x1C8E +#define MT6363_RG_LDO_VIO075_SW_OP_EN_ADDR 0x1C8E +#define MT6363_RG_LDO_VIO075_RC0_OP_CFG_ADDR 0x1C8F +#define MT6363_RG_LDO_VIO075_RC1_OP_CFG_ADDR 0x1C8F +#define MT6363_RG_LDO_VIO075_RC2_OP_CFG_ADDR 0x1C8F +#define MT6363_RG_LDO_VIO075_RC3_OP_CFG_ADDR 0x1C8F +#define MT6363_RG_LDO_VIO075_RC4_OP_CFG_ADDR 0x1C8F +#define MT6363_RG_LDO_VIO075_RC5_OP_CFG_ADDR 0x1C8F +#define MT6363_RG_LDO_VIO075_RC6_OP_CFG_ADDR 0x1C8F +#define MT6363_RG_LDO_VIO075_RC7_OP_CFG_ADDR 0x1C8F +#define MT6363_RG_LDO_VIO075_RC8_OP_CFG_ADDR 0x1C90 +#define MT6363_RG_LDO_VIO075_RC9_OP_CFG_ADDR 0x1C90 +#define MT6363_RG_LDO_VIO075_RC10_OP_CFG_ADDR 0x1C90 +#define MT6363_RG_LDO_VIO075_RC11_OP_CFG_ADDR 0x1C90 +#define MT6363_RG_LDO_VIO075_RC12_OP_CFG_ADDR 0x1C90 +#define MT6363_RG_LDO_VIO075_RC13_OP_CFG_ADDR 0x1C90 +#define MT6363_RG_LDO_VIO075_HW0_OP_CFG_ADDR 0x1C91 +#define MT6363_RG_LDO_VIO075_HW1_OP_CFG_ADDR 0x1C91 +#define MT6363_RG_LDO_VIO075_HW2_OP_CFG_ADDR 0x1C91 +#define MT6363_RG_LDO_VIO075_HW3_OP_CFG_ADDR 0x1C91 +#define MT6363_RG_LDO_VIO075_HW4_OP_CFG_ADDR 0x1C91 +#define MT6363_RG_LDO_VIO075_HW5_OP_CFG_ADDR 0x1C91 +#define MT6363_RG_LDO_VIO075_HW6_OP_CFG_ADDR 0x1C91 +#define MT6363_RG_LDO_VIO075_SW_OP_CFG_ADDR 0x1C91 +#define MT6363_RG_LDO_VIO075_RC0_OP_MODE_ADDR 0x1C92 +#define MT6363_RG_LDO_VIO075_RC1_OP_MODE_ADDR 0x1C92 +#define MT6363_RG_LDO_VIO075_RC2_OP_MODE_ADDR 0x1C92 +#define MT6363_RG_LDO_VIO075_RC3_OP_MODE_ADDR 0x1C92 +#define MT6363_RG_LDO_VIO075_RC4_OP_MODE_ADDR 0x1C92 +#define MT6363_RG_LDO_VIO075_RC5_OP_MODE_ADDR 0x1C92 +#define MT6363_RG_LDO_VIO075_RC6_OP_MODE_ADDR 0x1C92 +#define MT6363_RG_LDO_VIO075_RC7_OP_MODE_ADDR 0x1C92 +#define MT6363_RG_LDO_VIO075_RC8_OP_MODE_ADDR 0x1C93 +#define MT6363_RG_LDO_VIO075_RC9_OP_MODE_ADDR 0x1C93 +#define MT6363_RG_LDO_VIO075_RC10_OP_MODE_ADDR 0x1C93 +#define MT6363_RG_LDO_VIO075_RC11_OP_MODE_ADDR 0x1C93 +#define MT6363_RG_LDO_VIO075_RC12_OP_MODE_ADDR 0x1C93 +#define MT6363_RG_LDO_VIO075_RC13_OP_MODE_ADDR 0x1C93 +#define MT6363_RG_LDO_VIO075_HW0_OP_MODE_ADDR 0x1C94 +#define MT6363_RG_LDO_VIO075_HW1_OP_MODE_ADDR 0x1C94 +#define MT6363_RG_LDO_VIO075_HW2_OP_MODE_ADDR 0x1C94 +#define MT6363_RG_LDO_VIO075_HW3_OP_MODE_ADDR 0x1C94 +#define MT6363_RG_LDO_VIO075_HW4_OP_MODE_ADDR 0x1C94 +#define MT6363_RG_LDO_VIO075_HW5_OP_MODE_ADDR 0x1C94 +#define MT6363_RG_LDO_VIO075_HW6_OP_MODE_ADDR 0x1C94 +#define MT6363_RG_LDO_VA12_1_ONLV_EN_ADDR 0x1C96 +#define MT6363_RG_LDO_VA12_1_ONLV_EN_SHIFT 3 +#define MT6363_RG_LDO_VA12_1_RC0_OP_EN_ADDR 0x1C9A +#define MT6363_RG_LDO_VA12_1_RC1_OP_EN_ADDR 0x1C9A +#define MT6363_RG_LDO_VA12_1_RC2_OP_EN_ADDR 0x1C9A +#define MT6363_RG_LDO_VA12_1_RC3_OP_EN_ADDR 0x1C9A +#define MT6363_RG_LDO_VA12_1_RC4_OP_EN_ADDR 0x1C9A +#define MT6363_RG_LDO_VA12_1_RC5_OP_EN_ADDR 0x1C9A +#define MT6363_RG_LDO_VA12_1_RC6_OP_EN_ADDR 0x1C9A +#define MT6363_RG_LDO_VA12_1_RC7_OP_EN_ADDR 0x1C9A +#define MT6363_RG_LDO_VA12_1_RC8_OP_EN_ADDR 0x1C9B +#define MT6363_RG_LDO_VA12_1_RC9_OP_EN_ADDR 0x1C9B +#define MT6363_RG_LDO_VA12_1_RC10_OP_EN_ADDR 0x1C9B +#define MT6363_RG_LDO_VA12_1_RC11_OP_EN_ADDR 0x1C9B +#define MT6363_RG_LDO_VA12_1_RC12_OP_EN_ADDR 0x1C9B +#define MT6363_RG_LDO_VA12_1_RC13_OP_EN_ADDR 0x1C9B +#define MT6363_RG_LDO_VA12_1_HW0_OP_EN_ADDR 0x1C9C +#define MT6363_RG_LDO_VA12_1_HW1_OP_EN_ADDR 0x1C9C +#define MT6363_RG_LDO_VA12_1_HW2_OP_EN_ADDR 0x1C9C +#define MT6363_RG_LDO_VA12_1_HW3_OP_EN_ADDR 0x1C9C +#define MT6363_RG_LDO_VA12_1_HW4_OP_EN_ADDR 0x1C9C +#define MT6363_RG_LDO_VA12_1_HW5_OP_EN_ADDR 0x1C9C +#define MT6363_RG_LDO_VA12_1_HW6_OP_EN_ADDR 0x1C9C +#define MT6363_RG_LDO_VA12_1_SW_OP_EN_ADDR 0x1C9C +#define MT6363_RG_LDO_VA12_1_RC0_OP_CFG_ADDR 0x1C9D +#define MT6363_RG_LDO_VA12_1_RC1_OP_CFG_ADDR 0x1C9D +#define MT6363_RG_LDO_VA12_1_RC2_OP_CFG_ADDR 0x1C9D +#define MT6363_RG_LDO_VA12_1_RC3_OP_CFG_ADDR 0x1C9D +#define MT6363_RG_LDO_VA12_1_RC4_OP_CFG_ADDR 0x1C9D +#define MT6363_RG_LDO_VA12_1_RC5_OP_CFG_ADDR 0x1C9D +#define MT6363_RG_LDO_VA12_1_RC6_OP_CFG_ADDR 0x1C9D +#define MT6363_RG_LDO_VA12_1_RC7_OP_CFG_ADDR 0x1C9D +#define MT6363_RG_LDO_VA12_1_RC8_OP_CFG_ADDR 0x1C9E +#define MT6363_RG_LDO_VA12_1_RC9_OP_CFG_ADDR 0x1C9E +#define MT6363_RG_LDO_VA12_1_RC10_OP_CFG_ADDR 0x1C9E +#define MT6363_RG_LDO_VA12_1_RC11_OP_CFG_ADDR 0x1C9E +#define MT6363_RG_LDO_VA12_1_RC12_OP_CFG_ADDR 0x1C9E +#define MT6363_RG_LDO_VA12_1_RC13_OP_CFG_ADDR 0x1C9E +#define MT6363_RG_LDO_VA12_1_HW0_OP_CFG_ADDR 0x1C9F +#define MT6363_RG_LDO_VA12_1_HW1_OP_CFG_ADDR 0x1C9F +#define MT6363_RG_LDO_VA12_1_HW2_OP_CFG_ADDR 0x1C9F +#define MT6363_RG_LDO_VA12_1_HW3_OP_CFG_ADDR 0x1C9F +#define MT6363_RG_LDO_VA12_1_HW4_OP_CFG_ADDR 0x1C9F +#define MT6363_RG_LDO_VA12_1_HW5_OP_CFG_ADDR 0x1C9F +#define MT6363_RG_LDO_VA12_1_HW6_OP_CFG_ADDR 0x1C9F +#define MT6363_RG_LDO_VA12_1_SW_OP_CFG_ADDR 0x1C9F +#define MT6363_RG_LDO_VA12_1_RC0_OP_MODE_ADDR 0x1CA0 +#define MT6363_RG_LDO_VA12_1_RC1_OP_MODE_ADDR 0x1CA0 +#define MT6363_RG_LDO_VA12_1_RC2_OP_MODE_ADDR 0x1CA0 +#define MT6363_RG_LDO_VA12_1_RC3_OP_MODE_ADDR 0x1CA0 +#define MT6363_RG_LDO_VA12_1_RC4_OP_MODE_ADDR 0x1CA0 +#define MT6363_RG_LDO_VA12_1_RC5_OP_MODE_ADDR 0x1CA0 +#define MT6363_RG_LDO_VA12_1_RC6_OP_MODE_ADDR 0x1CA0 +#define MT6363_RG_LDO_VA12_1_RC7_OP_MODE_ADDR 0x1CA0 +#define MT6363_RG_LDO_VA12_1_RC8_OP_MODE_ADDR 0x1CA1 +#define MT6363_RG_LDO_VA12_1_RC9_OP_MODE_ADDR 0x1CA1 +#define MT6363_RG_LDO_VA12_1_RC10_OP_MODE_ADDR 0x1CA1 +#define MT6363_RG_LDO_VA12_1_RC11_OP_MODE_ADDR 0x1CA1 +#define MT6363_RG_LDO_VA12_1_RC12_OP_MODE_ADDR 0x1CA1 +#define MT6363_RG_LDO_VA12_1_RC13_OP_MODE_ADDR 0x1CA1 +#define MT6363_RG_LDO_VA12_1_HW0_OP_MODE_ADDR 0x1CA2 +#define MT6363_RG_LDO_VA12_1_HW1_OP_MODE_ADDR 0x1CA2 +#define MT6363_RG_LDO_VA12_1_HW2_OP_MODE_ADDR 0x1CA2 +#define MT6363_RG_LDO_VA12_1_HW3_OP_MODE_ADDR 0x1CA2 +#define MT6363_RG_LDO_VA12_1_HW4_OP_MODE_ADDR 0x1CA2 +#define MT6363_RG_LDO_VA12_1_HW5_OP_MODE_ADDR 0x1CA2 +#define MT6363_RG_LDO_VA12_1_HW6_OP_MODE_ADDR 0x1CA2 +#define MT6363_RG_LDO_VA12_2_ONLV_EN_ADDR 0x1CA4 +#define MT6363_RG_LDO_VA12_2_ONLV_EN_SHIFT 3 +#define MT6363_RG_LDO_VA12_2_RC0_OP_EN_ADDR 0x1CA8 +#define MT6363_RG_LDO_VA12_2_RC1_OP_EN_ADDR 0x1CA8 +#define MT6363_RG_LDO_VA12_2_RC2_OP_EN_ADDR 0x1CA8 +#define MT6363_RG_LDO_VA12_2_RC3_OP_EN_ADDR 0x1CA8 +#define MT6363_RG_LDO_VA12_2_RC4_OP_EN_ADDR 0x1CA8 +#define MT6363_RG_LDO_VA12_2_RC5_OP_EN_ADDR 0x1CA8 +#define MT6363_RG_LDO_VA12_2_RC6_OP_EN_ADDR 0x1CA8 +#define MT6363_RG_LDO_VA12_2_RC7_OP_EN_ADDR 0x1CA8 +#define MT6363_RG_LDO_VA12_2_RC8_OP_EN_ADDR 0x1CA9 +#define MT6363_RG_LDO_VA12_2_RC9_OP_EN_ADDR 0x1CA9 +#define MT6363_RG_LDO_VA12_2_RC10_OP_EN_ADDR 0x1CA9 +#define MT6363_RG_LDO_VA12_2_RC11_OP_EN_ADDR 0x1CA9 +#define MT6363_RG_LDO_VA12_2_RC12_OP_EN_ADDR 0x1CA9 +#define MT6363_RG_LDO_VA12_2_RC13_OP_EN_ADDR 0x1CA9 +#define MT6363_RG_LDO_VA12_2_HW0_OP_EN_ADDR 0x1CAA +#define MT6363_RG_LDO_VA12_2_HW1_OP_EN_ADDR 0x1CAA +#define MT6363_RG_LDO_VA12_2_HW2_OP_EN_ADDR 0x1CAA +#define MT6363_RG_LDO_VA12_2_HW3_OP_EN_ADDR 0x1CAA +#define MT6363_RG_LDO_VA12_2_HW4_OP_EN_ADDR 0x1CAA +#define MT6363_RG_LDO_VA12_2_HW5_OP_EN_ADDR 0x1CAA +#define MT6363_RG_LDO_VA12_2_HW6_OP_EN_ADDR 0x1CAA +#define MT6363_RG_LDO_VA12_2_SW_OP_EN_ADDR 0x1CAA +#define MT6363_RG_LDO_VA12_2_RC0_OP_CFG_ADDR 0x1CAB +#define MT6363_RG_LDO_VA12_2_RC1_OP_CFG_ADDR 0x1CAB +#define MT6363_RG_LDO_VA12_2_RC2_OP_CFG_ADDR 0x1CAB +#define MT6363_RG_LDO_VA12_2_RC3_OP_CFG_ADDR 0x1CAB +#define MT6363_RG_LDO_VA12_2_RC4_OP_CFG_ADDR 0x1CAB +#define MT6363_RG_LDO_VA12_2_RC5_OP_CFG_ADDR 0x1CAB +#define MT6363_RG_LDO_VA12_2_RC6_OP_CFG_ADDR 0x1CAB +#define MT6363_RG_LDO_VA12_2_RC7_OP_CFG_ADDR 0x1CAB +#define MT6363_RG_LDO_VA12_2_RC8_OP_CFG_ADDR 0x1CAC +#define MT6363_RG_LDO_VA12_2_RC9_OP_CFG_ADDR 0x1CAC +#define MT6363_RG_LDO_VA12_2_RC10_OP_CFG_ADDR 0x1CAC +#define MT6363_RG_LDO_VA12_2_RC11_OP_CFG_ADDR 0x1CAC +#define MT6363_RG_LDO_VA12_2_RC12_OP_CFG_ADDR 0x1CAC +#define MT6363_RG_LDO_VA12_2_RC13_OP_CFG_ADDR 0x1CAC +#define MT6363_RG_LDO_VA12_2_HW0_OP_CFG_ADDR 0x1CAD +#define MT6363_RG_LDO_VA12_2_HW1_OP_CFG_ADDR 0x1CAD +#define MT6363_RG_LDO_VA12_2_HW2_OP_CFG_ADDR 0x1CAD +#define MT6363_RG_LDO_VA12_2_HW3_OP_CFG_ADDR 0x1CAD +#define MT6363_RG_LDO_VA12_2_HW4_OP_CFG_ADDR 0x1CAD +#define MT6363_RG_LDO_VA12_2_HW5_OP_CFG_ADDR 0x1CAD +#define MT6363_RG_LDO_VA12_2_HW6_OP_CFG_ADDR 0x1CAD +#define MT6363_RG_LDO_VA12_2_SW_OP_CFG_ADDR 0x1CAD +#define MT6363_RG_LDO_VA12_2_RC0_OP_MODE_ADDR 0x1CAE +#define MT6363_RG_LDO_VA12_2_RC1_OP_MODE_ADDR 0x1CAE +#define MT6363_RG_LDO_VA12_2_RC2_OP_MODE_ADDR 0x1CAE +#define MT6363_RG_LDO_VA12_2_RC3_OP_MODE_ADDR 0x1CAE +#define MT6363_RG_LDO_VA12_2_RC4_OP_MODE_ADDR 0x1CAE +#define MT6363_RG_LDO_VA12_2_RC5_OP_MODE_ADDR 0x1CAE +#define MT6363_RG_LDO_VA12_2_RC6_OP_MODE_ADDR 0x1CAE +#define MT6363_RG_LDO_VA12_2_RC7_OP_MODE_ADDR 0x1CAE +#define MT6363_RG_LDO_VA12_2_RC8_OP_MODE_ADDR 0x1CAF +#define MT6363_RG_LDO_VA12_2_RC9_OP_MODE_ADDR 0x1CAF +#define MT6363_RG_LDO_VA12_2_RC10_OP_MODE_ADDR 0x1CAF +#define MT6363_RG_LDO_VA12_2_RC11_OP_MODE_ADDR 0x1CAF +#define MT6363_RG_LDO_VA12_2_RC12_OP_MODE_ADDR 0x1CAF +#define MT6363_RG_LDO_VA12_2_RC13_OP_MODE_ADDR 0x1CAF +#define MT6363_RG_LDO_VA12_2_HW0_OP_MODE_ADDR 0x1CB0 +#define MT6363_RG_LDO_VA12_2_HW1_OP_MODE_ADDR 0x1CB0 +#define MT6363_RG_LDO_VA12_2_HW2_OP_MODE_ADDR 0x1CB0 +#define MT6363_RG_LDO_VA12_2_HW3_OP_MODE_ADDR 0x1CB0 +#define MT6363_RG_LDO_VA12_2_HW4_OP_MODE_ADDR 0x1CB0 +#define MT6363_RG_LDO_VA12_2_HW5_OP_MODE_ADDR 0x1CB0 +#define MT6363_RG_LDO_VA12_2_HW6_OP_MODE_ADDR 0x1CB0 +#define MT6363_RG_LDO_VA15_ONLV_EN_ADDR 0x1CB2 +#define MT6363_RG_LDO_VA15_ONLV_EN_SHIFT 3 +#define MT6363_RG_LDO_VA15_RC0_OP_EN_ADDR 0x1CB6 +#define MT6363_RG_LDO_VA15_RC1_OP_EN_ADDR 0x1CB6 +#define MT6363_RG_LDO_VA15_RC2_OP_EN_ADDR 0x1CB6 +#define MT6363_RG_LDO_VA15_RC3_OP_EN_ADDR 0x1CB6 +#define MT6363_RG_LDO_VA15_RC4_OP_EN_ADDR 0x1CB6 +#define MT6363_RG_LDO_VA15_RC5_OP_EN_ADDR 0x1CB6 +#define MT6363_RG_LDO_VA15_RC6_OP_EN_ADDR 0x1CB6 +#define MT6363_RG_LDO_VA15_RC7_OP_EN_ADDR 0x1CB6 +#define MT6363_RG_LDO_VA15_RC8_OP_EN_ADDR 0x1CB7 +#define MT6363_RG_LDO_VA15_RC9_OP_EN_ADDR 0x1CB7 +#define MT6363_RG_LDO_VA15_RC10_OP_EN_ADDR 0x1CB7 +#define MT6363_RG_LDO_VA15_RC11_OP_EN_ADDR 0x1CB7 +#define MT6363_RG_LDO_VA15_RC12_OP_EN_ADDR 0x1CB7 +#define MT6363_RG_LDO_VA15_RC13_OP_EN_ADDR 0x1CB7 +#define MT6363_RG_LDO_VA15_HW0_OP_EN_ADDR 0x1CB8 +#define MT6363_RG_LDO_VA15_HW1_OP_EN_ADDR 0x1CB8 +#define MT6363_RG_LDO_VA15_HW2_OP_EN_ADDR 0x1CB8 +#define MT6363_RG_LDO_VA15_HW3_OP_EN_ADDR 0x1CB8 +#define MT6363_RG_LDO_VA15_HW4_OP_EN_ADDR 0x1CB8 +#define MT6363_RG_LDO_VA15_HW5_OP_EN_ADDR 0x1CB8 +#define MT6363_RG_LDO_VA15_HW6_OP_EN_ADDR 0x1CB8 +#define MT6363_RG_LDO_VA15_SW_OP_EN_ADDR 0x1CB8 +#define MT6363_RG_LDO_VA15_RC0_OP_CFG_ADDR 0x1CB9 +#define MT6363_RG_LDO_VA15_RC1_OP_CFG_ADDR 0x1CB9 +#define MT6363_RG_LDO_VA15_RC2_OP_CFG_ADDR 0x1CB9 +#define MT6363_RG_LDO_VA15_RC3_OP_CFG_ADDR 0x1CB9 +#define MT6363_RG_LDO_VA15_RC4_OP_CFG_ADDR 0x1CB9 +#define MT6363_RG_LDO_VA15_RC5_OP_CFG_ADDR 0x1CB9 +#define MT6363_RG_LDO_VA15_RC6_OP_CFG_ADDR 0x1CB9 +#define MT6363_RG_LDO_VA15_RC7_OP_CFG_ADDR 0x1CB9 +#define MT6363_RG_LDO_VA15_RC8_OP_CFG_ADDR 0x1CBA +#define MT6363_RG_LDO_VA15_RC9_OP_CFG_ADDR 0x1CBA +#define MT6363_RG_LDO_VA15_RC10_OP_CFG_ADDR 0x1CBA +#define MT6363_RG_LDO_VA15_RC11_OP_CFG_ADDR 0x1CBA +#define MT6363_RG_LDO_VA15_RC12_OP_CFG_ADDR 0x1CBA +#define MT6363_RG_LDO_VA15_RC13_OP_CFG_ADDR 0x1CBA +#define MT6363_RG_LDO_VA15_HW0_OP_CFG_ADDR 0x1CBB +#define MT6363_RG_LDO_VA15_HW1_OP_CFG_ADDR 0x1CBB +#define MT6363_RG_LDO_VA15_HW2_OP_CFG_ADDR 0x1CBB +#define MT6363_RG_LDO_VA15_HW3_OP_CFG_ADDR 0x1CBB +#define MT6363_RG_LDO_VA15_HW4_OP_CFG_ADDR 0x1CBB +#define MT6363_RG_LDO_VA15_HW5_OP_CFG_ADDR 0x1CBB +#define MT6363_RG_LDO_VA15_HW6_OP_CFG_ADDR 0x1CBB +#define MT6363_RG_LDO_VA15_SW_OP_CFG_ADDR 0x1CBB +#define MT6363_RG_LDO_VA15_RC0_OP_MODE_ADDR 0x1CBC +#define MT6363_RG_LDO_VA15_RC1_OP_MODE_ADDR 0x1CBC +#define MT6363_RG_LDO_VA15_RC2_OP_MODE_ADDR 0x1CBC +#define MT6363_RG_LDO_VA15_RC3_OP_MODE_ADDR 0x1CBC +#define MT6363_RG_LDO_VA15_RC4_OP_MODE_ADDR 0x1CBC +#define MT6363_RG_LDO_VA15_RC5_OP_MODE_ADDR 0x1CBC +#define MT6363_RG_LDO_VA15_RC6_OP_MODE_ADDR 0x1CBC +#define MT6363_RG_LDO_VA15_RC7_OP_MODE_ADDR 0x1CBC +#define MT6363_RG_LDO_VA15_RC8_OP_MODE_ADDR 0x1CBD +#define MT6363_RG_LDO_VA15_RC9_OP_MODE_ADDR 0x1CBD +#define MT6363_RG_LDO_VA15_RC10_OP_MODE_ADDR 0x1CBD +#define MT6363_RG_LDO_VA15_RC11_OP_MODE_ADDR 0x1CBD +#define MT6363_RG_LDO_VA15_RC12_OP_MODE_ADDR 0x1CBD +#define MT6363_RG_LDO_VA15_RC13_OP_MODE_ADDR 0x1CBD +#define MT6363_RG_LDO_VA15_HW0_OP_MODE_ADDR 0x1CBE +#define MT6363_RG_LDO_VA15_HW1_OP_MODE_ADDR 0x1CBE +#define MT6363_RG_LDO_VA15_HW2_OP_MODE_ADDR 0x1CBE +#define MT6363_RG_LDO_VA15_HW3_OP_MODE_ADDR 0x1CBE +#define MT6363_RG_LDO_VA15_HW4_OP_MODE_ADDR 0x1CBE +#define MT6363_RG_LDO_VA15_HW5_OP_MODE_ADDR 0x1CBE +#define MT6363_RG_LDO_VA15_HW6_OP_MODE_ADDR 0x1CBE +#define MT6363_RG_LDO_VM18_ONLV_EN_ADDR 0x1CC0 +#define MT6363_RG_LDO_VM18_ONLV_EN_SHIFT 3 +#define MT6363_RG_LDO_VM18_RC0_OP_EN_ADDR 0x1CC4 +#define MT6363_RG_LDO_VM18_RC1_OP_EN_ADDR 0x1CC4 +#define MT6363_RG_LDO_VM18_RC2_OP_EN_ADDR 0x1CC4 +#define MT6363_RG_LDO_VM18_RC3_OP_EN_ADDR 0x1CC4 +#define MT6363_RG_LDO_VM18_RC4_OP_EN_ADDR 0x1CC4 +#define MT6363_RG_LDO_VM18_RC5_OP_EN_ADDR 0x1CC4 +#define MT6363_RG_LDO_VM18_RC6_OP_EN_ADDR 0x1CC4 +#define MT6363_RG_LDO_VM18_RC7_OP_EN_ADDR 0x1CC4 +#define MT6363_RG_LDO_VM18_RC8_OP_EN_ADDR 0x1CC5 +#define MT6363_RG_LDO_VM18_RC9_OP_EN_ADDR 0x1CC5 +#define MT6363_RG_LDO_VM18_RC10_OP_EN_ADDR 0x1CC5 +#define MT6363_RG_LDO_VM18_RC11_OP_EN_ADDR 0x1CC5 +#define MT6363_RG_LDO_VM18_RC12_OP_EN_ADDR 0x1CC5 +#define MT6363_RG_LDO_VM18_RC13_OP_EN_ADDR 0x1CC5 +#define MT6363_RG_LDO_VM18_HW0_OP_EN_ADDR 0x1CC6 +#define MT6363_RG_LDO_VM18_HW1_OP_EN_ADDR 0x1CC6 +#define MT6363_RG_LDO_VM18_HW2_OP_EN_ADDR 0x1CC6 +#define MT6363_RG_LDO_VM18_HW3_OP_EN_ADDR 0x1CC6 +#define MT6363_RG_LDO_VM18_HW4_OP_EN_ADDR 0x1CC6 +#define MT6363_RG_LDO_VM18_HW5_OP_EN_ADDR 0x1CC6 +#define MT6363_RG_LDO_VM18_HW6_OP_EN_ADDR 0x1CC6 +#define MT6363_RG_LDO_VM18_SW_OP_EN_ADDR 0x1CC6 +#define MT6363_RG_LDO_VM18_RC0_OP_CFG_ADDR 0x1CC7 +#define MT6363_RG_LDO_VM18_RC1_OP_CFG_ADDR 0x1CC7 +#define MT6363_RG_LDO_VM18_RC2_OP_CFG_ADDR 0x1CC7 +#define MT6363_RG_LDO_VM18_RC3_OP_CFG_ADDR 0x1CC7 +#define MT6363_RG_LDO_VM18_RC4_OP_CFG_ADDR 0x1CC7 +#define MT6363_RG_LDO_VM18_RC5_OP_CFG_ADDR 0x1CC7 +#define MT6363_RG_LDO_VM18_RC6_OP_CFG_ADDR 0x1CC7 +#define MT6363_RG_LDO_VM18_RC7_OP_CFG_ADDR 0x1CC7 +#define MT6363_RG_LDO_VM18_RC8_OP_CFG_ADDR 0x1CC8 +#define MT6363_RG_LDO_VM18_RC9_OP_CFG_ADDR 0x1CC8 +#define MT6363_RG_LDO_VM18_RC10_OP_CFG_ADDR 0x1CC8 +#define MT6363_RG_LDO_VM18_RC11_OP_CFG_ADDR 0x1CC8 +#define MT6363_RG_LDO_VM18_RC12_OP_CFG_ADDR 0x1CC8 +#define MT6363_RG_LDO_VM18_RC13_OP_CFG_ADDR 0x1CC8 +#define MT6363_RG_LDO_VM18_HW0_OP_CFG_ADDR 0x1CC9 +#define MT6363_RG_LDO_VM18_HW1_OP_CFG_ADDR 0x1CC9 +#define MT6363_RG_LDO_VM18_HW2_OP_CFG_ADDR 0x1CC9 +#define MT6363_RG_LDO_VM18_HW3_OP_CFG_ADDR 0x1CC9 +#define MT6363_RG_LDO_VM18_HW4_OP_CFG_ADDR 0x1CC9 +#define MT6363_RG_LDO_VM18_HW5_OP_CFG_ADDR 0x1CC9 +#define MT6363_RG_LDO_VM18_HW6_OP_CFG_ADDR 0x1CC9 +#define MT6363_RG_LDO_VM18_SW_OP_CFG_ADDR 0x1CC9 +#define MT6363_RG_LDO_VM18_RC0_OP_MODE_ADDR 0x1CCA +#define MT6363_RG_LDO_VM18_RC1_OP_MODE_ADDR 0x1CCA +#define MT6363_RG_LDO_VM18_RC2_OP_MODE_ADDR 0x1CCA +#define MT6363_RG_LDO_VM18_RC3_OP_MODE_ADDR 0x1CCA +#define MT6363_RG_LDO_VM18_RC4_OP_MODE_ADDR 0x1CCA +#define MT6363_RG_LDO_VM18_RC5_OP_MODE_ADDR 0x1CCA +#define MT6363_RG_LDO_VM18_RC6_OP_MODE_ADDR 0x1CCA +#define MT6363_RG_LDO_VM18_RC7_OP_MODE_ADDR 0x1CCA +#define MT6363_RG_LDO_VM18_RC8_OP_MODE_ADDR 0x1CCB +#define MT6363_RG_LDO_VM18_RC9_OP_MODE_ADDR 0x1CCB +#define MT6363_RG_LDO_VM18_RC10_OP_MODE_ADDR 0x1CCB +#define MT6363_RG_LDO_VM18_RC11_OP_MODE_ADDR 0x1CCB +#define MT6363_RG_LDO_VM18_RC12_OP_MODE_ADDR 0x1CCB +#define MT6363_RG_LDO_VM18_RC13_OP_MODE_ADDR 0x1CCB +#define MT6363_RG_LDO_VM18_HW0_OP_MODE_ADDR 0x1CCC +#define MT6363_RG_LDO_VM18_HW1_OP_MODE_ADDR 0x1CCC +#define MT6363_RG_LDO_VM18_HW2_OP_MODE_ADDR 0x1CCC +#define MT6363_RG_LDO_VM18_HW3_OP_MODE_ADDR 0x1CCC +#define MT6363_RG_LDO_VM18_HW4_OP_MODE_ADDR 0x1CCC +#define MT6363_RG_LDO_VM18_HW5_OP_MODE_ADDR 0x1CCC +#define MT6363_RG_LDO_VM18_HW6_OP_MODE_ADDR 0x1CCC +#define MT6363_RG_LDO_VCN13_ONLV_EN_ADDR 0x1D08 +#define MT6363_RG_LDO_VCN13_ONLV_EN_SHIFT 3 +#define MT6363_RG_LDO_VCN13_VOSEL_SLEEP_ADDR 0x1D0D +#define MT6363_RG_LDO_VCN13_RC0_OP_EN_ADDR 0x1D14 +#define MT6363_RG_LDO_VCN13_RC1_OP_EN_ADDR 0x1D14 +#define MT6363_RG_LDO_VCN13_RC2_OP_EN_ADDR 0x1D14 +#define MT6363_RG_LDO_VCN13_RC3_OP_EN_ADDR 0x1D14 +#define MT6363_RG_LDO_VCN13_RC4_OP_EN_ADDR 0x1D14 +#define MT6363_RG_LDO_VCN13_RC5_OP_EN_ADDR 0x1D14 +#define MT6363_RG_LDO_VCN13_RC6_OP_EN_ADDR 0x1D14 +#define MT6363_RG_LDO_VCN13_RC7_OP_EN_ADDR 0x1D14 +#define MT6363_RG_LDO_VCN13_RC8_OP_EN_ADDR 0x1D15 +#define MT6363_RG_LDO_VCN13_RC9_OP_EN_ADDR 0x1D15 +#define MT6363_RG_LDO_VCN13_RC10_OP_EN_ADDR 0x1D15 +#define MT6363_RG_LDO_VCN13_RC11_OP_EN_ADDR 0x1D15 +#define MT6363_RG_LDO_VCN13_RC12_OP_EN_ADDR 0x1D15 +#define MT6363_RG_LDO_VCN13_RC13_OP_EN_ADDR 0x1D15 +#define MT6363_RG_LDO_VCN13_HW0_OP_EN_ADDR 0x1D16 +#define MT6363_RG_LDO_VCN13_HW1_OP_EN_ADDR 0x1D16 +#define MT6363_RG_LDO_VCN13_HW2_OP_EN_ADDR 0x1D16 +#define MT6363_RG_LDO_VCN13_HW3_OP_EN_ADDR 0x1D16 +#define MT6363_RG_LDO_VCN13_HW4_OP_EN_ADDR 0x1D16 +#define MT6363_RG_LDO_VCN13_HW5_OP_EN_ADDR 0x1D16 +#define MT6363_RG_LDO_VCN13_HW6_OP_EN_ADDR 0x1D16 +#define MT6363_RG_LDO_VCN13_SW_OP_EN_ADDR 0x1D16 +#define MT6363_RG_LDO_VCN13_RC0_OP_CFG_ADDR 0x1D17 +#define MT6363_RG_LDO_VCN13_RC1_OP_CFG_ADDR 0x1D17 +#define MT6363_RG_LDO_VCN13_RC2_OP_CFG_ADDR 0x1D17 +#define MT6363_RG_LDO_VCN13_RC3_OP_CFG_ADDR 0x1D17 +#define MT6363_RG_LDO_VCN13_RC4_OP_CFG_ADDR 0x1D17 +#define MT6363_RG_LDO_VCN13_RC5_OP_CFG_ADDR 0x1D17 +#define MT6363_RG_LDO_VCN13_RC6_OP_CFG_ADDR 0x1D17 +#define MT6363_RG_LDO_VCN13_RC7_OP_CFG_ADDR 0x1D17 +#define MT6363_RG_LDO_VCN13_RC8_OP_CFG_ADDR 0x1D18 +#define MT6363_RG_LDO_VCN13_RC9_OP_CFG_ADDR 0x1D18 +#define MT6363_RG_LDO_VCN13_RC10_OP_CFG_ADDR 0x1D18 +#define MT6363_RG_LDO_VCN13_RC11_OP_CFG_ADDR 0x1D18 +#define MT6363_RG_LDO_VCN13_RC12_OP_CFG_ADDR 0x1D18 +#define MT6363_RG_LDO_VCN13_RC13_OP_CFG_ADDR 0x1D18 +#define MT6363_RG_LDO_VCN13_HW0_OP_CFG_ADDR 0x1D19 +#define MT6363_RG_LDO_VCN13_HW1_OP_CFG_ADDR 0x1D19 +#define MT6363_RG_LDO_VCN13_HW2_OP_CFG_ADDR 0x1D19 +#define MT6363_RG_LDO_VCN13_HW3_OP_CFG_ADDR 0x1D19 +#define MT6363_RG_LDO_VCN13_HW4_OP_CFG_ADDR 0x1D19 +#define MT6363_RG_LDO_VCN13_HW5_OP_CFG_ADDR 0x1D19 +#define MT6363_RG_LDO_VCN13_HW6_OP_CFG_ADDR 0x1D19 +#define MT6363_RG_LDO_VCN13_SW_OP_CFG_ADDR 0x1D19 +#define MT6363_RG_LDO_VCN13_RC0_OP_MODE_ADDR 0x1D1A +#define MT6363_RG_LDO_VCN13_RC1_OP_MODE_ADDR 0x1D1A +#define MT6363_RG_LDO_VCN13_RC2_OP_MODE_ADDR 0x1D1A +#define MT6363_RG_LDO_VCN13_RC3_OP_MODE_ADDR 0x1D1A +#define MT6363_RG_LDO_VCN13_RC4_OP_MODE_ADDR 0x1D1A +#define MT6363_RG_LDO_VCN13_RC5_OP_MODE_ADDR 0x1D1A +#define MT6363_RG_LDO_VCN13_RC6_OP_MODE_ADDR 0x1D1A +#define MT6363_RG_LDO_VCN13_RC7_OP_MODE_ADDR 0x1D1A +#define MT6363_RG_LDO_VCN13_RC8_OP_MODE_ADDR 0x1D1B +#define MT6363_RG_LDO_VCN13_RC9_OP_MODE_ADDR 0x1D1B +#define MT6363_RG_LDO_VCN13_RC10_OP_MODE_ADDR 0x1D1B +#define MT6363_RG_LDO_VCN13_RC11_OP_MODE_ADDR 0x1D1B +#define MT6363_RG_LDO_VCN13_RC12_OP_MODE_ADDR 0x1D1B +#define MT6363_RG_LDO_VCN13_RC13_OP_MODE_ADDR 0x1D1B +#define MT6363_RG_LDO_VCN13_HW0_OP_MODE_ADDR 0x1D1C +#define MT6363_RG_LDO_VCN13_HW1_OP_MODE_ADDR 0x1D1C +#define MT6363_RG_LDO_VCN13_HW2_OP_MODE_ADDR 0x1D1C +#define MT6363_RG_LDO_VCN13_HW3_OP_MODE_ADDR 0x1D1C +#define MT6363_RG_LDO_VCN13_HW4_OP_MODE_ADDR 0x1D1C +#define MT6363_RG_LDO_VCN13_HW5_OP_MODE_ADDR 0x1D1C +#define MT6363_RG_LDO_VCN13_HW6_OP_MODE_ADDR 0x1D1C +#define MT6363_RG_LDO_VSRAM_DIGRF_ONLV_EN_ADDR 0x1D1E +#define MT6363_RG_LDO_VSRAM_DIGRF_ONLV_EN_SHIFT 3 +#define MT6363_RG_LDO_VSRAM_DIGRF_VOSEL_SLEEP_ADDR 0x1D23 +#define MT6363_RG_LDO_VSRAM_DIGRF_RC0_OP_EN_ADDR 0x1D2A +#define MT6363_RG_LDO_VSRAM_DIGRF_RC1_OP_EN_ADDR 0x1D2A +#define MT6363_RG_LDO_VSRAM_DIGRF_RC2_OP_EN_ADDR 0x1D2A +#define MT6363_RG_LDO_VSRAM_DIGRF_RC3_OP_EN_ADDR 0x1D2A +#define MT6363_RG_LDO_VSRAM_DIGRF_RC4_OP_EN_ADDR 0x1D2A +#define MT6363_RG_LDO_VSRAM_DIGRF_RC5_OP_EN_ADDR 0x1D2A +#define MT6363_RG_LDO_VSRAM_DIGRF_RC6_OP_EN_ADDR 0x1D2A +#define MT6363_RG_LDO_VSRAM_DIGRF_RC7_OP_EN_ADDR 0x1D2A +#define MT6363_RG_LDO_VSRAM_DIGRF_RC8_OP_EN_ADDR 0x1D2B +#define MT6363_RG_LDO_VSRAM_DIGRF_RC9_OP_EN_ADDR 0x1D2B +#define MT6363_RG_LDO_VSRAM_DIGRF_RC10_OP_EN_ADDR 0x1D2B +#define MT6363_RG_LDO_VSRAM_DIGRF_RC11_OP_EN_ADDR 0x1D2B +#define MT6363_RG_LDO_VSRAM_DIGRF_RC12_OP_EN_ADDR 0x1D2B +#define MT6363_RG_LDO_VSRAM_DIGRF_RC13_OP_EN_ADDR 0x1D2B +#define MT6363_RG_LDO_VSRAM_DIGRF_HW0_OP_EN_ADDR 0x1D2C +#define MT6363_RG_LDO_VSRAM_DIGRF_HW1_OP_EN_ADDR 0x1D2C +#define MT6363_RG_LDO_VSRAM_DIGRF_HW2_OP_EN_ADDR 0x1D2C +#define MT6363_RG_LDO_VSRAM_DIGRF_HW3_OP_EN_ADDR 0x1D2C +#define MT6363_RG_LDO_VSRAM_DIGRF_HW4_OP_EN_ADDR 0x1D2C +#define MT6363_RG_LDO_VSRAM_DIGRF_HW5_OP_EN_ADDR 0x1D2C +#define MT6363_RG_LDO_VSRAM_DIGRF_HW6_OP_EN_ADDR 0x1D2C +#define MT6363_RG_LDO_VSRAM_DIGRF_SW_OP_EN_ADDR 0x1D2C +#define MT6363_RG_LDO_VSRAM_DIGRF_RC0_OP_CFG_ADDR 0x1D2D +#define MT6363_RG_LDO_VSRAM_DIGRF_RC1_OP_CFG_ADDR 0x1D2D +#define MT6363_RG_LDO_VSRAM_DIGRF_RC2_OP_CFG_ADDR 0x1D2D +#define MT6363_RG_LDO_VSRAM_DIGRF_RC3_OP_CFG_ADDR 0x1D2D +#define MT6363_RG_LDO_VSRAM_DIGRF_RC4_OP_CFG_ADDR 0x1D2D +#define MT6363_RG_LDO_VSRAM_DIGRF_RC5_OP_CFG_ADDR 0x1D2D +#define MT6363_RG_LDO_VSRAM_DIGRF_RC6_OP_CFG_ADDR 0x1D2D +#define MT6363_RG_LDO_VSRAM_DIGRF_RC7_OP_CFG_ADDR 0x1D2D +#define MT6363_RG_LDO_VSRAM_DIGRF_RC8_OP_CFG_ADDR 0x1D2E +#define MT6363_RG_LDO_VSRAM_DIGRF_RC9_OP_CFG_ADDR 0x1D2E +#define MT6363_RG_LDO_VSRAM_DIGRF_RC10_OP_CFG_ADDR 0x1D2E +#define MT6363_RG_LDO_VSRAM_DIGRF_RC11_OP_CFG_ADDR 0x1D2E +#define MT6363_RG_LDO_VSRAM_DIGRF_RC12_OP_CFG_ADDR 0x1D2E +#define MT6363_RG_LDO_VSRAM_DIGRF_RC13_OP_CFG_ADDR 0x1D2E +#define MT6363_RG_LDO_VSRAM_DIGRF_HW0_OP_CFG_ADDR 0x1D2F +#define MT6363_RG_LDO_VSRAM_DIGRF_HW1_OP_CFG_ADDR 0x1D2F +#define MT6363_RG_LDO_VSRAM_DIGRF_HW2_OP_CFG_ADDR 0x1D2F +#define MT6363_RG_LDO_VSRAM_DIGRF_HW3_OP_CFG_ADDR 0x1D2F +#define MT6363_RG_LDO_VSRAM_DIGRF_HW4_OP_CFG_ADDR 0x1D2F +#define MT6363_RG_LDO_VSRAM_DIGRF_HW5_OP_CFG_ADDR 0x1D2F +#define MT6363_RG_LDO_VSRAM_DIGRF_HW6_OP_CFG_ADDR 0x1D2F +#define MT6363_RG_LDO_VSRAM_DIGRF_SW_OP_CFG_ADDR 0x1D2F +#define MT6363_RG_LDO_VSRAM_DIGRF_RC0_OP_MODE_ADDR 0x1D30 +#define MT6363_RG_LDO_VSRAM_DIGRF_RC1_OP_MODE_ADDR 0x1D30 +#define MT6363_RG_LDO_VSRAM_DIGRF_RC2_OP_MODE_ADDR 0x1D30 +#define MT6363_RG_LDO_VSRAM_DIGRF_RC3_OP_MODE_ADDR 0x1D30 +#define MT6363_RG_LDO_VSRAM_DIGRF_RC4_OP_MODE_ADDR 0x1D30 +#define MT6363_RG_LDO_VSRAM_DIGRF_RC5_OP_MODE_ADDR 0x1D30 +#define MT6363_RG_LDO_VSRAM_DIGRF_RC6_OP_MODE_ADDR 0x1D30 +#define MT6363_RG_LDO_VSRAM_DIGRF_RC7_OP_MODE_ADDR 0x1D30 +#define MT6363_RG_LDO_VSRAM_DIGRF_RC8_OP_MODE_ADDR 0x1D31 +#define MT6363_RG_LDO_VSRAM_DIGRF_RC9_OP_MODE_ADDR 0x1D31 +#define MT6363_RG_LDO_VSRAM_DIGRF_RC10_OP_MODE_ADDR 0x1D31 +#define MT6363_RG_LDO_VSRAM_DIGRF_RC11_OP_MODE_ADDR 0x1D31 +#define MT6363_RG_LDO_VSRAM_DIGRF_RC12_OP_MODE_ADDR 0x1D31 +#define MT6363_RG_LDO_VSRAM_DIGRF_RC13_OP_MODE_ADDR 0x1D31 +#define MT6363_RG_LDO_VSRAM_DIGRF_HW0_OP_MODE_ADDR 0x1D32 +#define MT6363_RG_LDO_VSRAM_DIGRF_HW1_OP_MODE_ADDR 0x1D32 +#define MT6363_RG_LDO_VSRAM_DIGRF_HW2_OP_MODE_ADDR 0x1D32 +#define MT6363_RG_LDO_VSRAM_DIGRF_HW3_OP_MODE_ADDR 0x1D32 +#define MT6363_RG_LDO_VSRAM_DIGRF_HW4_OP_MODE_ADDR 0x1D32 +#define MT6363_RG_LDO_VSRAM_DIGRF_HW5_OP_MODE_ADDR 0x1D32 +#define MT6363_RG_LDO_VSRAM_DIGRF_HW6_OP_MODE_ADDR 0x1D32 +#define MT6363_RG_LDO_VSRAM_MDFE_ONLV_EN_ADDR 0x1D88 +#define MT6363_RG_LDO_VSRAM_MDFE_ONLV_EN_SHIFT 3 +#define MT6363_RG_LDO_VSRAM_MDFE_VOSEL_SLEEP_ADDR 0x1D8D +#define MT6363_RG_LDO_VSRAM_MDFE_RC0_OP_EN_ADDR 0x1D94 +#define MT6363_RG_LDO_VSRAM_MDFE_RC1_OP_EN_ADDR 0x1D94 +#define MT6363_RG_LDO_VSRAM_MDFE_RC2_OP_EN_ADDR 0x1D94 +#define MT6363_RG_LDO_VSRAM_MDFE_RC3_OP_EN_ADDR 0x1D94 +#define MT6363_RG_LDO_VSRAM_MDFE_RC4_OP_EN_ADDR 0x1D94 +#define MT6363_RG_LDO_VSRAM_MDFE_RC5_OP_EN_ADDR 0x1D94 +#define MT6363_RG_LDO_VSRAM_MDFE_RC6_OP_EN_ADDR 0x1D94 +#define MT6363_RG_LDO_VSRAM_MDFE_RC7_OP_EN_ADDR 0x1D94 +#define MT6363_RG_LDO_VSRAM_MDFE_RC8_OP_EN_ADDR 0x1D95 +#define MT6363_RG_LDO_VSRAM_MDFE_RC9_OP_EN_ADDR 0x1D95 +#define MT6363_RG_LDO_VSRAM_MDFE_RC10_OP_EN_ADDR 0x1D95 +#define MT6363_RG_LDO_VSRAM_MDFE_RC11_OP_EN_ADDR 0x1D95 +#define MT6363_RG_LDO_VSRAM_MDFE_RC12_OP_EN_ADDR 0x1D95 +#define MT6363_RG_LDO_VSRAM_MDFE_RC13_OP_EN_ADDR 0x1D95 +#define MT6363_RG_LDO_VSRAM_MDFE_HW0_OP_EN_ADDR 0x1D96 +#define MT6363_RG_LDO_VSRAM_MDFE_HW1_OP_EN_ADDR 0x1D96 +#define MT6363_RG_LDO_VSRAM_MDFE_HW2_OP_EN_ADDR 0x1D96 +#define MT6363_RG_LDO_VSRAM_MDFE_HW3_OP_EN_ADDR 0x1D96 +#define MT6363_RG_LDO_VSRAM_MDFE_HW4_OP_EN_ADDR 0x1D96 +#define MT6363_RG_LDO_VSRAM_MDFE_HW5_OP_EN_ADDR 0x1D96 +#define MT6363_RG_LDO_VSRAM_MDFE_HW6_OP_EN_ADDR 0x1D96 +#define MT6363_RG_LDO_VSRAM_MDFE_SW_OP_EN_ADDR 0x1D96 +#define MT6363_RG_LDO_VSRAM_MDFE_RC0_OP_CFG_ADDR 0x1D97 +#define MT6363_RG_LDO_VSRAM_MDFE_RC1_OP_CFG_ADDR 0x1D97 +#define MT6363_RG_LDO_VSRAM_MDFE_RC2_OP_CFG_ADDR 0x1D97 +#define MT6363_RG_LDO_VSRAM_MDFE_RC3_OP_CFG_ADDR 0x1D97 +#define MT6363_RG_LDO_VSRAM_MDFE_RC4_OP_CFG_ADDR 0x1D97 +#define MT6363_RG_LDO_VSRAM_MDFE_RC5_OP_CFG_ADDR 0x1D97 +#define MT6363_RG_LDO_VSRAM_MDFE_RC6_OP_CFG_ADDR 0x1D97 +#define MT6363_RG_LDO_VSRAM_MDFE_RC7_OP_CFG_ADDR 0x1D97 +#define MT6363_RG_LDO_VSRAM_MDFE_RC8_OP_CFG_ADDR 0x1D98 +#define MT6363_RG_LDO_VSRAM_MDFE_RC9_OP_CFG_ADDR 0x1D98 +#define MT6363_RG_LDO_VSRAM_MDFE_RC10_OP_CFG_ADDR 0x1D98 +#define MT6363_RG_LDO_VSRAM_MDFE_RC11_OP_CFG_ADDR 0x1D98 +#define MT6363_RG_LDO_VSRAM_MDFE_RC12_OP_CFG_ADDR 0x1D98 +#define MT6363_RG_LDO_VSRAM_MDFE_RC13_OP_CFG_ADDR 0x1D98 +#define MT6363_RG_LDO_VSRAM_MDFE_HW0_OP_CFG_ADDR 0x1D99 +#define MT6363_RG_LDO_VSRAM_MDFE_HW1_OP_CFG_ADDR 0x1D99 +#define MT6363_RG_LDO_VSRAM_MDFE_HW2_OP_CFG_ADDR 0x1D99 +#define MT6363_RG_LDO_VSRAM_MDFE_HW3_OP_CFG_ADDR 0x1D99 +#define MT6363_RG_LDO_VSRAM_MDFE_HW4_OP_CFG_ADDR 0x1D99 +#define MT6363_RG_LDO_VSRAM_MDFE_HW5_OP_CFG_ADDR 0x1D99 +#define MT6363_RG_LDO_VSRAM_MDFE_HW6_OP_CFG_ADDR 0x1D99 +#define MT6363_RG_LDO_VSRAM_MDFE_SW_OP_CFG_ADDR 0x1D99 +#define MT6363_RG_LDO_VSRAM_MDFE_RC0_OP_MODE_ADDR 0x1D9A +#define MT6363_RG_LDO_VSRAM_MDFE_RC1_OP_MODE_ADDR 0x1D9A +#define MT6363_RG_LDO_VSRAM_MDFE_RC2_OP_MODE_ADDR 0x1D9A +#define MT6363_RG_LDO_VSRAM_MDFE_RC3_OP_MODE_ADDR 0x1D9A +#define MT6363_RG_LDO_VSRAM_MDFE_RC4_OP_MODE_ADDR 0x1D9A +#define MT6363_RG_LDO_VSRAM_MDFE_RC5_OP_MODE_ADDR 0x1D9A +#define MT6363_RG_LDO_VSRAM_MDFE_RC6_OP_MODE_ADDR 0x1D9A +#define MT6363_RG_LDO_VSRAM_MDFE_RC7_OP_MODE_ADDR 0x1D9A +#define MT6363_RG_LDO_VSRAM_MDFE_RC8_OP_MODE_ADDR 0x1D9B +#define MT6363_RG_LDO_VSRAM_MDFE_RC9_OP_MODE_ADDR 0x1D9B +#define MT6363_RG_LDO_VSRAM_MDFE_RC10_OP_MODE_ADDR 0x1D9B +#define MT6363_RG_LDO_VSRAM_MDFE_RC11_OP_MODE_ADDR 0x1D9B +#define MT6363_RG_LDO_VSRAM_MDFE_RC12_OP_MODE_ADDR 0x1D9B +#define MT6363_RG_LDO_VSRAM_MDFE_RC13_OP_MODE_ADDR 0x1D9B +#define MT6363_RG_LDO_VSRAM_MDFE_HW0_OP_MODE_ADDR 0x1D9C +#define MT6363_RG_LDO_VSRAM_MDFE_HW1_OP_MODE_ADDR 0x1D9C +#define MT6363_RG_LDO_VSRAM_MDFE_HW2_OP_MODE_ADDR 0x1D9C +#define MT6363_RG_LDO_VSRAM_MDFE_HW3_OP_MODE_ADDR 0x1D9C +#define MT6363_RG_LDO_VSRAM_MDFE_HW4_OP_MODE_ADDR 0x1D9C +#define MT6363_RG_LDO_VSRAM_MDFE_HW5_OP_MODE_ADDR 0x1D9C +#define MT6363_RG_LDO_VSRAM_MDFE_HW6_OP_MODE_ADDR 0x1D9C +#define MT6363_RG_LDO_VSRAM_MODEM_ONLV_EN_ADDR 0x1DA3 +#define MT6363_RG_LDO_VSRAM_MODEM_ONLV_EN_SHIFT 3 +#define MT6363_RG_LDO_VSRAM_MODEM_VOSEL_SLEEP_ADDR 0x1DA8 +#define MT6363_RG_LDO_VSRAM_MODEM_RC0_OP_EN_ADDR 0x1DAF +#define MT6363_RG_LDO_VSRAM_MODEM_RC1_OP_EN_ADDR 0x1DAF +#define MT6363_RG_LDO_VSRAM_MODEM_RC2_OP_EN_ADDR 0x1DAF +#define MT6363_RG_LDO_VSRAM_MODEM_RC3_OP_EN_ADDR 0x1DAF +#define MT6363_RG_LDO_VSRAM_MODEM_RC4_OP_EN_ADDR 0x1DAF +#define MT6363_RG_LDO_VSRAM_MODEM_RC5_OP_EN_ADDR 0x1DAF +#define MT6363_RG_LDO_VSRAM_MODEM_RC6_OP_EN_ADDR 0x1DAF +#define MT6363_RG_LDO_VSRAM_MODEM_RC7_OP_EN_ADDR 0x1DAF +#define MT6363_RG_LDO_VSRAM_MODEM_RC8_OP_EN_ADDR 0x1DB0 +#define MT6363_RG_LDO_VSRAM_MODEM_RC9_OP_EN_ADDR 0x1DB0 +#define MT6363_RG_LDO_VSRAM_MODEM_RC10_OP_EN_ADDR 0x1DB0 +#define MT6363_RG_LDO_VSRAM_MODEM_RC11_OP_EN_ADDR 0x1DB0 +#define MT6363_RG_LDO_VSRAM_MODEM_RC12_OP_EN_ADDR 0x1DB0 +#define MT6363_RG_LDO_VSRAM_MODEM_RC13_OP_EN_ADDR 0x1DB0 +#define MT6363_RG_LDO_VSRAM_MODEM_HW0_OP_EN_ADDR 0x1DB1 +#define MT6363_RG_LDO_VSRAM_MODEM_HW1_OP_EN_ADDR 0x1DB1 +#define MT6363_RG_LDO_VSRAM_MODEM_HW2_OP_EN_ADDR 0x1DB1 +#define MT6363_RG_LDO_VSRAM_MODEM_HW3_OP_EN_ADDR 0x1DB1 +#define MT6363_RG_LDO_VSRAM_MODEM_HW4_OP_EN_ADDR 0x1DB1 +#define MT6363_RG_LDO_VSRAM_MODEM_HW5_OP_EN_ADDR 0x1DB1 +#define MT6363_RG_LDO_VSRAM_MODEM_HW6_OP_EN_ADDR 0x1DB1 +#define MT6363_RG_LDO_VSRAM_MODEM_SW_OP_EN_ADDR 0x1DB1 +#define MT6363_RG_LDO_VSRAM_MODEM_RC0_OP_CFG_ADDR 0x1DB2 +#define MT6363_RG_LDO_VSRAM_MODEM_RC1_OP_CFG_ADDR 0x1DB2 +#define MT6363_RG_LDO_VSRAM_MODEM_RC2_OP_CFG_ADDR 0x1DB2 +#define MT6363_RG_LDO_VSRAM_MODEM_RC3_OP_CFG_ADDR 0x1DB2 +#define MT6363_RG_LDO_VSRAM_MODEM_RC4_OP_CFG_ADDR 0x1DB2 +#define MT6363_RG_LDO_VSRAM_MODEM_RC5_OP_CFG_ADDR 0x1DB2 +#define MT6363_RG_LDO_VSRAM_MODEM_RC6_OP_CFG_ADDR 0x1DB2 +#define MT6363_RG_LDO_VSRAM_MODEM_RC7_OP_CFG_ADDR 0x1DB2 +#define MT6363_RG_LDO_VSRAM_MODEM_RC8_OP_CFG_ADDR 0x1DB3 +#define MT6363_RG_LDO_VSRAM_MODEM_RC9_OP_CFG_ADDR 0x1DB3 +#define MT6363_RG_LDO_VSRAM_MODEM_RC10_OP_CFG_ADDR 0x1DB3 +#define MT6363_RG_LDO_VSRAM_MODEM_RC11_OP_CFG_ADDR 0x1DB3 +#define MT6363_RG_LDO_VSRAM_MODEM_RC12_OP_CFG_ADDR 0x1DB3 +#define MT6363_RG_LDO_VSRAM_MODEM_RC13_OP_CFG_ADDR 0x1DB3 +#define MT6363_RG_LDO_VSRAM_MODEM_HW0_OP_CFG_ADDR 0x1DB4 +#define MT6363_RG_LDO_VSRAM_MODEM_HW1_OP_CFG_ADDR 0x1DB4 +#define MT6363_RG_LDO_VSRAM_MODEM_HW2_OP_CFG_ADDR 0x1DB4 +#define MT6363_RG_LDO_VSRAM_MODEM_HW3_OP_CFG_ADDR 0x1DB4 +#define MT6363_RG_LDO_VSRAM_MODEM_HW4_OP_CFG_ADDR 0x1DB4 +#define MT6363_RG_LDO_VSRAM_MODEM_HW5_OP_CFG_ADDR 0x1DB4 +#define MT6363_RG_LDO_VSRAM_MODEM_HW6_OP_CFG_ADDR 0x1DB4 +#define MT6363_RG_LDO_VSRAM_MODEM_SW_OP_CFG_ADDR 0x1DB4 +#define MT6363_RG_LDO_VSRAM_MODEM_RC0_OP_MODE_ADDR 0x1DB5 +#define MT6363_RG_LDO_VSRAM_MODEM_RC1_OP_MODE_ADDR 0x1DB5 +#define MT6363_RG_LDO_VSRAM_MODEM_RC2_OP_MODE_ADDR 0x1DB5 +#define MT6363_RG_LDO_VSRAM_MODEM_RC3_OP_MODE_ADDR 0x1DB5 +#define MT6363_RG_LDO_VSRAM_MODEM_RC4_OP_MODE_ADDR 0x1DB5 +#define MT6363_RG_LDO_VSRAM_MODEM_RC5_OP_MODE_ADDR 0x1DB5 +#define MT6363_RG_LDO_VSRAM_MODEM_RC6_OP_MODE_ADDR 0x1DB5 +#define MT6363_RG_LDO_VSRAM_MODEM_RC7_OP_MODE_ADDR 0x1DB5 +#define MT6363_RG_LDO_VSRAM_MODEM_RC8_OP_MODE_ADDR 0x1DB6 +#define MT6363_RG_LDO_VSRAM_MODEM_RC9_OP_MODE_ADDR 0x1DB6 +#define MT6363_RG_LDO_VSRAM_MODEM_RC10_OP_MODE_ADDR 0x1DB6 +#define MT6363_RG_LDO_VSRAM_MODEM_RC11_OP_MODE_ADDR 0x1DB6 +#define MT6363_RG_LDO_VSRAM_MODEM_RC12_OP_MODE_ADDR 0x1DB6 +#define MT6363_RG_LDO_VSRAM_MODEM_RC13_OP_MODE_ADDR 0x1DB6 +#define MT6363_RG_LDO_VSRAM_MODEM_HW0_OP_MODE_ADDR 0x1DB7 +#define MT6363_RG_LDO_VSRAM_MODEM_HW1_OP_MODE_ADDR 0x1DB7 +#define MT6363_RG_LDO_VSRAM_MODEM_HW2_OP_MODE_ADDR 0x1DB7 +#define MT6363_RG_LDO_VSRAM_MODEM_HW3_OP_MODE_ADDR 0x1DB7 +#define MT6363_RG_LDO_VSRAM_MODEM_HW4_OP_MODE_ADDR 0x1DB7 +#define MT6363_RG_LDO_VSRAM_MODEM_HW5_OP_MODE_ADDR 0x1DB7 +#define MT6363_RG_LDO_VSRAM_MODEM_HW6_OP_MODE_ADDR 0x1DB7 +#define MT6363_RG_LDO_VSRAM_CPUB_ONLV_EN_ADDR 0x1E08 +#define MT6363_RG_LDO_VSRAM_CPUB_ONLV_EN_SHIFT 3 +#define MT6363_RG_LDO_VSRAM_CPUB_VOSEL_SLEEP_ADDR 0x1E0D +#define MT6363_RG_LDO_VSRAM_CPUB_RC0_OP_EN_ADDR 0x1E14 +#define MT6363_RG_LDO_VSRAM_CPUB_RC1_OP_EN_ADDR 0x1E14 +#define MT6363_RG_LDO_VSRAM_CPUB_RC2_OP_EN_ADDR 0x1E14 +#define MT6363_RG_LDO_VSRAM_CPUB_RC3_OP_EN_ADDR 0x1E14 +#define MT6363_RG_LDO_VSRAM_CPUB_RC4_OP_EN_ADDR 0x1E14 +#define MT6363_RG_LDO_VSRAM_CPUB_RC5_OP_EN_ADDR 0x1E14 +#define MT6363_RG_LDO_VSRAM_CPUB_RC6_OP_EN_ADDR 0x1E14 +#define MT6363_RG_LDO_VSRAM_CPUB_RC7_OP_EN_ADDR 0x1E14 +#define MT6363_RG_LDO_VSRAM_CPUB_RC8_OP_EN_ADDR 0x1E15 +#define MT6363_RG_LDO_VSRAM_CPUB_RC9_OP_EN_ADDR 0x1E15 +#define MT6363_RG_LDO_VSRAM_CPUB_RC10_OP_EN_ADDR 0x1E15 +#define MT6363_RG_LDO_VSRAM_CPUB_RC11_OP_EN_ADDR 0x1E15 +#define MT6363_RG_LDO_VSRAM_CPUB_RC12_OP_EN_ADDR 0x1E15 +#define MT6363_RG_LDO_VSRAM_CPUB_RC13_OP_EN_ADDR 0x1E15 +#define MT6363_RG_LDO_VSRAM_CPUB_HW0_OP_EN_ADDR 0x1E16 +#define MT6363_RG_LDO_VSRAM_CPUB_HW1_OP_EN_ADDR 0x1E16 +#define MT6363_RG_LDO_VSRAM_CPUB_HW2_OP_EN_ADDR 0x1E16 +#define MT6363_RG_LDO_VSRAM_CPUB_HW3_OP_EN_ADDR 0x1E16 +#define MT6363_RG_LDO_VSRAM_CPUB_HW4_OP_EN_ADDR 0x1E16 +#define MT6363_RG_LDO_VSRAM_CPUB_HW5_OP_EN_ADDR 0x1E16 +#define MT6363_RG_LDO_VSRAM_CPUB_HW6_OP_EN_ADDR 0x1E16 +#define MT6363_RG_LDO_VSRAM_CPUB_SW_OP_EN_ADDR 0x1E16 +#define MT6363_RG_LDO_VSRAM_CPUB_RC0_OP_CFG_ADDR 0x1E17 +#define MT6363_RG_LDO_VSRAM_CPUB_RC1_OP_CFG_ADDR 0x1E17 +#define MT6363_RG_LDO_VSRAM_CPUB_RC2_OP_CFG_ADDR 0x1E17 +#define MT6363_RG_LDO_VSRAM_CPUB_RC3_OP_CFG_ADDR 0x1E17 +#define MT6363_RG_LDO_VSRAM_CPUB_RC4_OP_CFG_ADDR 0x1E17 +#define MT6363_RG_LDO_VSRAM_CPUB_RC5_OP_CFG_ADDR 0x1E17 +#define MT6363_RG_LDO_VSRAM_CPUB_RC6_OP_CFG_ADDR 0x1E17 +#define MT6363_RG_LDO_VSRAM_CPUB_RC7_OP_CFG_ADDR 0x1E17 +#define MT6363_RG_LDO_VSRAM_CPUB_RC8_OP_CFG_ADDR 0x1E18 +#define MT6363_RG_LDO_VSRAM_CPUB_RC9_OP_CFG_ADDR 0x1E18 +#define MT6363_RG_LDO_VSRAM_CPUB_RC10_OP_CFG_ADDR 0x1E18 +#define MT6363_RG_LDO_VSRAM_CPUB_RC11_OP_CFG_ADDR 0x1E18 +#define MT6363_RG_LDO_VSRAM_CPUB_RC12_OP_CFG_ADDR 0x1E18 +#define MT6363_RG_LDO_VSRAM_CPUB_RC13_OP_CFG_ADDR 0x1E18 +#define MT6363_RG_LDO_VSRAM_CPUB_HW0_OP_CFG_ADDR 0x1E19 +#define MT6363_RG_LDO_VSRAM_CPUB_HW1_OP_CFG_ADDR 0x1E19 +#define MT6363_RG_LDO_VSRAM_CPUB_HW2_OP_CFG_ADDR 0x1E19 +#define MT6363_RG_LDO_VSRAM_CPUB_HW3_OP_CFG_ADDR 0x1E19 +#define MT6363_RG_LDO_VSRAM_CPUB_HW4_OP_CFG_ADDR 0x1E19 +#define MT6363_RG_LDO_VSRAM_CPUB_HW5_OP_CFG_ADDR 0x1E19 +#define MT6363_RG_LDO_VSRAM_CPUB_HW6_OP_CFG_ADDR 0x1E19 +#define MT6363_RG_LDO_VSRAM_CPUB_SW_OP_CFG_ADDR 0x1E19 +#define MT6363_RG_LDO_VSRAM_CPUB_RC0_OP_MODE_ADDR 0x1E1A +#define MT6363_RG_LDO_VSRAM_CPUB_RC1_OP_MODE_ADDR 0x1E1A +#define MT6363_RG_LDO_VSRAM_CPUB_RC2_OP_MODE_ADDR 0x1E1A +#define MT6363_RG_LDO_VSRAM_CPUB_RC3_OP_MODE_ADDR 0x1E1A +#define MT6363_RG_LDO_VSRAM_CPUB_RC4_OP_MODE_ADDR 0x1E1A +#define MT6363_RG_LDO_VSRAM_CPUB_RC5_OP_MODE_ADDR 0x1E1A +#define MT6363_RG_LDO_VSRAM_CPUB_RC6_OP_MODE_ADDR 0x1E1A +#define MT6363_RG_LDO_VSRAM_CPUB_RC7_OP_MODE_ADDR 0x1E1A +#define MT6363_RG_LDO_VSRAM_CPUB_RC8_OP_MODE_ADDR 0x1E1B +#define MT6363_RG_LDO_VSRAM_CPUB_RC9_OP_MODE_ADDR 0x1E1B +#define MT6363_RG_LDO_VSRAM_CPUB_RC10_OP_MODE_ADDR 0x1E1B +#define MT6363_RG_LDO_VSRAM_CPUB_RC11_OP_MODE_ADDR 0x1E1B +#define MT6363_RG_LDO_VSRAM_CPUB_RC12_OP_MODE_ADDR 0x1E1B +#define MT6363_RG_LDO_VSRAM_CPUB_RC13_OP_MODE_ADDR 0x1E1B +#define MT6363_RG_LDO_VSRAM_CPUB_HW0_OP_MODE_ADDR 0x1E1C +#define MT6363_RG_LDO_VSRAM_CPUB_HW1_OP_MODE_ADDR 0x1E1C +#define MT6363_RG_LDO_VSRAM_CPUB_HW2_OP_MODE_ADDR 0x1E1C +#define MT6363_RG_LDO_VSRAM_CPUB_HW3_OP_MODE_ADDR 0x1E1C +#define MT6363_RG_LDO_VSRAM_CPUB_HW4_OP_MODE_ADDR 0x1E1C +#define MT6363_RG_LDO_VSRAM_CPUB_HW5_OP_MODE_ADDR 0x1E1C +#define MT6363_RG_LDO_VSRAM_CPUB_HW6_OP_MODE_ADDR 0x1E1C +#define MT6363_RG_LDO_VSRAM_CPUM_ONLV_EN_ADDR 0x1E1E +#define MT6363_RG_LDO_VSRAM_CPUM_ONLV_EN_SHIFT 3 +#define MT6363_RG_LDO_VSRAM_CPUM_VOSEL_SLEEP_ADDR 0x1E23 +#define MT6363_RG_LDO_VSRAM_CPUM_RC0_OP_EN_ADDR 0x1E2A +#define MT6363_RG_LDO_VSRAM_CPUM_RC1_OP_EN_ADDR 0x1E2A +#define MT6363_RG_LDO_VSRAM_CPUM_RC2_OP_EN_ADDR 0x1E2A +#define MT6363_RG_LDO_VSRAM_CPUM_RC3_OP_EN_ADDR 0x1E2A +#define MT6363_RG_LDO_VSRAM_CPUM_RC4_OP_EN_ADDR 0x1E2A +#define MT6363_RG_LDO_VSRAM_CPUM_RC5_OP_EN_ADDR 0x1E2A +#define MT6363_RG_LDO_VSRAM_CPUM_RC6_OP_EN_ADDR 0x1E2A +#define MT6363_RG_LDO_VSRAM_CPUM_RC7_OP_EN_ADDR 0x1E2A +#define MT6363_RG_LDO_VSRAM_CPUM_RC8_OP_EN_ADDR 0x1E2B +#define MT6363_RG_LDO_VSRAM_CPUM_RC9_OP_EN_ADDR 0x1E2B +#define MT6363_RG_LDO_VSRAM_CPUM_RC10_OP_EN_ADDR 0x1E2B +#define MT6363_RG_LDO_VSRAM_CPUM_RC11_OP_EN_ADDR 0x1E2B +#define MT6363_RG_LDO_VSRAM_CPUM_RC12_OP_EN_ADDR 0x1E2B +#define MT6363_RG_LDO_VSRAM_CPUM_RC13_OP_EN_ADDR 0x1E2B +#define MT6363_RG_LDO_VSRAM_CPUM_HW0_OP_EN_ADDR 0x1E2C +#define MT6363_RG_LDO_VSRAM_CPUM_HW1_OP_EN_ADDR 0x1E2C +#define MT6363_RG_LDO_VSRAM_CPUM_HW2_OP_EN_ADDR 0x1E2C +#define MT6363_RG_LDO_VSRAM_CPUM_HW3_OP_EN_ADDR 0x1E2C +#define MT6363_RG_LDO_VSRAM_CPUM_HW4_OP_EN_ADDR 0x1E2C +#define MT6363_RG_LDO_VSRAM_CPUM_HW5_OP_EN_ADDR 0x1E2C +#define MT6363_RG_LDO_VSRAM_CPUM_HW6_OP_EN_ADDR 0x1E2C +#define MT6363_RG_LDO_VSRAM_CPUM_SW_OP_EN_ADDR 0x1E2C +#define MT6363_RG_LDO_VSRAM_CPUM_RC0_OP_CFG_ADDR 0x1E2D +#define MT6363_RG_LDO_VSRAM_CPUM_RC1_OP_CFG_ADDR 0x1E2D +#define MT6363_RG_LDO_VSRAM_CPUM_RC2_OP_CFG_ADDR 0x1E2D +#define MT6363_RG_LDO_VSRAM_CPUM_RC3_OP_CFG_ADDR 0x1E2D +#define MT6363_RG_LDO_VSRAM_CPUM_RC4_OP_CFG_ADDR 0x1E2D +#define MT6363_RG_LDO_VSRAM_CPUM_RC5_OP_CFG_ADDR 0x1E2D +#define MT6363_RG_LDO_VSRAM_CPUM_RC6_OP_CFG_ADDR 0x1E2D +#define MT6363_RG_LDO_VSRAM_CPUM_RC7_OP_CFG_ADDR 0x1E2D +#define MT6363_RG_LDO_VSRAM_CPUM_RC8_OP_CFG_ADDR 0x1E2E +#define MT6363_RG_LDO_VSRAM_CPUM_RC9_OP_CFG_ADDR 0x1E2E +#define MT6363_RG_LDO_VSRAM_CPUM_RC10_OP_CFG_ADDR 0x1E2E +#define MT6363_RG_LDO_VSRAM_CPUM_RC11_OP_CFG_ADDR 0x1E2E +#define MT6363_RG_LDO_VSRAM_CPUM_RC12_OP_CFG_ADDR 0x1E2E +#define MT6363_RG_LDO_VSRAM_CPUM_RC13_OP_CFG_ADDR 0x1E2E +#define MT6363_RG_LDO_VSRAM_CPUM_HW0_OP_CFG_ADDR 0x1E2F +#define MT6363_RG_LDO_VSRAM_CPUM_HW1_OP_CFG_ADDR 0x1E2F +#define MT6363_RG_LDO_VSRAM_CPUM_HW2_OP_CFG_ADDR 0x1E2F +#define MT6363_RG_LDO_VSRAM_CPUM_HW3_OP_CFG_ADDR 0x1E2F +#define MT6363_RG_LDO_VSRAM_CPUM_HW4_OP_CFG_ADDR 0x1E2F +#define MT6363_RG_LDO_VSRAM_CPUM_HW5_OP_CFG_ADDR 0x1E2F +#define MT6363_RG_LDO_VSRAM_CPUM_HW6_OP_CFG_ADDR 0x1E2F +#define MT6363_RG_LDO_VSRAM_CPUM_SW_OP_CFG_ADDR 0x1E2F +#define MT6363_RG_LDO_VSRAM_CPUM_RC0_OP_MODE_ADDR 0x1E30 +#define MT6363_RG_LDO_VSRAM_CPUM_RC1_OP_MODE_ADDR 0x1E30 +#define MT6363_RG_LDO_VSRAM_CPUM_RC2_OP_MODE_ADDR 0x1E30 +#define MT6363_RG_LDO_VSRAM_CPUM_RC3_OP_MODE_ADDR 0x1E30 +#define MT6363_RG_LDO_VSRAM_CPUM_RC4_OP_MODE_ADDR 0x1E30 +#define MT6363_RG_LDO_VSRAM_CPUM_RC5_OP_MODE_ADDR 0x1E30 +#define MT6363_RG_LDO_VSRAM_CPUM_RC6_OP_MODE_ADDR 0x1E30 +#define MT6363_RG_LDO_VSRAM_CPUM_RC7_OP_MODE_ADDR 0x1E30 +#define MT6363_RG_LDO_VSRAM_CPUM_RC8_OP_MODE_ADDR 0x1E31 +#define MT6363_RG_LDO_VSRAM_CPUM_RC9_OP_MODE_ADDR 0x1E31 +#define MT6363_RG_LDO_VSRAM_CPUM_RC10_OP_MODE_ADDR 0x1E31 +#define MT6363_RG_LDO_VSRAM_CPUM_RC11_OP_MODE_ADDR 0x1E31 +#define MT6363_RG_LDO_VSRAM_CPUM_RC12_OP_MODE_ADDR 0x1E31 +#define MT6363_RG_LDO_VSRAM_CPUM_RC13_OP_MODE_ADDR 0x1E31 +#define MT6363_RG_LDO_VSRAM_CPUM_HW0_OP_MODE_ADDR 0x1E32 +#define MT6363_RG_LDO_VSRAM_CPUM_HW1_OP_MODE_ADDR 0x1E32 +#define MT6363_RG_LDO_VSRAM_CPUM_HW2_OP_MODE_ADDR 0x1E32 +#define MT6363_RG_LDO_VSRAM_CPUM_HW3_OP_MODE_ADDR 0x1E32 +#define MT6363_RG_LDO_VSRAM_CPUM_HW4_OP_MODE_ADDR 0x1E32 +#define MT6363_RG_LDO_VSRAM_CPUM_HW5_OP_MODE_ADDR 0x1E32 +#define MT6363_RG_LDO_VSRAM_CPUM_HW6_OP_MODE_ADDR 0x1E32 +#define MT6363_RG_LDO_VSRAM_CPUL_ONLV_EN_ADDR 0x1E88 +#define MT6363_RG_LDO_VSRAM_CPUL_ONLV_EN_SHIFT 3 +#define MT6363_RG_LDO_VSRAM_CPUL_VOSEL_SLEEP_ADDR 0x1E8D +#define MT6363_RG_LDO_VSRAM_CPUL_RC0_OP_EN_ADDR 0x1E94 +#define MT6363_RG_LDO_VSRAM_CPUL_RC1_OP_EN_ADDR 0x1E94 +#define MT6363_RG_LDO_VSRAM_CPUL_RC2_OP_EN_ADDR 0x1E94 +#define MT6363_RG_LDO_VSRAM_CPUL_RC3_OP_EN_ADDR 0x1E94 +#define MT6363_RG_LDO_VSRAM_CPUL_RC4_OP_EN_ADDR 0x1E94 +#define MT6363_RG_LDO_VSRAM_CPUL_RC5_OP_EN_ADDR 0x1E94 +#define MT6363_RG_LDO_VSRAM_CPUL_RC6_OP_EN_ADDR 0x1E94 +#define MT6363_RG_LDO_VSRAM_CPUL_RC7_OP_EN_ADDR 0x1E94 +#define MT6363_RG_LDO_VSRAM_CPUL_RC8_OP_EN_ADDR 0x1E95 +#define MT6363_RG_LDO_VSRAM_CPUL_RC9_OP_EN_ADDR 0x1E95 +#define MT6363_RG_LDO_VSRAM_CPUL_RC10_OP_EN_ADDR 0x1E95 +#define MT6363_RG_LDO_VSRAM_CPUL_RC11_OP_EN_ADDR 0x1E95 +#define MT6363_RG_LDO_VSRAM_CPUL_RC12_OP_EN_ADDR 0x1E95 +#define MT6363_RG_LDO_VSRAM_CPUL_RC13_OP_EN_ADDR 0x1E95 +#define MT6363_RG_LDO_VSRAM_CPUL_HW0_OP_EN_ADDR 0x1E96 +#define MT6363_RG_LDO_VSRAM_CPUL_HW1_OP_EN_ADDR 0x1E96 +#define MT6363_RG_LDO_VSRAM_CPUL_HW2_OP_EN_ADDR 0x1E96 +#define MT6363_RG_LDO_VSRAM_CPUL_HW3_OP_EN_ADDR 0x1E96 +#define MT6363_RG_LDO_VSRAM_CPUL_HW4_OP_EN_ADDR 0x1E96 +#define MT6363_RG_LDO_VSRAM_CPUL_HW5_OP_EN_ADDR 0x1E96 +#define MT6363_RG_LDO_VSRAM_CPUL_HW6_OP_EN_ADDR 0x1E96 +#define MT6363_RG_LDO_VSRAM_CPUL_SW_OP_EN_ADDR 0x1E96 +#define MT6363_RG_LDO_VSRAM_CPUL_RC0_OP_CFG_ADDR 0x1E97 +#define MT6363_RG_LDO_VSRAM_CPUL_RC1_OP_CFG_ADDR 0x1E97 +#define MT6363_RG_LDO_VSRAM_CPUL_RC2_OP_CFG_ADDR 0x1E97 +#define MT6363_RG_LDO_VSRAM_CPUL_RC3_OP_CFG_ADDR 0x1E97 +#define MT6363_RG_LDO_VSRAM_CPUL_RC4_OP_CFG_ADDR 0x1E97 +#define MT6363_RG_LDO_VSRAM_CPUL_RC5_OP_CFG_ADDR 0x1E97 +#define MT6363_RG_LDO_VSRAM_CPUL_RC6_OP_CFG_ADDR 0x1E97 +#define MT6363_RG_LDO_VSRAM_CPUL_RC7_OP_CFG_ADDR 0x1E97 +#define MT6363_RG_LDO_VSRAM_CPUL_RC8_OP_CFG_ADDR 0x1E98 +#define MT6363_RG_LDO_VSRAM_CPUL_RC9_OP_CFG_ADDR 0x1E98 +#define MT6363_RG_LDO_VSRAM_CPUL_RC10_OP_CFG_ADDR 0x1E98 +#define MT6363_RG_LDO_VSRAM_CPUL_RC11_OP_CFG_ADDR 0x1E98 +#define MT6363_RG_LDO_VSRAM_CPUL_RC12_OP_CFG_ADDR 0x1E98 +#define MT6363_RG_LDO_VSRAM_CPUL_RC13_OP_CFG_ADDR 0x1E98 +#define MT6363_RG_LDO_VSRAM_CPUL_HW0_OP_CFG_ADDR 0x1E99 +#define MT6363_RG_LDO_VSRAM_CPUL_HW1_OP_CFG_ADDR 0x1E99 +#define MT6363_RG_LDO_VSRAM_CPUL_HW2_OP_CFG_ADDR 0x1E99 +#define MT6363_RG_LDO_VSRAM_CPUL_HW3_OP_CFG_ADDR 0x1E99 +#define MT6363_RG_LDO_VSRAM_CPUL_HW4_OP_CFG_ADDR 0x1E99 +#define MT6363_RG_LDO_VSRAM_CPUL_HW5_OP_CFG_ADDR 0x1E99 +#define MT6363_RG_LDO_VSRAM_CPUL_HW6_OP_CFG_ADDR 0x1E99 +#define MT6363_RG_LDO_VSRAM_CPUL_SW_OP_CFG_ADDR 0x1E99 +#define MT6363_RG_LDO_VSRAM_CPUL_RC0_OP_MODE_ADDR 0x1E9A +#define MT6363_RG_LDO_VSRAM_CPUL_RC1_OP_MODE_ADDR 0x1E9A +#define MT6363_RG_LDO_VSRAM_CPUL_RC2_OP_MODE_ADDR 0x1E9A +#define MT6363_RG_LDO_VSRAM_CPUL_RC3_OP_MODE_ADDR 0x1E9A +#define MT6363_RG_LDO_VSRAM_CPUL_RC4_OP_MODE_ADDR 0x1E9A +#define MT6363_RG_LDO_VSRAM_CPUL_RC5_OP_MODE_ADDR 0x1E9A +#define MT6363_RG_LDO_VSRAM_CPUL_RC6_OP_MODE_ADDR 0x1E9A +#define MT6363_RG_LDO_VSRAM_CPUL_RC7_OP_MODE_ADDR 0x1E9A +#define MT6363_RG_LDO_VSRAM_CPUL_RC8_OP_MODE_ADDR 0x1E9B +#define MT6363_RG_LDO_VSRAM_CPUL_RC9_OP_MODE_ADDR 0x1E9B +#define MT6363_RG_LDO_VSRAM_CPUL_RC10_OP_MODE_ADDR 0x1E9B +#define MT6363_RG_LDO_VSRAM_CPUL_RC11_OP_MODE_ADDR 0x1E9B +#define MT6363_RG_LDO_VSRAM_CPUL_RC12_OP_MODE_ADDR 0x1E9B +#define MT6363_RG_LDO_VSRAM_CPUL_RC13_OP_MODE_ADDR 0x1E9B +#define MT6363_RG_LDO_VSRAM_CPUL_HW0_OP_MODE_ADDR 0x1E9C +#define MT6363_RG_LDO_VSRAM_CPUL_HW1_OP_MODE_ADDR 0x1E9C +#define MT6363_RG_LDO_VSRAM_CPUL_HW2_OP_MODE_ADDR 0x1E9C +#define MT6363_RG_LDO_VSRAM_CPUL_HW3_OP_MODE_ADDR 0x1E9C +#define MT6363_RG_LDO_VSRAM_CPUL_HW4_OP_MODE_ADDR 0x1E9C +#define MT6363_RG_LDO_VSRAM_CPUL_HW5_OP_MODE_ADDR 0x1E9C +#define MT6363_RG_LDO_VSRAM_CPUL_HW6_OP_MODE_ADDR 0x1E9C +#define MT6363_RG_LDO_VSRAM_APU_ONLV_EN_ADDR 0x1E9E +#define MT6363_RG_LDO_VSRAM_APU_ONLV_EN_SHIFT 3 +#define MT6363_RG_LDO_VSRAM_APU_VOSEL_SLEEP_ADDR 0x1EA3 +#define MT6363_RG_LDO_VSRAM_APU_RC0_OP_EN_ADDR 0x1EAA +#define MT6363_RG_LDO_VSRAM_APU_RC1_OP_EN_ADDR 0x1EAA +#define MT6363_RG_LDO_VSRAM_APU_RC2_OP_EN_ADDR 0x1EAA +#define MT6363_RG_LDO_VSRAM_APU_RC3_OP_EN_ADDR 0x1EAA +#define MT6363_RG_LDO_VSRAM_APU_RC4_OP_EN_ADDR 0x1EAA +#define MT6363_RG_LDO_VSRAM_APU_RC5_OP_EN_ADDR 0x1EAA +#define MT6363_RG_LDO_VSRAM_APU_RC6_OP_EN_ADDR 0x1EAA +#define MT6363_RG_LDO_VSRAM_APU_RC7_OP_EN_ADDR 0x1EAA +#define MT6363_RG_LDO_VSRAM_APU_RC8_OP_EN_ADDR 0x1EAB +#define MT6363_RG_LDO_VSRAM_APU_RC9_OP_EN_ADDR 0x1EAB +#define MT6363_RG_LDO_VSRAM_APU_RC10_OP_EN_ADDR 0x1EAB +#define MT6363_RG_LDO_VSRAM_APU_RC11_OP_EN_ADDR 0x1EAB +#define MT6363_RG_LDO_VSRAM_APU_RC12_OP_EN_ADDR 0x1EAB +#define MT6363_RG_LDO_VSRAM_APU_RC13_OP_EN_ADDR 0x1EAB +#define MT6363_RG_LDO_VSRAM_APU_HW0_OP_EN_ADDR 0x1EAC +#define MT6363_RG_LDO_VSRAM_APU_HW1_OP_EN_ADDR 0x1EAC +#define MT6363_RG_LDO_VSRAM_APU_HW2_OP_EN_ADDR 0x1EAC +#define MT6363_RG_LDO_VSRAM_APU_HW3_OP_EN_ADDR 0x1EAC +#define MT6363_RG_LDO_VSRAM_APU_HW4_OP_EN_ADDR 0x1EAC +#define MT6363_RG_LDO_VSRAM_APU_HW5_OP_EN_ADDR 0x1EAC +#define MT6363_RG_LDO_VSRAM_APU_HW6_OP_EN_ADDR 0x1EAC +#define MT6363_RG_LDO_VSRAM_APU_SW_OP_EN_ADDR 0x1EAC +#define MT6363_RG_LDO_VSRAM_APU_RC0_OP_CFG_ADDR 0x1EAD +#define MT6363_RG_LDO_VSRAM_APU_RC1_OP_CFG_ADDR 0x1EAD +#define MT6363_RG_LDO_VSRAM_APU_RC2_OP_CFG_ADDR 0x1EAD +#define MT6363_RG_LDO_VSRAM_APU_RC3_OP_CFG_ADDR 0x1EAD +#define MT6363_RG_LDO_VSRAM_APU_RC4_OP_CFG_ADDR 0x1EAD +#define MT6363_RG_LDO_VSRAM_APU_RC5_OP_CFG_ADDR 0x1EAD +#define MT6363_RG_LDO_VSRAM_APU_RC6_OP_CFG_ADDR 0x1EAD +#define MT6363_RG_LDO_VSRAM_APU_RC7_OP_CFG_ADDR 0x1EAD +#define MT6363_RG_LDO_VSRAM_APU_RC8_OP_CFG_ADDR 0x1EAE +#define MT6363_RG_LDO_VSRAM_APU_RC9_OP_CFG_ADDR 0x1EAE +#define MT6363_RG_LDO_VSRAM_APU_RC10_OP_CFG_ADDR 0x1EAE +#define MT6363_RG_LDO_VSRAM_APU_RC11_OP_CFG_ADDR 0x1EAE +#define MT6363_RG_LDO_VSRAM_APU_RC12_OP_CFG_ADDR 0x1EAE +#define MT6363_RG_LDO_VSRAM_APU_RC13_OP_CFG_ADDR 0x1EAE +#define MT6363_RG_LDO_VSRAM_APU_HW0_OP_CFG_ADDR 0x1EAF +#define MT6363_RG_LDO_VSRAM_APU_HW1_OP_CFG_ADDR 0x1EAF +#define MT6363_RG_LDO_VSRAM_APU_HW2_OP_CFG_ADDR 0x1EAF +#define MT6363_RG_LDO_VSRAM_APU_HW3_OP_CFG_ADDR 0x1EAF +#define MT6363_RG_LDO_VSRAM_APU_HW4_OP_CFG_ADDR 0x1EAF +#define MT6363_RG_LDO_VSRAM_APU_HW5_OP_CFG_ADDR 0x1EAF +#define MT6363_RG_LDO_VSRAM_APU_HW6_OP_CFG_ADDR 0x1EAF +#define MT6363_RG_LDO_VSRAM_APU_SW_OP_CFG_ADDR 0x1EAF +#define MT6363_RG_LDO_VSRAM_APU_RC0_OP_MODE_ADDR 0x1EB0 +#define MT6363_RG_LDO_VSRAM_APU_RC1_OP_MODE_ADDR 0x1EB0 +#define MT6363_RG_LDO_VSRAM_APU_RC2_OP_MODE_ADDR 0x1EB0 +#define MT6363_RG_LDO_VSRAM_APU_RC3_OP_MODE_ADDR 0x1EB0 +#define MT6363_RG_LDO_VSRAM_APU_RC4_OP_MODE_ADDR 0x1EB0 +#define MT6363_RG_LDO_VSRAM_APU_RC5_OP_MODE_ADDR 0x1EB0 +#define MT6363_RG_LDO_VSRAM_APU_RC6_OP_MODE_ADDR 0x1EB0 +#define MT6363_RG_LDO_VSRAM_APU_RC7_OP_MODE_ADDR 0x1EB0 +#define MT6363_RG_LDO_VSRAM_APU_RC8_OP_MODE_ADDR 0x1EB1 +#define MT6363_RG_LDO_VSRAM_APU_RC9_OP_MODE_ADDR 0x1EB1 +#define MT6363_RG_LDO_VSRAM_APU_RC10_OP_MODE_ADDR 0x1EB1 +#define MT6363_RG_LDO_VSRAM_APU_RC11_OP_MODE_ADDR 0x1EB1 +#define MT6363_RG_LDO_VSRAM_APU_RC12_OP_MODE_ADDR 0x1EB1 +#define MT6363_RG_LDO_VSRAM_APU_RC13_OP_MODE_ADDR 0x1EB1 +#define MT6363_RG_LDO_VSRAM_APU_HW0_OP_MODE_ADDR 0x1EB2 +#define MT6363_RG_LDO_VSRAM_APU_HW1_OP_MODE_ADDR 0x1EB2 +#define MT6363_RG_LDO_VSRAM_APU_HW2_OP_MODE_ADDR 0x1EB2 +#define MT6363_RG_LDO_VSRAM_APU_HW3_OP_MODE_ADDR 0x1EB2 +#define MT6363_RG_LDO_VSRAM_APU_HW4_OP_MODE_ADDR 0x1EB2 +#define MT6363_RG_LDO_VSRAM_APU_HW5_OP_MODE_ADDR 0x1EB2 +#define MT6363_RG_LDO_VSRAM_APU_HW6_OP_MODE_ADDR 0x1EB2 +#define MT6363_RG_BUCK_VS1_VOTER_EN_LO_BIT0_ADDR 0x189A +#define MT6363_RG_BUCK_VS1_VOTER_EN_LO_BIT1_ADDR 0x189A +#define MT6363_RG_BUCK_VS1_VOTER_EN_LO_BIT2_ADDR 0x189A +#define MT6363_RG_BUCK_VS1_VOTER_EN_LO_BIT3_ADDR 0x189A +#define MT6363_RG_BUCK_VS1_VOTER_EN_LO_BIT4_ADDR 0x189A +#define MT6363_RG_BUCK_VS1_VOTER_EN_LO_BIT5_ADDR 0x189A +#define MT6363_RG_BUCK_VS1_VOTER_EN_LO_BIT6_ADDR 0x189A +#define MT6363_RG_BUCK_VS1_VOTER_EN_LO_BIT7_ADDR 0x189A +#define MT6363_RG_BUCK_VS1_VOTER_EN_HI_BIT0_ADDR 0x189D +#define MT6363_RG_BUCK_VS1_VOTER_EN_HI_BIT1_ADDR 0x189D +#define MT6363_RG_BUCK_VS1_VOTER_EN_HI_BIT2_ADDR 0x189D +#define MT6363_RG_BUCK_VS1_VOTER_EN_HI_BIT3_ADDR 0x189D +#define MT6363_RG_BUCK_VS2_VOTER_EN_LO_BIT0_ADDR 0x149A +#define MT6363_RG_BUCK_VS2_VOTER_EN_LO_BIT1_ADDR 0x149A +#define MT6363_RG_BUCK_VS2_VOTER_EN_LO_BIT2_ADDR 0x149A +#define MT6363_RG_BUCK_VS2_VOTER_EN_LO_BIT3_ADDR 0x149A +#define MT6363_RG_BUCK_VS2_VOTER_EN_LO_BIT4_ADDR 0x149A +#define MT6363_RG_BUCK_VS2_VOTER_EN_LO_BIT5_ADDR 0x149A +#define MT6363_RG_BUCK_VS2_VOTER_EN_LO_BIT6_ADDR 0x149A +#define MT6363_RG_BUCK_VS2_VOTER_EN_LO_BIT7_ADDR 0x149A +#define MT6363_RG_BUCK_VS2_VOTER_EN_HI_BIT0_ADDR 0x149D +#define MT6363_RG_BUCK_VS2_VOTER_EN_HI_BIT1_ADDR 0x149D +#define MT6363_RG_BUCK_VS2_VOTER_EN_HI_BIT2_ADDR 0x149D +#define MT6363_RG_BUCK_VS2_VOTER_EN_HI_BIT3_ADDR 0x149D +#define MT6363_RG_BUCK_VS3_VOTER_EN_LO_BIT0_ADDR 0x191A +#define MT6363_RG_BUCK_VS3_VOTER_EN_LO_BIT1_ADDR 0x191A +#define MT6363_RG_BUCK_VS3_VOTER_EN_LO_BIT2_ADDR 0x191A +#define MT6363_RG_BUCK_VS3_VOTER_EN_LO_BIT3_ADDR 0x191A +#define MT6363_RG_BUCK_VS3_VOTER_EN_LO_BIT4_ADDR 0x191A +#define MT6363_RG_BUCK_VS3_VOTER_EN_LO_BIT5_ADDR 0x191A +#define MT6363_RG_BUCK_VS3_VOTER_EN_LO_BIT6_ADDR 0x191A +#define MT6363_RG_BUCK_VS3_VOTER_EN_LO_BIT7_ADDR 0x191A +#define MT6363_RG_BUCK_VS3_VOTER_EN_HI_BIT0_ADDR 0x191D +#define MT6363_RG_BUCK_VS3_VOTER_EN_HI_BIT1_ADDR 0x191D +#define MT6363_RG_BUCK_VS3_VOTER_EN_HI_BIT2_ADDR 0x191D +#define MT6363_RG_BUCK_VS3_VOTER_EN_HI_BIT3_ADDR 0x191D + +#endif /* MT6363_LOWPOWER_REG_H */ diff --git a/plat/mediatek/include/drivers/pmic/mt6373_lowpower_reg.h b/plat/mediatek/include/drivers/pmic/mt6373_lowpower_reg.h new file mode 100644 index 000000000..c729079d7 --- /dev/null +++ b/plat/mediatek/include/drivers/pmic/mt6373_lowpower_reg.h @@ -0,0 +1,2200 @@ +/* + * Copyright (c) 2025, Mediatek Inc. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT6373_LOWPOWER_REG_H +#define MT6373_LOWPOWER_REG_H + +#define MT6373_RG_BUCK_VBUCK0_VOSEL_SLEEP_ADDR 0x1487 +#define MT6373_RG_BUCK_VBUCK0_ONLV_EN_ADDR 0x1488 +#define MT6373_RG_BUCK_VBUCK0_ONLV_EN_SHIFT 4 +#define MT6373_RG_BUCK_VBUCK0_RC0_OP_EN_ADDR 0x148D +#define MT6373_RG_BUCK_VBUCK0_RC1_OP_EN_ADDR 0x148D +#define MT6373_RG_BUCK_VBUCK0_RC2_OP_EN_ADDR 0x148D +#define MT6373_RG_BUCK_VBUCK0_RC3_OP_EN_ADDR 0x148D +#define MT6373_RG_BUCK_VBUCK0_RC4_OP_EN_ADDR 0x148D +#define MT6373_RG_BUCK_VBUCK0_RC5_OP_EN_ADDR 0x148D +#define MT6373_RG_BUCK_VBUCK0_RC6_OP_EN_ADDR 0x148D +#define MT6373_RG_BUCK_VBUCK0_RC7_OP_EN_ADDR 0x148D +#define MT6373_RG_BUCK_VBUCK0_RC8_OP_EN_ADDR 0x148E +#define MT6373_RG_BUCK_VBUCK0_RC9_OP_EN_ADDR 0x148E +#define MT6373_RG_BUCK_VBUCK0_RC10_OP_EN_ADDR 0x148E +#define MT6373_RG_BUCK_VBUCK0_RC11_OP_EN_ADDR 0x148E +#define MT6373_RG_BUCK_VBUCK0_RC12_OP_EN_ADDR 0x148E +#define MT6373_RG_BUCK_VBUCK0_RC13_OP_EN_ADDR 0x148E +#define MT6373_RG_BUCK_VBUCK0_HW0_OP_EN_ADDR 0x148F +#define MT6373_RG_BUCK_VBUCK0_HW1_OP_EN_ADDR 0x148F +#define MT6373_RG_BUCK_VBUCK0_HW2_OP_EN_ADDR 0x148F +#define MT6373_RG_BUCK_VBUCK0_HW3_OP_EN_ADDR 0x148F +#define MT6373_RG_BUCK_VBUCK0_SW_OP_EN_ADDR 0x148F +#define MT6373_RG_BUCK_VBUCK0_RC0_OP_CFG_ADDR 0x1490 +#define MT6373_RG_BUCK_VBUCK0_RC1_OP_CFG_ADDR 0x1490 +#define MT6373_RG_BUCK_VBUCK0_RC2_OP_CFG_ADDR 0x1490 +#define MT6373_RG_BUCK_VBUCK0_RC3_OP_CFG_ADDR 0x1490 +#define MT6373_RG_BUCK_VBUCK0_RC4_OP_CFG_ADDR 0x1490 +#define MT6373_RG_BUCK_VBUCK0_RC5_OP_CFG_ADDR 0x1490 +#define MT6373_RG_BUCK_VBUCK0_RC6_OP_CFG_ADDR 0x1490 +#define MT6373_RG_BUCK_VBUCK0_RC7_OP_CFG_ADDR 0x1490 +#define MT6373_RG_BUCK_VBUCK0_RC8_OP_CFG_ADDR 0x1491 +#define MT6373_RG_BUCK_VBUCK0_RC9_OP_CFG_ADDR 0x1491 +#define MT6373_RG_BUCK_VBUCK0_RC10_OP_CFG_ADDR 0x1491 +#define MT6373_RG_BUCK_VBUCK0_RC11_OP_CFG_ADDR 0x1491 +#define MT6373_RG_BUCK_VBUCK0_RC12_OP_CFG_ADDR 0x1491 +#define MT6373_RG_BUCK_VBUCK0_RC13_OP_CFG_ADDR 0x1491 +#define MT6373_RG_BUCK_VBUCK0_HW0_OP_CFG_ADDR 0x1492 +#define MT6373_RG_BUCK_VBUCK0_HW1_OP_CFG_ADDR 0x1492 +#define MT6373_RG_BUCK_VBUCK0_HW2_OP_CFG_ADDR 0x1492 +#define MT6373_RG_BUCK_VBUCK0_HW3_OP_CFG_ADDR 0x1492 +#define MT6373_RG_BUCK_VBUCK0_RC0_OP_MODE_ADDR 0x1493 +#define MT6373_RG_BUCK_VBUCK0_RC1_OP_MODE_ADDR 0x1493 +#define MT6373_RG_BUCK_VBUCK0_RC2_OP_MODE_ADDR 0x1493 +#define MT6373_RG_BUCK_VBUCK0_RC3_OP_MODE_ADDR 0x1493 +#define MT6373_RG_BUCK_VBUCK0_RC4_OP_MODE_ADDR 0x1493 +#define MT6373_RG_BUCK_VBUCK0_RC5_OP_MODE_ADDR 0x1493 +#define MT6373_RG_BUCK_VBUCK0_RC6_OP_MODE_ADDR 0x1493 +#define MT6373_RG_BUCK_VBUCK0_RC7_OP_MODE_ADDR 0x1493 +#define MT6373_RG_BUCK_VBUCK0_RC8_OP_MODE_ADDR 0x1494 +#define MT6373_RG_BUCK_VBUCK0_RC9_OP_MODE_ADDR 0x1494 +#define MT6373_RG_BUCK_VBUCK0_RC10_OP_MODE_ADDR 0x1494 +#define MT6373_RG_BUCK_VBUCK0_RC11_OP_MODE_ADDR 0x1494 +#define MT6373_RG_BUCK_VBUCK0_RC12_OP_MODE_ADDR 0x1494 +#define MT6373_RG_BUCK_VBUCK0_RC13_OP_MODE_ADDR 0x1494 +#define MT6373_RG_BUCK_VBUCK0_HW0_OP_MODE_ADDR 0x1495 +#define MT6373_RG_BUCK_VBUCK0_HW1_OP_MODE_ADDR 0x1495 +#define MT6373_RG_BUCK_VBUCK0_HW2_OP_MODE_ADDR 0x1495 +#define MT6373_RG_BUCK_VBUCK0_HW3_OP_MODE_ADDR 0x1495 +#define MT6373_RG_BUCK_VBUCK1_VOSEL_SLEEP_ADDR 0x1507 +#define MT6373_RG_BUCK_VBUCK1_ONLV_EN_ADDR 0x1508 +#define MT6373_RG_BUCK_VBUCK1_ONLV_EN_SHIFT 4 +#define MT6373_RG_BUCK_VBUCK1_RC0_OP_EN_ADDR 0x150D +#define MT6373_RG_BUCK_VBUCK1_RC1_OP_EN_ADDR 0x150D +#define MT6373_RG_BUCK_VBUCK1_RC2_OP_EN_ADDR 0x150D +#define MT6373_RG_BUCK_VBUCK1_RC3_OP_EN_ADDR 0x150D +#define MT6373_RG_BUCK_VBUCK1_RC4_OP_EN_ADDR 0x150D +#define MT6373_RG_BUCK_VBUCK1_RC5_OP_EN_ADDR 0x150D +#define MT6373_RG_BUCK_VBUCK1_RC6_OP_EN_ADDR 0x150D +#define MT6373_RG_BUCK_VBUCK1_RC7_OP_EN_ADDR 0x150D +#define MT6373_RG_BUCK_VBUCK1_RC8_OP_EN_ADDR 0x150E +#define MT6373_RG_BUCK_VBUCK1_RC9_OP_EN_ADDR 0x150E +#define MT6373_RG_BUCK_VBUCK1_RC10_OP_EN_ADDR 0x150E +#define MT6373_RG_BUCK_VBUCK1_RC11_OP_EN_ADDR 0x150E +#define MT6373_RG_BUCK_VBUCK1_RC12_OP_EN_ADDR 0x150E +#define MT6373_RG_BUCK_VBUCK1_RC13_OP_EN_ADDR 0x150E +#define MT6373_RG_BUCK_VBUCK1_HW0_OP_EN_ADDR 0x150F +#define MT6373_RG_BUCK_VBUCK1_HW1_OP_EN_ADDR 0x150F +#define MT6373_RG_BUCK_VBUCK1_HW2_OP_EN_ADDR 0x150F +#define MT6373_RG_BUCK_VBUCK1_HW3_OP_EN_ADDR 0x150F +#define MT6373_RG_BUCK_VBUCK1_SW_OP_EN_ADDR 0x150F +#define MT6373_RG_BUCK_VBUCK1_RC0_OP_CFG_ADDR 0x1510 +#define MT6373_RG_BUCK_VBUCK1_RC1_OP_CFG_ADDR 0x1510 +#define MT6373_RG_BUCK_VBUCK1_RC2_OP_CFG_ADDR 0x1510 +#define MT6373_RG_BUCK_VBUCK1_RC3_OP_CFG_ADDR 0x1510 +#define MT6373_RG_BUCK_VBUCK1_RC4_OP_CFG_ADDR 0x1510 +#define MT6373_RG_BUCK_VBUCK1_RC5_OP_CFG_ADDR 0x1510 +#define MT6373_RG_BUCK_VBUCK1_RC6_OP_CFG_ADDR 0x1510 +#define MT6373_RG_BUCK_VBUCK1_RC7_OP_CFG_ADDR 0x1510 +#define MT6373_RG_BUCK_VBUCK1_RC8_OP_CFG_ADDR 0x1511 +#define MT6373_RG_BUCK_VBUCK1_RC9_OP_CFG_ADDR 0x1511 +#define MT6373_RG_BUCK_VBUCK1_RC10_OP_CFG_ADDR 0x1511 +#define MT6373_RG_BUCK_VBUCK1_RC11_OP_CFG_ADDR 0x1511 +#define MT6373_RG_BUCK_VBUCK1_RC12_OP_CFG_ADDR 0x1511 +#define MT6373_RG_BUCK_VBUCK1_RC13_OP_CFG_ADDR 0x1511 +#define MT6373_RG_BUCK_VBUCK1_HW0_OP_CFG_ADDR 0x1512 +#define MT6373_RG_BUCK_VBUCK1_HW1_OP_CFG_ADDR 0x1512 +#define MT6373_RG_BUCK_VBUCK1_HW2_OP_CFG_ADDR 0x1512 +#define MT6373_RG_BUCK_VBUCK1_HW3_OP_CFG_ADDR 0x1512 +#define MT6373_RG_BUCK_VBUCK1_RC0_OP_MODE_ADDR 0x1513 +#define MT6373_RG_BUCK_VBUCK1_RC1_OP_MODE_ADDR 0x1513 +#define MT6373_RG_BUCK_VBUCK1_RC2_OP_MODE_ADDR 0x1513 +#define MT6373_RG_BUCK_VBUCK1_RC3_OP_MODE_ADDR 0x1513 +#define MT6373_RG_BUCK_VBUCK1_RC4_OP_MODE_ADDR 0x1513 +#define MT6373_RG_BUCK_VBUCK1_RC5_OP_MODE_ADDR 0x1513 +#define MT6373_RG_BUCK_VBUCK1_RC6_OP_MODE_ADDR 0x1513 +#define MT6373_RG_BUCK_VBUCK1_RC7_OP_MODE_ADDR 0x1513 +#define MT6373_RG_BUCK_VBUCK1_RC8_OP_MODE_ADDR 0x1514 +#define MT6373_RG_BUCK_VBUCK1_RC9_OP_MODE_ADDR 0x1514 +#define MT6373_RG_BUCK_VBUCK1_RC10_OP_MODE_ADDR 0x1514 +#define MT6373_RG_BUCK_VBUCK1_RC11_OP_MODE_ADDR 0x1514 +#define MT6373_RG_BUCK_VBUCK1_RC12_OP_MODE_ADDR 0x1514 +#define MT6373_RG_BUCK_VBUCK1_RC13_OP_MODE_ADDR 0x1514 +#define MT6373_RG_BUCK_VBUCK1_HW0_OP_MODE_ADDR 0x1515 +#define MT6373_RG_BUCK_VBUCK1_HW1_OP_MODE_ADDR 0x1515 +#define MT6373_RG_BUCK_VBUCK1_HW2_OP_MODE_ADDR 0x1515 +#define MT6373_RG_BUCK_VBUCK1_HW3_OP_MODE_ADDR 0x1515 +#define MT6373_RG_BUCK_VBUCK2_VOSEL_SLEEP_ADDR 0x1587 +#define MT6373_RG_BUCK_VBUCK2_ONLV_EN_ADDR 0x1588 +#define MT6373_RG_BUCK_VBUCK2_ONLV_EN_SHIFT 4 +#define MT6373_RG_BUCK_VBUCK2_RC0_OP_EN_ADDR 0x158D +#define MT6373_RG_BUCK_VBUCK2_RC1_OP_EN_ADDR 0x158D +#define MT6373_RG_BUCK_VBUCK2_RC2_OP_EN_ADDR 0x158D +#define MT6373_RG_BUCK_VBUCK2_RC3_OP_EN_ADDR 0x158D +#define MT6373_RG_BUCK_VBUCK2_RC4_OP_EN_ADDR 0x158D +#define MT6373_RG_BUCK_VBUCK2_RC5_OP_EN_ADDR 0x158D +#define MT6373_RG_BUCK_VBUCK2_RC6_OP_EN_ADDR 0x158D +#define MT6373_RG_BUCK_VBUCK2_RC7_OP_EN_ADDR 0x158D +#define MT6373_RG_BUCK_VBUCK2_RC8_OP_EN_ADDR 0x158E +#define MT6373_RG_BUCK_VBUCK2_RC9_OP_EN_ADDR 0x158E +#define MT6373_RG_BUCK_VBUCK2_RC10_OP_EN_ADDR 0x158E +#define MT6373_RG_BUCK_VBUCK2_RC11_OP_EN_ADDR 0x158E +#define MT6373_RG_BUCK_VBUCK2_RC12_OP_EN_ADDR 0x158E +#define MT6373_RG_BUCK_VBUCK2_RC13_OP_EN_ADDR 0x158E +#define MT6373_RG_BUCK_VBUCK2_HW0_OP_EN_ADDR 0x158F +#define MT6373_RG_BUCK_VBUCK2_HW1_OP_EN_ADDR 0x158F +#define MT6373_RG_BUCK_VBUCK2_HW2_OP_EN_ADDR 0x158F +#define MT6373_RG_BUCK_VBUCK2_HW3_OP_EN_ADDR 0x158F +#define MT6373_RG_BUCK_VBUCK2_SW_OP_EN_ADDR 0x158F +#define MT6373_RG_BUCK_VBUCK2_RC0_OP_CFG_ADDR 0x1590 +#define MT6373_RG_BUCK_VBUCK2_RC1_OP_CFG_ADDR 0x1590 +#define MT6373_RG_BUCK_VBUCK2_RC2_OP_CFG_ADDR 0x1590 +#define MT6373_RG_BUCK_VBUCK2_RC3_OP_CFG_ADDR 0x1590 +#define MT6373_RG_BUCK_VBUCK2_RC4_OP_CFG_ADDR 0x1590 +#define MT6373_RG_BUCK_VBUCK2_RC5_OP_CFG_ADDR 0x1590 +#define MT6373_RG_BUCK_VBUCK2_RC6_OP_CFG_ADDR 0x1590 +#define MT6373_RG_BUCK_VBUCK2_RC7_OP_CFG_ADDR 0x1590 +#define MT6373_RG_BUCK_VBUCK2_RC8_OP_CFG_ADDR 0x1591 +#define MT6373_RG_BUCK_VBUCK2_RC9_OP_CFG_ADDR 0x1591 +#define MT6373_RG_BUCK_VBUCK2_RC10_OP_CFG_ADDR 0x1591 +#define MT6373_RG_BUCK_VBUCK2_RC11_OP_CFG_ADDR 0x1591 +#define MT6373_RG_BUCK_VBUCK2_RC12_OP_CFG_ADDR 0x1591 +#define MT6373_RG_BUCK_VBUCK2_RC13_OP_CFG_ADDR 0x1591 +#define MT6373_RG_BUCK_VBUCK2_HW0_OP_CFG_ADDR 0x1592 +#define MT6373_RG_BUCK_VBUCK2_HW1_OP_CFG_ADDR 0x1592 +#define MT6373_RG_BUCK_VBUCK2_HW2_OP_CFG_ADDR 0x1592 +#define MT6373_RG_BUCK_VBUCK2_HW3_OP_CFG_ADDR 0x1592 +#define MT6373_RG_BUCK_VBUCK2_RC0_OP_MODE_ADDR 0x1593 +#define MT6373_RG_BUCK_VBUCK2_RC1_OP_MODE_ADDR 0x1593 +#define MT6373_RG_BUCK_VBUCK2_RC2_OP_MODE_ADDR 0x1593 +#define MT6373_RG_BUCK_VBUCK2_RC3_OP_MODE_ADDR 0x1593 +#define MT6373_RG_BUCK_VBUCK2_RC4_OP_MODE_ADDR 0x1593 +#define MT6373_RG_BUCK_VBUCK2_RC5_OP_MODE_ADDR 0x1593 +#define MT6373_RG_BUCK_VBUCK2_RC6_OP_MODE_ADDR 0x1593 +#define MT6373_RG_BUCK_VBUCK2_RC7_OP_MODE_ADDR 0x1593 +#define MT6373_RG_BUCK_VBUCK2_RC8_OP_MODE_ADDR 0x1594 +#define MT6373_RG_BUCK_VBUCK2_RC9_OP_MODE_ADDR 0x1594 +#define MT6373_RG_BUCK_VBUCK2_RC10_OP_MODE_ADDR 0x1594 +#define MT6373_RG_BUCK_VBUCK2_RC11_OP_MODE_ADDR 0x1594 +#define MT6373_RG_BUCK_VBUCK2_RC12_OP_MODE_ADDR 0x1594 +#define MT6373_RG_BUCK_VBUCK2_RC13_OP_MODE_ADDR 0x1594 +#define MT6373_RG_BUCK_VBUCK2_HW0_OP_MODE_ADDR 0x1595 +#define MT6373_RG_BUCK_VBUCK2_HW1_OP_MODE_ADDR 0x1595 +#define MT6373_RG_BUCK_VBUCK2_HW2_OP_MODE_ADDR 0x1595 +#define MT6373_RG_BUCK_VBUCK2_HW3_OP_MODE_ADDR 0x1595 +#define MT6373_RG_BUCK_VBUCK3_VOSEL_SLEEP_ADDR 0x1607 +#define MT6373_RG_BUCK_VBUCK3_ONLV_EN_ADDR 0x1608 +#define MT6373_RG_BUCK_VBUCK3_ONLV_EN_SHIFT 4 +#define MT6373_RG_BUCK_VBUCK3_RC0_OP_EN_ADDR 0x160D +#define MT6373_RG_BUCK_VBUCK3_RC1_OP_EN_ADDR 0x160D +#define MT6373_RG_BUCK_VBUCK3_RC2_OP_EN_ADDR 0x160D +#define MT6373_RG_BUCK_VBUCK3_RC3_OP_EN_ADDR 0x160D +#define MT6373_RG_BUCK_VBUCK3_RC4_OP_EN_ADDR 0x160D +#define MT6373_RG_BUCK_VBUCK3_RC5_OP_EN_ADDR 0x160D +#define MT6373_RG_BUCK_VBUCK3_RC6_OP_EN_ADDR 0x160D +#define MT6373_RG_BUCK_VBUCK3_RC7_OP_EN_ADDR 0x160D +#define MT6373_RG_BUCK_VBUCK3_RC8_OP_EN_ADDR 0x160E +#define MT6373_RG_BUCK_VBUCK3_RC9_OP_EN_ADDR 0x160E +#define MT6373_RG_BUCK_VBUCK3_RC10_OP_EN_ADDR 0x160E +#define MT6373_RG_BUCK_VBUCK3_RC11_OP_EN_ADDR 0x160E +#define MT6373_RG_BUCK_VBUCK3_RC12_OP_EN_ADDR 0x160E +#define MT6373_RG_BUCK_VBUCK3_RC13_OP_EN_ADDR 0x160E +#define MT6373_RG_BUCK_VBUCK3_HW0_OP_EN_ADDR 0x160F +#define MT6373_RG_BUCK_VBUCK3_HW1_OP_EN_ADDR 0x160F +#define MT6373_RG_BUCK_VBUCK3_HW2_OP_EN_ADDR 0x160F +#define MT6373_RG_BUCK_VBUCK3_HW3_OP_EN_ADDR 0x160F +#define MT6373_RG_BUCK_VBUCK3_SW_OP_EN_ADDR 0x160F +#define MT6373_RG_BUCK_VBUCK3_RC0_OP_CFG_ADDR 0x1610 +#define MT6373_RG_BUCK_VBUCK3_RC1_OP_CFG_ADDR 0x1610 +#define MT6373_RG_BUCK_VBUCK3_RC2_OP_CFG_ADDR 0x1610 +#define MT6373_RG_BUCK_VBUCK3_RC3_OP_CFG_ADDR 0x1610 +#define MT6373_RG_BUCK_VBUCK3_RC4_OP_CFG_ADDR 0x1610 +#define MT6373_RG_BUCK_VBUCK3_RC5_OP_CFG_ADDR 0x1610 +#define MT6373_RG_BUCK_VBUCK3_RC6_OP_CFG_ADDR 0x1610 +#define MT6373_RG_BUCK_VBUCK3_RC7_OP_CFG_ADDR 0x1610 +#define MT6373_RG_BUCK_VBUCK3_RC8_OP_CFG_ADDR 0x1611 +#define MT6373_RG_BUCK_VBUCK3_RC9_OP_CFG_ADDR 0x1611 +#define MT6373_RG_BUCK_VBUCK3_RC10_OP_CFG_ADDR 0x1611 +#define MT6373_RG_BUCK_VBUCK3_RC11_OP_CFG_ADDR 0x1611 +#define MT6373_RG_BUCK_VBUCK3_RC12_OP_CFG_ADDR 0x1611 +#define MT6373_RG_BUCK_VBUCK3_RC13_OP_CFG_ADDR 0x1611 +#define MT6373_RG_BUCK_VBUCK3_HW0_OP_CFG_ADDR 0x1612 +#define MT6373_RG_BUCK_VBUCK3_HW1_OP_CFG_ADDR 0x1612 +#define MT6373_RG_BUCK_VBUCK3_HW2_OP_CFG_ADDR 0x1612 +#define MT6373_RG_BUCK_VBUCK3_HW3_OP_CFG_ADDR 0x1612 +#define MT6373_RG_BUCK_VBUCK3_RC0_OP_MODE_ADDR 0x1613 +#define MT6373_RG_BUCK_VBUCK3_RC1_OP_MODE_ADDR 0x1613 +#define MT6373_RG_BUCK_VBUCK3_RC2_OP_MODE_ADDR 0x1613 +#define MT6373_RG_BUCK_VBUCK3_RC3_OP_MODE_ADDR 0x1613 +#define MT6373_RG_BUCK_VBUCK3_RC4_OP_MODE_ADDR 0x1613 +#define MT6373_RG_BUCK_VBUCK3_RC5_OP_MODE_ADDR 0x1613 +#define MT6373_RG_BUCK_VBUCK3_RC6_OP_MODE_ADDR 0x1613 +#define MT6373_RG_BUCK_VBUCK3_RC7_OP_MODE_ADDR 0x1613 +#define MT6373_RG_BUCK_VBUCK3_RC8_OP_MODE_ADDR 0x1614 +#define MT6373_RG_BUCK_VBUCK3_RC9_OP_MODE_ADDR 0x1614 +#define MT6373_RG_BUCK_VBUCK3_RC10_OP_MODE_ADDR 0x1614 +#define MT6373_RG_BUCK_VBUCK3_RC11_OP_MODE_ADDR 0x1614 +#define MT6373_RG_BUCK_VBUCK3_RC12_OP_MODE_ADDR 0x1614 +#define MT6373_RG_BUCK_VBUCK3_RC13_OP_MODE_ADDR 0x1614 +#define MT6373_RG_BUCK_VBUCK3_HW0_OP_MODE_ADDR 0x1615 +#define MT6373_RG_BUCK_VBUCK3_HW1_OP_MODE_ADDR 0x1615 +#define MT6373_RG_BUCK_VBUCK3_HW2_OP_MODE_ADDR 0x1615 +#define MT6373_RG_BUCK_VBUCK3_HW3_OP_MODE_ADDR 0x1615 +#define MT6373_RG_BUCK_VBUCK4_VOSEL_SLEEP_ADDR 0x1687 +#define MT6373_RG_BUCK_VBUCK4_ONLV_EN_ADDR 0x1688 +#define MT6373_RG_BUCK_VBUCK4_ONLV_EN_SHIFT 4 +#define MT6373_RG_BUCK_VBUCK4_RC0_OP_EN_ADDR 0x168D +#define MT6373_RG_BUCK_VBUCK4_RC1_OP_EN_ADDR 0x168D +#define MT6373_RG_BUCK_VBUCK4_RC2_OP_EN_ADDR 0x168D +#define MT6373_RG_BUCK_VBUCK4_RC3_OP_EN_ADDR 0x168D +#define MT6373_RG_BUCK_VBUCK4_RC4_OP_EN_ADDR 0x168D +#define MT6373_RG_BUCK_VBUCK4_RC5_OP_EN_ADDR 0x168D +#define MT6373_RG_BUCK_VBUCK4_RC6_OP_EN_ADDR 0x168D +#define MT6373_RG_BUCK_VBUCK4_RC7_OP_EN_ADDR 0x168D +#define MT6373_RG_BUCK_VBUCK4_RC8_OP_EN_ADDR 0x168E +#define MT6373_RG_BUCK_VBUCK4_RC9_OP_EN_ADDR 0x168E +#define MT6373_RG_BUCK_VBUCK4_RC10_OP_EN_ADDR 0x168E +#define MT6373_RG_BUCK_VBUCK4_RC11_OP_EN_ADDR 0x168E +#define MT6373_RG_BUCK_VBUCK4_RC12_OP_EN_ADDR 0x168E +#define MT6373_RG_BUCK_VBUCK4_RC13_OP_EN_ADDR 0x168E +#define MT6373_RG_BUCK_VBUCK4_HW0_OP_EN_ADDR 0x168F +#define MT6373_RG_BUCK_VBUCK4_HW1_OP_EN_ADDR 0x168F +#define MT6373_RG_BUCK_VBUCK4_HW2_OP_EN_ADDR 0x168F +#define MT6373_RG_BUCK_VBUCK4_HW3_OP_EN_ADDR 0x168F +#define MT6373_RG_BUCK_VBUCK4_SW_OP_EN_ADDR 0x168F +#define MT6373_RG_BUCK_VBUCK4_RC0_OP_CFG_ADDR 0x1690 +#define MT6373_RG_BUCK_VBUCK4_RC1_OP_CFG_ADDR 0x1690 +#define MT6373_RG_BUCK_VBUCK4_RC2_OP_CFG_ADDR 0x1690 +#define MT6373_RG_BUCK_VBUCK4_RC3_OP_CFG_ADDR 0x1690 +#define MT6373_RG_BUCK_VBUCK4_RC4_OP_CFG_ADDR 0x1690 +#define MT6373_RG_BUCK_VBUCK4_RC5_OP_CFG_ADDR 0x1690 +#define MT6373_RG_BUCK_VBUCK4_RC6_OP_CFG_ADDR 0x1690 +#define MT6373_RG_BUCK_VBUCK4_RC7_OP_CFG_ADDR 0x1690 +#define MT6373_RG_BUCK_VBUCK4_RC8_OP_CFG_ADDR 0x1691 +#define MT6373_RG_BUCK_VBUCK4_RC9_OP_CFG_ADDR 0x1691 +#define MT6373_RG_BUCK_VBUCK4_RC10_OP_CFG_ADDR 0x1691 +#define MT6373_RG_BUCK_VBUCK4_RC11_OP_CFG_ADDR 0x1691 +#define MT6373_RG_BUCK_VBUCK4_RC12_OP_CFG_ADDR 0x1691 +#define MT6373_RG_BUCK_VBUCK4_RC13_OP_CFG_ADDR 0x1691 +#define MT6373_RG_BUCK_VBUCK4_HW0_OP_CFG_ADDR 0x1692 +#define MT6373_RG_BUCK_VBUCK4_HW1_OP_CFG_ADDR 0x1692 +#define MT6373_RG_BUCK_VBUCK4_HW2_OP_CFG_ADDR 0x1692 +#define MT6373_RG_BUCK_VBUCK4_HW3_OP_CFG_ADDR 0x1692 +#define MT6373_RG_BUCK_VBUCK4_RC0_OP_MODE_ADDR 0x1693 +#define MT6373_RG_BUCK_VBUCK4_RC1_OP_MODE_ADDR 0x1693 +#define MT6373_RG_BUCK_VBUCK4_RC2_OP_MODE_ADDR 0x1693 +#define MT6373_RG_BUCK_VBUCK4_RC3_OP_MODE_ADDR 0x1693 +#define MT6373_RG_BUCK_VBUCK4_RC4_OP_MODE_ADDR 0x1693 +#define MT6373_RG_BUCK_VBUCK4_RC5_OP_MODE_ADDR 0x1693 +#define MT6373_RG_BUCK_VBUCK4_RC6_OP_MODE_ADDR 0x1693 +#define MT6373_RG_BUCK_VBUCK4_RC7_OP_MODE_ADDR 0x1693 +#define MT6373_RG_BUCK_VBUCK4_RC8_OP_MODE_ADDR 0x1694 +#define MT6373_RG_BUCK_VBUCK4_RC9_OP_MODE_ADDR 0x1694 +#define MT6373_RG_BUCK_VBUCK4_RC10_OP_MODE_ADDR 0x1694 +#define MT6373_RG_BUCK_VBUCK4_RC11_OP_MODE_ADDR 0x1694 +#define MT6373_RG_BUCK_VBUCK4_RC12_OP_MODE_ADDR 0x1694 +#define MT6373_RG_BUCK_VBUCK4_RC13_OP_MODE_ADDR 0x1694 +#define MT6373_RG_BUCK_VBUCK4_HW0_OP_MODE_ADDR 0x1695 +#define MT6373_RG_BUCK_VBUCK4_HW1_OP_MODE_ADDR 0x1695 +#define MT6373_RG_BUCK_VBUCK4_HW2_OP_MODE_ADDR 0x1695 +#define MT6373_RG_BUCK_VBUCK4_HW3_OP_MODE_ADDR 0x1695 +#define MT6373_RG_BUCK_VBUCK5_VOSEL_SLEEP_ADDR 0x1707 +#define MT6373_RG_BUCK_VBUCK5_ONLV_EN_ADDR 0x1708 +#define MT6373_RG_BUCK_VBUCK5_ONLV_EN_SHIFT 4 +#define MT6373_RG_BUCK_VBUCK5_RC0_OP_EN_ADDR 0x170D +#define MT6373_RG_BUCK_VBUCK5_RC1_OP_EN_ADDR 0x170D +#define MT6373_RG_BUCK_VBUCK5_RC2_OP_EN_ADDR 0x170D +#define MT6373_RG_BUCK_VBUCK5_RC3_OP_EN_ADDR 0x170D +#define MT6373_RG_BUCK_VBUCK5_RC4_OP_EN_ADDR 0x170D +#define MT6373_RG_BUCK_VBUCK5_RC5_OP_EN_ADDR 0x170D +#define MT6373_RG_BUCK_VBUCK5_RC6_OP_EN_ADDR 0x170D +#define MT6373_RG_BUCK_VBUCK5_RC7_OP_EN_ADDR 0x170D +#define MT6373_RG_BUCK_VBUCK5_RC8_OP_EN_ADDR 0x170E +#define MT6373_RG_BUCK_VBUCK5_RC9_OP_EN_ADDR 0x170E +#define MT6373_RG_BUCK_VBUCK5_RC10_OP_EN_ADDR 0x170E +#define MT6373_RG_BUCK_VBUCK5_RC11_OP_EN_ADDR 0x170E +#define MT6373_RG_BUCK_VBUCK5_RC12_OP_EN_ADDR 0x170E +#define MT6373_RG_BUCK_VBUCK5_RC13_OP_EN_ADDR 0x170E +#define MT6373_RG_BUCK_VBUCK5_HW0_OP_EN_ADDR 0x170F +#define MT6373_RG_BUCK_VBUCK5_HW1_OP_EN_ADDR 0x170F +#define MT6373_RG_BUCK_VBUCK5_HW2_OP_EN_ADDR 0x170F +#define MT6373_RG_BUCK_VBUCK5_HW3_OP_EN_ADDR 0x170F +#define MT6373_RG_BUCK_VBUCK5_SW_OP_EN_ADDR 0x170F +#define MT6373_RG_BUCK_VBUCK5_RC0_OP_CFG_ADDR 0x1710 +#define MT6373_RG_BUCK_VBUCK5_RC1_OP_CFG_ADDR 0x1710 +#define MT6373_RG_BUCK_VBUCK5_RC2_OP_CFG_ADDR 0x1710 +#define MT6373_RG_BUCK_VBUCK5_RC3_OP_CFG_ADDR 0x1710 +#define MT6373_RG_BUCK_VBUCK5_RC4_OP_CFG_ADDR 0x1710 +#define MT6373_RG_BUCK_VBUCK5_RC5_OP_CFG_ADDR 0x1710 +#define MT6373_RG_BUCK_VBUCK5_RC6_OP_CFG_ADDR 0x1710 +#define MT6373_RG_BUCK_VBUCK5_RC7_OP_CFG_ADDR 0x1710 +#define MT6373_RG_BUCK_VBUCK5_RC8_OP_CFG_ADDR 0x1711 +#define MT6373_RG_BUCK_VBUCK5_RC9_OP_CFG_ADDR 0x1711 +#define MT6373_RG_BUCK_VBUCK5_RC10_OP_CFG_ADDR 0x1711 +#define MT6373_RG_BUCK_VBUCK5_RC11_OP_CFG_ADDR 0x1711 +#define MT6373_RG_BUCK_VBUCK5_RC12_OP_CFG_ADDR 0x1711 +#define MT6373_RG_BUCK_VBUCK5_RC13_OP_CFG_ADDR 0x1711 +#define MT6373_RG_BUCK_VBUCK5_HW0_OP_CFG_ADDR 0x1712 +#define MT6373_RG_BUCK_VBUCK5_HW1_OP_CFG_ADDR 0x1712 +#define MT6373_RG_BUCK_VBUCK5_HW2_OP_CFG_ADDR 0x1712 +#define MT6373_RG_BUCK_VBUCK5_HW3_OP_CFG_ADDR 0x1712 +#define MT6373_RG_BUCK_VBUCK5_RC0_OP_MODE_ADDR 0x1713 +#define MT6373_RG_BUCK_VBUCK5_RC1_OP_MODE_ADDR 0x1713 +#define MT6373_RG_BUCK_VBUCK5_RC2_OP_MODE_ADDR 0x1713 +#define MT6373_RG_BUCK_VBUCK5_RC3_OP_MODE_ADDR 0x1713 +#define MT6373_RG_BUCK_VBUCK5_RC4_OP_MODE_ADDR 0x1713 +#define MT6373_RG_BUCK_VBUCK5_RC5_OP_MODE_ADDR 0x1713 +#define MT6373_RG_BUCK_VBUCK5_RC6_OP_MODE_ADDR 0x1713 +#define MT6373_RG_BUCK_VBUCK5_RC7_OP_MODE_ADDR 0x1713 +#define MT6373_RG_BUCK_VBUCK5_RC8_OP_MODE_ADDR 0x1714 +#define MT6373_RG_BUCK_VBUCK5_RC9_OP_MODE_ADDR 0x1714 +#define MT6373_RG_BUCK_VBUCK5_RC10_OP_MODE_ADDR 0x1714 +#define MT6373_RG_BUCK_VBUCK5_RC11_OP_MODE_ADDR 0x1714 +#define MT6373_RG_BUCK_VBUCK5_RC12_OP_MODE_ADDR 0x1714 +#define MT6373_RG_BUCK_VBUCK5_RC13_OP_MODE_ADDR 0x1714 +#define MT6373_RG_BUCK_VBUCK5_HW0_OP_MODE_ADDR 0x1715 +#define MT6373_RG_BUCK_VBUCK5_HW1_OP_MODE_ADDR 0x1715 +#define MT6373_RG_BUCK_VBUCK5_HW2_OP_MODE_ADDR 0x1715 +#define MT6373_RG_BUCK_VBUCK5_HW3_OP_MODE_ADDR 0x1715 +#define MT6373_RG_BUCK_VBUCK6_VOSEL_SLEEP_ADDR 0x1787 +#define MT6373_RG_BUCK_VBUCK6_ONLV_EN_ADDR 0x1788 +#define MT6373_RG_BUCK_VBUCK6_ONLV_EN_SHIFT 4 +#define MT6373_RG_BUCK_VBUCK6_RC0_OP_EN_ADDR 0x178D +#define MT6373_RG_BUCK_VBUCK6_RC1_OP_EN_ADDR 0x178D +#define MT6373_RG_BUCK_VBUCK6_RC2_OP_EN_ADDR 0x178D +#define MT6373_RG_BUCK_VBUCK6_RC3_OP_EN_ADDR 0x178D +#define MT6373_RG_BUCK_VBUCK6_RC4_OP_EN_ADDR 0x178D +#define MT6373_RG_BUCK_VBUCK6_RC5_OP_EN_ADDR 0x178D +#define MT6373_RG_BUCK_VBUCK6_RC6_OP_EN_ADDR 0x178D +#define MT6373_RG_BUCK_VBUCK6_RC7_OP_EN_ADDR 0x178D +#define MT6373_RG_BUCK_VBUCK6_RC8_OP_EN_ADDR 0x178E +#define MT6373_RG_BUCK_VBUCK6_RC9_OP_EN_ADDR 0x178E +#define MT6373_RG_BUCK_VBUCK6_RC10_OP_EN_ADDR 0x178E +#define MT6373_RG_BUCK_VBUCK6_RC11_OP_EN_ADDR 0x178E +#define MT6373_RG_BUCK_VBUCK6_RC12_OP_EN_ADDR 0x178E +#define MT6373_RG_BUCK_VBUCK6_RC13_OP_EN_ADDR 0x178E +#define MT6373_RG_BUCK_VBUCK6_HW0_OP_EN_ADDR 0x178F +#define MT6373_RG_BUCK_VBUCK6_HW1_OP_EN_ADDR 0x178F +#define MT6373_RG_BUCK_VBUCK6_HW2_OP_EN_ADDR 0x178F +#define MT6373_RG_BUCK_VBUCK6_HW3_OP_EN_ADDR 0x178F +#define MT6373_RG_BUCK_VBUCK6_SW_OP_EN_ADDR 0x178F +#define MT6373_RG_BUCK_VBUCK6_RC0_OP_CFG_ADDR 0x1790 +#define MT6373_RG_BUCK_VBUCK6_RC1_OP_CFG_ADDR 0x1790 +#define MT6373_RG_BUCK_VBUCK6_RC2_OP_CFG_ADDR 0x1790 +#define MT6373_RG_BUCK_VBUCK6_RC3_OP_CFG_ADDR 0x1790 +#define MT6373_RG_BUCK_VBUCK6_RC4_OP_CFG_ADDR 0x1790 +#define MT6373_RG_BUCK_VBUCK6_RC5_OP_CFG_ADDR 0x1790 +#define MT6373_RG_BUCK_VBUCK6_RC6_OP_CFG_ADDR 0x1790 +#define MT6373_RG_BUCK_VBUCK6_RC7_OP_CFG_ADDR 0x1790 +#define MT6373_RG_BUCK_VBUCK6_RC8_OP_CFG_ADDR 0x1791 +#define MT6373_RG_BUCK_VBUCK6_RC9_OP_CFG_ADDR 0x1791 +#define MT6373_RG_BUCK_VBUCK6_RC10_OP_CFG_ADDR 0x1791 +#define MT6373_RG_BUCK_VBUCK6_RC11_OP_CFG_ADDR 0x1791 +#define MT6373_RG_BUCK_VBUCK6_RC12_OP_CFG_ADDR 0x1791 +#define MT6373_RG_BUCK_VBUCK6_RC13_OP_CFG_ADDR 0x1791 +#define MT6373_RG_BUCK_VBUCK6_HW0_OP_CFG_ADDR 0x1792 +#define MT6373_RG_BUCK_VBUCK6_HW1_OP_CFG_ADDR 0x1792 +#define MT6373_RG_BUCK_VBUCK6_HW2_OP_CFG_ADDR 0x1792 +#define MT6373_RG_BUCK_VBUCK6_HW3_OP_CFG_ADDR 0x1792 +#define MT6373_RG_BUCK_VBUCK6_RC0_OP_MODE_ADDR 0x1793 +#define MT6373_RG_BUCK_VBUCK6_RC1_OP_MODE_ADDR 0x1793 +#define MT6373_RG_BUCK_VBUCK6_RC2_OP_MODE_ADDR 0x1793 +#define MT6373_RG_BUCK_VBUCK6_RC3_OP_MODE_ADDR 0x1793 +#define MT6373_RG_BUCK_VBUCK6_RC4_OP_MODE_ADDR 0x1793 +#define MT6373_RG_BUCK_VBUCK6_RC5_OP_MODE_ADDR 0x1793 +#define MT6373_RG_BUCK_VBUCK6_RC6_OP_MODE_ADDR 0x1793 +#define MT6373_RG_BUCK_VBUCK6_RC7_OP_MODE_ADDR 0x1793 +#define MT6373_RG_BUCK_VBUCK6_RC8_OP_MODE_ADDR 0x1794 +#define MT6373_RG_BUCK_VBUCK6_RC9_OP_MODE_ADDR 0x1794 +#define MT6373_RG_BUCK_VBUCK6_RC10_OP_MODE_ADDR 0x1794 +#define MT6373_RG_BUCK_VBUCK6_RC11_OP_MODE_ADDR 0x1794 +#define MT6373_RG_BUCK_VBUCK6_RC12_OP_MODE_ADDR 0x1794 +#define MT6373_RG_BUCK_VBUCK6_RC13_OP_MODE_ADDR 0x1794 +#define MT6373_RG_BUCK_VBUCK6_HW0_OP_MODE_ADDR 0x1795 +#define MT6373_RG_BUCK_VBUCK6_HW1_OP_MODE_ADDR 0x1795 +#define MT6373_RG_BUCK_VBUCK6_HW2_OP_MODE_ADDR 0x1795 +#define MT6373_RG_BUCK_VBUCK6_HW3_OP_MODE_ADDR 0x1795 +#define MT6373_RG_BUCK_VBUCK7_VOSEL_SLEEP_ADDR 0x1807 +#define MT6373_RG_BUCK_VBUCK7_ONLV_EN_ADDR 0x1808 +#define MT6373_RG_BUCK_VBUCK7_ONLV_EN_SHIFT 4 +#define MT6373_RG_BUCK_VBUCK7_RC0_OP_EN_ADDR 0x180D +#define MT6373_RG_BUCK_VBUCK7_RC1_OP_EN_ADDR 0x180D +#define MT6373_RG_BUCK_VBUCK7_RC2_OP_EN_ADDR 0x180D +#define MT6373_RG_BUCK_VBUCK7_RC3_OP_EN_ADDR 0x180D +#define MT6373_RG_BUCK_VBUCK7_RC4_OP_EN_ADDR 0x180D +#define MT6373_RG_BUCK_VBUCK7_RC5_OP_EN_ADDR 0x180D +#define MT6373_RG_BUCK_VBUCK7_RC6_OP_EN_ADDR 0x180D +#define MT6373_RG_BUCK_VBUCK7_RC7_OP_EN_ADDR 0x180D +#define MT6373_RG_BUCK_VBUCK7_RC8_OP_EN_ADDR 0x180E +#define MT6373_RG_BUCK_VBUCK7_RC9_OP_EN_ADDR 0x180E +#define MT6373_RG_BUCK_VBUCK7_RC10_OP_EN_ADDR 0x180E +#define MT6373_RG_BUCK_VBUCK7_RC11_OP_EN_ADDR 0x180E +#define MT6373_RG_BUCK_VBUCK7_RC12_OP_EN_ADDR 0x180E +#define MT6373_RG_BUCK_VBUCK7_RC13_OP_EN_ADDR 0x180E +#define MT6373_RG_BUCK_VBUCK7_HW0_OP_EN_ADDR 0x180F +#define MT6373_RG_BUCK_VBUCK7_HW1_OP_EN_ADDR 0x180F +#define MT6373_RG_BUCK_VBUCK7_HW2_OP_EN_ADDR 0x180F +#define MT6373_RG_BUCK_VBUCK7_HW3_OP_EN_ADDR 0x180F +#define MT6373_RG_BUCK_VBUCK7_SW_OP_EN_ADDR 0x180F +#define MT6373_RG_BUCK_VBUCK7_RC0_OP_CFG_ADDR 0x1810 +#define MT6373_RG_BUCK_VBUCK7_RC1_OP_CFG_ADDR 0x1810 +#define MT6373_RG_BUCK_VBUCK7_RC2_OP_CFG_ADDR 0x1810 +#define MT6373_RG_BUCK_VBUCK7_RC3_OP_CFG_ADDR 0x1810 +#define MT6373_RG_BUCK_VBUCK7_RC4_OP_CFG_ADDR 0x1810 +#define MT6373_RG_BUCK_VBUCK7_RC5_OP_CFG_ADDR 0x1810 +#define MT6373_RG_BUCK_VBUCK7_RC6_OP_CFG_ADDR 0x1810 +#define MT6373_RG_BUCK_VBUCK7_RC7_OP_CFG_ADDR 0x1810 +#define MT6373_RG_BUCK_VBUCK7_RC8_OP_CFG_ADDR 0x1811 +#define MT6373_RG_BUCK_VBUCK7_RC9_OP_CFG_ADDR 0x1811 +#define MT6373_RG_BUCK_VBUCK7_RC10_OP_CFG_ADDR 0x1811 +#define MT6373_RG_BUCK_VBUCK7_RC11_OP_CFG_ADDR 0x1811 +#define MT6373_RG_BUCK_VBUCK7_RC12_OP_CFG_ADDR 0x1811 +#define MT6373_RG_BUCK_VBUCK7_RC13_OP_CFG_ADDR 0x1811 +#define MT6373_RG_BUCK_VBUCK7_HW0_OP_CFG_ADDR 0x1812 +#define MT6373_RG_BUCK_VBUCK7_HW1_OP_CFG_ADDR 0x1812 +#define MT6373_RG_BUCK_VBUCK7_HW2_OP_CFG_ADDR 0x1812 +#define MT6373_RG_BUCK_VBUCK7_HW3_OP_CFG_ADDR 0x1812 +#define MT6373_RG_BUCK_VBUCK7_RC0_OP_MODE_ADDR 0x1813 +#define MT6373_RG_BUCK_VBUCK7_RC1_OP_MODE_ADDR 0x1813 +#define MT6373_RG_BUCK_VBUCK7_RC2_OP_MODE_ADDR 0x1813 +#define MT6373_RG_BUCK_VBUCK7_RC3_OP_MODE_ADDR 0x1813 +#define MT6373_RG_BUCK_VBUCK7_RC4_OP_MODE_ADDR 0x1813 +#define MT6373_RG_BUCK_VBUCK7_RC5_OP_MODE_ADDR 0x1813 +#define MT6373_RG_BUCK_VBUCK7_RC6_OP_MODE_ADDR 0x1813 +#define MT6373_RG_BUCK_VBUCK7_RC7_OP_MODE_ADDR 0x1813 +#define MT6373_RG_BUCK_VBUCK7_RC8_OP_MODE_ADDR 0x1814 +#define MT6373_RG_BUCK_VBUCK7_RC9_OP_MODE_ADDR 0x1814 +#define MT6373_RG_BUCK_VBUCK7_RC10_OP_MODE_ADDR 0x1814 +#define MT6373_RG_BUCK_VBUCK7_RC11_OP_MODE_ADDR 0x1814 +#define MT6373_RG_BUCK_VBUCK7_RC12_OP_MODE_ADDR 0x1814 +#define MT6373_RG_BUCK_VBUCK7_RC13_OP_MODE_ADDR 0x1814 +#define MT6373_RG_BUCK_VBUCK7_HW0_OP_MODE_ADDR 0x1815 +#define MT6373_RG_BUCK_VBUCK7_HW1_OP_MODE_ADDR 0x1815 +#define MT6373_RG_BUCK_VBUCK7_HW2_OP_MODE_ADDR 0x1815 +#define MT6373_RG_BUCK_VBUCK7_HW3_OP_MODE_ADDR 0x1815 +#define MT6373_RG_BUCK_VBUCK8_VOSEL_SLEEP_ADDR 0x1887 +#define MT6373_RG_BUCK_VBUCK8_ONLV_EN_ADDR 0x1888 +#define MT6373_RG_BUCK_VBUCK8_ONLV_EN_SHIFT 4 +#define MT6373_RG_BUCK_VBUCK8_RC0_OP_EN_ADDR 0x188D +#define MT6373_RG_BUCK_VBUCK8_RC1_OP_EN_ADDR 0x188D +#define MT6373_RG_BUCK_VBUCK8_RC2_OP_EN_ADDR 0x188D +#define MT6373_RG_BUCK_VBUCK8_RC3_OP_EN_ADDR 0x188D +#define MT6373_RG_BUCK_VBUCK8_RC4_OP_EN_ADDR 0x188D +#define MT6373_RG_BUCK_VBUCK8_RC5_OP_EN_ADDR 0x188D +#define MT6373_RG_BUCK_VBUCK8_RC6_OP_EN_ADDR 0x188D +#define MT6373_RG_BUCK_VBUCK8_RC7_OP_EN_ADDR 0x188D +#define MT6373_RG_BUCK_VBUCK8_RC8_OP_EN_ADDR 0x188E +#define MT6373_RG_BUCK_VBUCK8_RC9_OP_EN_ADDR 0x188E +#define MT6373_RG_BUCK_VBUCK8_RC10_OP_EN_ADDR 0x188E +#define MT6373_RG_BUCK_VBUCK8_RC11_OP_EN_ADDR 0x188E +#define MT6373_RG_BUCK_VBUCK8_RC12_OP_EN_ADDR 0x188E +#define MT6373_RG_BUCK_VBUCK8_RC13_OP_EN_ADDR 0x188E +#define MT6373_RG_BUCK_VBUCK8_HW0_OP_EN_ADDR 0x188F +#define MT6373_RG_BUCK_VBUCK8_HW1_OP_EN_ADDR 0x188F +#define MT6373_RG_BUCK_VBUCK8_HW2_OP_EN_ADDR 0x188F +#define MT6373_RG_BUCK_VBUCK8_HW3_OP_EN_ADDR 0x188F +#define MT6373_RG_BUCK_VBUCK8_SW_OP_EN_ADDR 0x188F +#define MT6373_RG_BUCK_VBUCK8_RC0_OP_CFG_ADDR 0x1890 +#define MT6373_RG_BUCK_VBUCK8_RC1_OP_CFG_ADDR 0x1890 +#define MT6373_RG_BUCK_VBUCK8_RC2_OP_CFG_ADDR 0x1890 +#define MT6373_RG_BUCK_VBUCK8_RC3_OP_CFG_ADDR 0x1890 +#define MT6373_RG_BUCK_VBUCK8_RC4_OP_CFG_ADDR 0x1890 +#define MT6373_RG_BUCK_VBUCK8_RC5_OP_CFG_ADDR 0x1890 +#define MT6373_RG_BUCK_VBUCK8_RC6_OP_CFG_ADDR 0x1890 +#define MT6373_RG_BUCK_VBUCK8_RC7_OP_CFG_ADDR 0x1890 +#define MT6373_RG_BUCK_VBUCK8_RC8_OP_CFG_ADDR 0x1891 +#define MT6373_RG_BUCK_VBUCK8_RC9_OP_CFG_ADDR 0x1891 +#define MT6373_RG_BUCK_VBUCK8_RC10_OP_CFG_ADDR 0x1891 +#define MT6373_RG_BUCK_VBUCK8_RC11_OP_CFG_ADDR 0x1891 +#define MT6373_RG_BUCK_VBUCK8_RC12_OP_CFG_ADDR 0x1891 +#define MT6373_RG_BUCK_VBUCK8_RC13_OP_CFG_ADDR 0x1891 +#define MT6373_RG_BUCK_VBUCK8_HW0_OP_CFG_ADDR 0x1892 +#define MT6373_RG_BUCK_VBUCK8_HW1_OP_CFG_ADDR 0x1892 +#define MT6373_RG_BUCK_VBUCK8_HW2_OP_CFG_ADDR 0x1892 +#define MT6373_RG_BUCK_VBUCK8_HW3_OP_CFG_ADDR 0x1892 +#define MT6373_RG_BUCK_VBUCK8_RC0_OP_MODE_ADDR 0x1893 +#define MT6373_RG_BUCK_VBUCK8_RC1_OP_MODE_ADDR 0x1893 +#define MT6373_RG_BUCK_VBUCK8_RC2_OP_MODE_ADDR 0x1893 +#define MT6373_RG_BUCK_VBUCK8_RC3_OP_MODE_ADDR 0x1893 +#define MT6373_RG_BUCK_VBUCK8_RC4_OP_MODE_ADDR 0x1893 +#define MT6373_RG_BUCK_VBUCK8_RC5_OP_MODE_ADDR 0x1893 +#define MT6373_RG_BUCK_VBUCK8_RC6_OP_MODE_ADDR 0x1893 +#define MT6373_RG_BUCK_VBUCK8_RC7_OP_MODE_ADDR 0x1893 +#define MT6373_RG_BUCK_VBUCK8_RC8_OP_MODE_ADDR 0x1894 +#define MT6373_RG_BUCK_VBUCK8_RC9_OP_MODE_ADDR 0x1894 +#define MT6373_RG_BUCK_VBUCK8_RC10_OP_MODE_ADDR 0x1894 +#define MT6373_RG_BUCK_VBUCK8_RC11_OP_MODE_ADDR 0x1894 +#define MT6373_RG_BUCK_VBUCK8_RC12_OP_MODE_ADDR 0x1894 +#define MT6373_RG_BUCK_VBUCK8_RC13_OP_MODE_ADDR 0x1894 +#define MT6373_RG_BUCK_VBUCK8_HW0_OP_MODE_ADDR 0x1895 +#define MT6373_RG_BUCK_VBUCK8_HW1_OP_MODE_ADDR 0x1895 +#define MT6373_RG_BUCK_VBUCK8_HW2_OP_MODE_ADDR 0x1895 +#define MT6373_RG_BUCK_VBUCK8_HW3_OP_MODE_ADDR 0x1895 +#define MT6373_RG_BUCK_VBUCK9_VOSEL_SLEEP_ADDR 0x1907 +#define MT6373_RG_BUCK_VBUCK9_ONLV_EN_ADDR 0x1908 +#define MT6373_RG_BUCK_VBUCK9_ONLV_EN_SHIFT 4 +#define MT6373_RG_BUCK_VBUCK9_RC0_OP_EN_ADDR 0x190D +#define MT6373_RG_BUCK_VBUCK9_RC1_OP_EN_ADDR 0x190D +#define MT6373_RG_BUCK_VBUCK9_RC2_OP_EN_ADDR 0x190D +#define MT6373_RG_BUCK_VBUCK9_RC3_OP_EN_ADDR 0x190D +#define MT6373_RG_BUCK_VBUCK9_RC4_OP_EN_ADDR 0x190D +#define MT6373_RG_BUCK_VBUCK9_RC5_OP_EN_ADDR 0x190D +#define MT6373_RG_BUCK_VBUCK9_RC6_OP_EN_ADDR 0x190D +#define MT6373_RG_BUCK_VBUCK9_RC7_OP_EN_ADDR 0x190D +#define MT6373_RG_BUCK_VBUCK9_RC8_OP_EN_ADDR 0x190E +#define MT6373_RG_BUCK_VBUCK9_RC9_OP_EN_ADDR 0x190E +#define MT6373_RG_BUCK_VBUCK9_RC10_OP_EN_ADDR 0x190E +#define MT6373_RG_BUCK_VBUCK9_RC11_OP_EN_ADDR 0x190E +#define MT6373_RG_BUCK_VBUCK9_RC12_OP_EN_ADDR 0x190E +#define MT6373_RG_BUCK_VBUCK9_RC13_OP_EN_ADDR 0x190E +#define MT6373_RG_BUCK_VBUCK9_HW0_OP_EN_ADDR 0x190F +#define MT6373_RG_BUCK_VBUCK9_HW1_OP_EN_ADDR 0x190F +#define MT6373_RG_BUCK_VBUCK9_HW2_OP_EN_ADDR 0x190F +#define MT6373_RG_BUCK_VBUCK9_HW3_OP_EN_ADDR 0x190F +#define MT6373_RG_BUCK_VBUCK9_SW_OP_EN_ADDR 0x190F +#define MT6373_RG_BUCK_VBUCK9_RC0_OP_CFG_ADDR 0x1910 +#define MT6373_RG_BUCK_VBUCK9_RC1_OP_CFG_ADDR 0x1910 +#define MT6373_RG_BUCK_VBUCK9_RC2_OP_CFG_ADDR 0x1910 +#define MT6373_RG_BUCK_VBUCK9_RC3_OP_CFG_ADDR 0x1910 +#define MT6373_RG_BUCK_VBUCK9_RC4_OP_CFG_ADDR 0x1910 +#define MT6373_RG_BUCK_VBUCK9_RC5_OP_CFG_ADDR 0x1910 +#define MT6373_RG_BUCK_VBUCK9_RC6_OP_CFG_ADDR 0x1910 +#define MT6373_RG_BUCK_VBUCK9_RC7_OP_CFG_ADDR 0x1910 +#define MT6373_RG_BUCK_VBUCK9_RC8_OP_CFG_ADDR 0x1911 +#define MT6373_RG_BUCK_VBUCK9_RC9_OP_CFG_ADDR 0x1911 +#define MT6373_RG_BUCK_VBUCK9_RC10_OP_CFG_ADDR 0x1911 +#define MT6373_RG_BUCK_VBUCK9_RC11_OP_CFG_ADDR 0x1911 +#define MT6373_RG_BUCK_VBUCK9_RC12_OP_CFG_ADDR 0x1911 +#define MT6373_RG_BUCK_VBUCK9_RC13_OP_CFG_ADDR 0x1911 +#define MT6373_RG_BUCK_VBUCK9_HW0_OP_CFG_ADDR 0x1912 +#define MT6373_RG_BUCK_VBUCK9_HW1_OP_CFG_ADDR 0x1912 +#define MT6373_RG_BUCK_VBUCK9_HW2_OP_CFG_ADDR 0x1912 +#define MT6373_RG_BUCK_VBUCK9_HW3_OP_CFG_ADDR 0x1912 +#define MT6373_RG_BUCK_VBUCK9_RC0_OP_MODE_ADDR 0x1913 +#define MT6373_RG_BUCK_VBUCK9_RC1_OP_MODE_ADDR 0x1913 +#define MT6373_RG_BUCK_VBUCK9_RC2_OP_MODE_ADDR 0x1913 +#define MT6373_RG_BUCK_VBUCK9_RC3_OP_MODE_ADDR 0x1913 +#define MT6373_RG_BUCK_VBUCK9_RC4_OP_MODE_ADDR 0x1913 +#define MT6373_RG_BUCK_VBUCK9_RC5_OP_MODE_ADDR 0x1913 +#define MT6373_RG_BUCK_VBUCK9_RC6_OP_MODE_ADDR 0x1913 +#define MT6373_RG_BUCK_VBUCK9_RC7_OP_MODE_ADDR 0x1913 +#define MT6373_RG_BUCK_VBUCK9_RC8_OP_MODE_ADDR 0x1914 +#define MT6373_RG_BUCK_VBUCK9_RC9_OP_MODE_ADDR 0x1914 +#define MT6373_RG_BUCK_VBUCK9_RC10_OP_MODE_ADDR 0x1914 +#define MT6373_RG_BUCK_VBUCK9_RC11_OP_MODE_ADDR 0x1914 +#define MT6373_RG_BUCK_VBUCK9_RC12_OP_MODE_ADDR 0x1914 +#define MT6373_RG_BUCK_VBUCK9_RC13_OP_MODE_ADDR 0x1914 +#define MT6373_RG_BUCK_VBUCK9_HW0_OP_MODE_ADDR 0x1915 +#define MT6373_RG_BUCK_VBUCK9_HW1_OP_MODE_ADDR 0x1915 +#define MT6373_RG_BUCK_VBUCK9_HW2_OP_MODE_ADDR 0x1915 +#define MT6373_RG_BUCK_VBUCK9_HW3_OP_MODE_ADDR 0x1915 +#define MT6373_RG_LDO_VAUD18_ONLV_EN_ADDR 0x1B88 +#define MT6373_RG_LDO_VAUD18_ONLV_EN_SHIFT 3 +#define MT6373_RG_LDO_VAUD18_RC0_OP_EN_ADDR 0x1B8C +#define MT6373_RG_LDO_VAUD18_RC1_OP_EN_ADDR 0x1B8C +#define MT6373_RG_LDO_VAUD18_RC2_OP_EN_ADDR 0x1B8C +#define MT6373_RG_LDO_VAUD18_RC3_OP_EN_ADDR 0x1B8C +#define MT6373_RG_LDO_VAUD18_RC4_OP_EN_ADDR 0x1B8C +#define MT6373_RG_LDO_VAUD18_RC5_OP_EN_ADDR 0x1B8C +#define MT6373_RG_LDO_VAUD18_RC6_OP_EN_ADDR 0x1B8C +#define MT6373_RG_LDO_VAUD18_RC7_OP_EN_ADDR 0x1B8C +#define MT6373_RG_LDO_VAUD18_RC8_OP_EN_ADDR 0x1B8D +#define MT6373_RG_LDO_VAUD18_RC9_OP_EN_ADDR 0x1B8D +#define MT6373_RG_LDO_VAUD18_RC10_OP_EN_ADDR 0x1B8D +#define MT6373_RG_LDO_VAUD18_RC11_OP_EN_ADDR 0x1B8D +#define MT6373_RG_LDO_VAUD18_RC12_OP_EN_ADDR 0x1B8D +#define MT6373_RG_LDO_VAUD18_RC13_OP_EN_ADDR 0x1B8D +#define MT6373_RG_LDO_VAUD18_HW0_OP_EN_ADDR 0x1B8E +#define MT6373_RG_LDO_VAUD18_HW1_OP_EN_ADDR 0x1B8E +#define MT6373_RG_LDO_VAUD18_HW2_OP_EN_ADDR 0x1B8E +#define MT6373_RG_LDO_VAUD18_HW3_OP_EN_ADDR 0x1B8E +#define MT6373_RG_LDO_VAUD18_HW4_OP_EN_ADDR 0x1B8E +#define MT6373_RG_LDO_VAUD18_HW5_OP_EN_ADDR 0x1B8E +#define MT6373_RG_LDO_VAUD18_HW6_OP_EN_ADDR 0x1B8E +#define MT6373_RG_LDO_VAUD18_SW_OP_EN_ADDR 0x1B8E +#define MT6373_RG_LDO_VAUD18_RC0_OP_CFG_ADDR 0x1B8F +#define MT6373_RG_LDO_VAUD18_RC1_OP_CFG_ADDR 0x1B8F +#define MT6373_RG_LDO_VAUD18_RC2_OP_CFG_ADDR 0x1B8F +#define MT6373_RG_LDO_VAUD18_RC3_OP_CFG_ADDR 0x1B8F +#define MT6373_RG_LDO_VAUD18_RC4_OP_CFG_ADDR 0x1B8F +#define MT6373_RG_LDO_VAUD18_RC5_OP_CFG_ADDR 0x1B8F +#define MT6373_RG_LDO_VAUD18_RC6_OP_CFG_ADDR 0x1B8F +#define MT6373_RG_LDO_VAUD18_RC7_OP_CFG_ADDR 0x1B8F +#define MT6373_RG_LDO_VAUD18_RC8_OP_CFG_ADDR 0x1B90 +#define MT6373_RG_LDO_VAUD18_RC9_OP_CFG_ADDR 0x1B90 +#define MT6373_RG_LDO_VAUD18_RC10_OP_CFG_ADDR 0x1B90 +#define MT6373_RG_LDO_VAUD18_RC11_OP_CFG_ADDR 0x1B90 +#define MT6373_RG_LDO_VAUD18_RC12_OP_CFG_ADDR 0x1B90 +#define MT6373_RG_LDO_VAUD18_RC13_OP_CFG_ADDR 0x1B90 +#define MT6373_RG_LDO_VAUD18_HW0_OP_CFG_ADDR 0x1B91 +#define MT6373_RG_LDO_VAUD18_HW1_OP_CFG_ADDR 0x1B91 +#define MT6373_RG_LDO_VAUD18_HW2_OP_CFG_ADDR 0x1B91 +#define MT6373_RG_LDO_VAUD18_HW3_OP_CFG_ADDR 0x1B91 +#define MT6373_RG_LDO_VAUD18_HW4_OP_CFG_ADDR 0x1B91 +#define MT6373_RG_LDO_VAUD18_HW5_OP_CFG_ADDR 0x1B91 +#define MT6373_RG_LDO_VAUD18_HW6_OP_CFG_ADDR 0x1B91 +#define MT6373_RG_LDO_VAUD18_SW_OP_CFG_ADDR 0x1B91 +#define MT6373_RG_LDO_VAUD18_RC0_OP_MODE_ADDR 0x1B92 +#define MT6373_RG_LDO_VAUD18_RC1_OP_MODE_ADDR 0x1B92 +#define MT6373_RG_LDO_VAUD18_RC2_OP_MODE_ADDR 0x1B92 +#define MT6373_RG_LDO_VAUD18_RC3_OP_MODE_ADDR 0x1B92 +#define MT6373_RG_LDO_VAUD18_RC4_OP_MODE_ADDR 0x1B92 +#define MT6373_RG_LDO_VAUD18_RC5_OP_MODE_ADDR 0x1B92 +#define MT6373_RG_LDO_VAUD18_RC6_OP_MODE_ADDR 0x1B92 +#define MT6373_RG_LDO_VAUD18_RC7_OP_MODE_ADDR 0x1B92 +#define MT6373_RG_LDO_VAUD18_RC8_OP_MODE_ADDR 0x1B93 +#define MT6373_RG_LDO_VAUD18_RC9_OP_MODE_ADDR 0x1B93 +#define MT6373_RG_LDO_VAUD18_RC10_OP_MODE_ADDR 0x1B93 +#define MT6373_RG_LDO_VAUD18_RC11_OP_MODE_ADDR 0x1B93 +#define MT6373_RG_LDO_VAUD18_RC12_OP_MODE_ADDR 0x1B93 +#define MT6373_RG_LDO_VAUD18_RC13_OP_MODE_ADDR 0x1B93 +#define MT6373_RG_LDO_VAUD18_HW0_OP_MODE_ADDR 0x1B94 +#define MT6373_RG_LDO_VAUD18_HW1_OP_MODE_ADDR 0x1B94 +#define MT6373_RG_LDO_VAUD18_HW2_OP_MODE_ADDR 0x1B94 +#define MT6373_RG_LDO_VAUD18_HW3_OP_MODE_ADDR 0x1B94 +#define MT6373_RG_LDO_VAUD18_HW4_OP_MODE_ADDR 0x1B94 +#define MT6373_RG_LDO_VAUD18_HW5_OP_MODE_ADDR 0x1B94 +#define MT6373_RG_LDO_VAUD18_HW6_OP_MODE_ADDR 0x1B94 +#define MT6373_RG_LDO_VUSB_ONLV_EN_ADDR 0x1B96 +#define MT6373_RG_LDO_VUSB_ONLV_EN_SHIFT 3 +#define MT6373_RG_LDO_VUSB_RC0_OP_EN_ADDR 0x1B9A +#define MT6373_RG_LDO_VUSB_RC1_OP_EN_ADDR 0x1B9A +#define MT6373_RG_LDO_VUSB_RC2_OP_EN_ADDR 0x1B9A +#define MT6373_RG_LDO_VUSB_RC3_OP_EN_ADDR 0x1B9A +#define MT6373_RG_LDO_VUSB_RC4_OP_EN_ADDR 0x1B9A +#define MT6373_RG_LDO_VUSB_RC5_OP_EN_ADDR 0x1B9A +#define MT6373_RG_LDO_VUSB_RC6_OP_EN_ADDR 0x1B9A +#define MT6373_RG_LDO_VUSB_RC7_OP_EN_ADDR 0x1B9A +#define MT6373_RG_LDO_VUSB_RC8_OP_EN_ADDR 0x1B9B +#define MT6373_RG_LDO_VUSB_RC9_OP_EN_ADDR 0x1B9B +#define MT6373_RG_LDO_VUSB_RC10_OP_EN_ADDR 0x1B9B +#define MT6373_RG_LDO_VUSB_RC11_OP_EN_ADDR 0x1B9B +#define MT6373_RG_LDO_VUSB_RC12_OP_EN_ADDR 0x1B9B +#define MT6373_RG_LDO_VUSB_RC13_OP_EN_ADDR 0x1B9B +#define MT6373_RG_LDO_VUSB_HW0_OP_EN_ADDR 0x1B9C +#define MT6373_RG_LDO_VUSB_HW1_OP_EN_ADDR 0x1B9C +#define MT6373_RG_LDO_VUSB_HW2_OP_EN_ADDR 0x1B9C +#define MT6373_RG_LDO_VUSB_HW3_OP_EN_ADDR 0x1B9C +#define MT6373_RG_LDO_VUSB_HW4_OP_EN_ADDR 0x1B9C +#define MT6373_RG_LDO_VUSB_HW5_OP_EN_ADDR 0x1B9C +#define MT6373_RG_LDO_VUSB_HW6_OP_EN_ADDR 0x1B9C +#define MT6373_RG_LDO_VUSB_SW_OP_EN_ADDR 0x1B9C +#define MT6373_RG_LDO_VUSB_RC0_OP_CFG_ADDR 0x1B9D +#define MT6373_RG_LDO_VUSB_RC1_OP_CFG_ADDR 0x1B9D +#define MT6373_RG_LDO_VUSB_RC2_OP_CFG_ADDR 0x1B9D +#define MT6373_RG_LDO_VUSB_RC3_OP_CFG_ADDR 0x1B9D +#define MT6373_RG_LDO_VUSB_RC4_OP_CFG_ADDR 0x1B9D +#define MT6373_RG_LDO_VUSB_RC5_OP_CFG_ADDR 0x1B9D +#define MT6373_RG_LDO_VUSB_RC6_OP_CFG_ADDR 0x1B9D +#define MT6373_RG_LDO_VUSB_RC7_OP_CFG_ADDR 0x1B9D +#define MT6373_RG_LDO_VUSB_RC8_OP_CFG_ADDR 0x1B9E +#define MT6373_RG_LDO_VUSB_RC9_OP_CFG_ADDR 0x1B9E +#define MT6373_RG_LDO_VUSB_RC10_OP_CFG_ADDR 0x1B9E +#define MT6373_RG_LDO_VUSB_RC11_OP_CFG_ADDR 0x1B9E +#define MT6373_RG_LDO_VUSB_RC12_OP_CFG_ADDR 0x1B9E +#define MT6373_RG_LDO_VUSB_RC13_OP_CFG_ADDR 0x1B9E +#define MT6373_RG_LDO_VUSB_HW0_OP_CFG_ADDR 0x1B9F +#define MT6373_RG_LDO_VUSB_HW1_OP_CFG_ADDR 0x1B9F +#define MT6373_RG_LDO_VUSB_HW2_OP_CFG_ADDR 0x1B9F +#define MT6373_RG_LDO_VUSB_HW3_OP_CFG_ADDR 0x1B9F +#define MT6373_RG_LDO_VUSB_HW4_OP_CFG_ADDR 0x1B9F +#define MT6373_RG_LDO_VUSB_HW5_OP_CFG_ADDR 0x1B9F +#define MT6373_RG_LDO_VUSB_HW6_OP_CFG_ADDR 0x1B9F +#define MT6373_RG_LDO_VUSB_SW_OP_CFG_ADDR 0x1B9F +#define MT6373_RG_LDO_VUSB_RC0_OP_MODE_ADDR 0x1BA0 +#define MT6373_RG_LDO_VUSB_RC1_OP_MODE_ADDR 0x1BA0 +#define MT6373_RG_LDO_VUSB_RC2_OP_MODE_ADDR 0x1BA0 +#define MT6373_RG_LDO_VUSB_RC3_OP_MODE_ADDR 0x1BA0 +#define MT6373_RG_LDO_VUSB_RC4_OP_MODE_ADDR 0x1BA0 +#define MT6373_RG_LDO_VUSB_RC5_OP_MODE_ADDR 0x1BA0 +#define MT6373_RG_LDO_VUSB_RC6_OP_MODE_ADDR 0x1BA0 +#define MT6373_RG_LDO_VUSB_RC7_OP_MODE_ADDR 0x1BA0 +#define MT6373_RG_LDO_VUSB_RC8_OP_MODE_ADDR 0x1BA1 +#define MT6373_RG_LDO_VUSB_RC9_OP_MODE_ADDR 0x1BA1 +#define MT6373_RG_LDO_VUSB_RC10_OP_MODE_ADDR 0x1BA1 +#define MT6373_RG_LDO_VUSB_RC11_OP_MODE_ADDR 0x1BA1 +#define MT6373_RG_LDO_VUSB_RC12_OP_MODE_ADDR 0x1BA1 +#define MT6373_RG_LDO_VUSB_RC13_OP_MODE_ADDR 0x1BA1 +#define MT6373_RG_LDO_VUSB_HW0_OP_MODE_ADDR 0x1BA2 +#define MT6373_RG_LDO_VUSB_HW1_OP_MODE_ADDR 0x1BA2 +#define MT6373_RG_LDO_VUSB_HW2_OP_MODE_ADDR 0x1BA2 +#define MT6373_RG_LDO_VUSB_HW3_OP_MODE_ADDR 0x1BA2 +#define MT6373_RG_LDO_VUSB_HW4_OP_MODE_ADDR 0x1BA2 +#define MT6373_RG_LDO_VUSB_HW5_OP_MODE_ADDR 0x1BA2 +#define MT6373_RG_LDO_VUSB_HW6_OP_MODE_ADDR 0x1BA2 +#define MT6373_RG_LDO_VAUX18_ONLV_EN_ADDR 0x1BA4 +#define MT6373_RG_LDO_VAUX18_ONLV_EN_SHIFT 3 +#define MT6373_RG_LDO_VAUX18_RC0_OP_EN_ADDR 0x1BA8 +#define MT6373_RG_LDO_VAUX18_RC1_OP_EN_ADDR 0x1BA8 +#define MT6373_RG_LDO_VAUX18_RC2_OP_EN_ADDR 0x1BA8 +#define MT6373_RG_LDO_VAUX18_RC3_OP_EN_ADDR 0x1BA8 +#define MT6373_RG_LDO_VAUX18_RC4_OP_EN_ADDR 0x1BA8 +#define MT6373_RG_LDO_VAUX18_RC5_OP_EN_ADDR 0x1BA8 +#define MT6373_RG_LDO_VAUX18_RC6_OP_EN_ADDR 0x1BA8 +#define MT6373_RG_LDO_VAUX18_RC7_OP_EN_ADDR 0x1BA8 +#define MT6373_RG_LDO_VAUX18_RC8_OP_EN_ADDR 0x1BA9 +#define MT6373_RG_LDO_VAUX18_RC9_OP_EN_ADDR 0x1BA9 +#define MT6373_RG_LDO_VAUX18_RC10_OP_EN_ADDR 0x1BA9 +#define MT6373_RG_LDO_VAUX18_RC11_OP_EN_ADDR 0x1BA9 +#define MT6373_RG_LDO_VAUX18_RC12_OP_EN_ADDR 0x1BA9 +#define MT6373_RG_LDO_VAUX18_RC13_OP_EN_ADDR 0x1BA9 +#define MT6373_RG_LDO_VAUX18_HW0_OP_EN_ADDR 0x1BAA +#define MT6373_RG_LDO_VAUX18_HW1_OP_EN_ADDR 0x1BAA +#define MT6373_RG_LDO_VAUX18_HW2_OP_EN_ADDR 0x1BAA +#define MT6373_RG_LDO_VAUX18_HW3_OP_EN_ADDR 0x1BAA +#define MT6373_RG_LDO_VAUX18_HW4_OP_EN_ADDR 0x1BAA +#define MT6373_RG_LDO_VAUX18_HW5_OP_EN_ADDR 0x1BAA +#define MT6373_RG_LDO_VAUX18_HW6_OP_EN_ADDR 0x1BAA +#define MT6373_RG_LDO_VAUX18_SW_OP_EN_ADDR 0x1BAA +#define MT6373_RG_LDO_VAUX18_RC0_OP_CFG_ADDR 0x1BAB +#define MT6373_RG_LDO_VAUX18_RC1_OP_CFG_ADDR 0x1BAB +#define MT6373_RG_LDO_VAUX18_RC2_OP_CFG_ADDR 0x1BAB +#define MT6373_RG_LDO_VAUX18_RC3_OP_CFG_ADDR 0x1BAB +#define MT6373_RG_LDO_VAUX18_RC4_OP_CFG_ADDR 0x1BAB +#define MT6373_RG_LDO_VAUX18_RC5_OP_CFG_ADDR 0x1BAB +#define MT6373_RG_LDO_VAUX18_RC6_OP_CFG_ADDR 0x1BAB +#define MT6373_RG_LDO_VAUX18_RC7_OP_CFG_ADDR 0x1BAB +#define MT6373_RG_LDO_VAUX18_RC8_OP_CFG_ADDR 0x1BAC +#define MT6373_RG_LDO_VAUX18_RC9_OP_CFG_ADDR 0x1BAC +#define MT6373_RG_LDO_VAUX18_RC10_OP_CFG_ADDR 0x1BAC +#define MT6373_RG_LDO_VAUX18_RC11_OP_CFG_ADDR 0x1BAC +#define MT6373_RG_LDO_VAUX18_RC12_OP_CFG_ADDR 0x1BAC +#define MT6373_RG_LDO_VAUX18_RC13_OP_CFG_ADDR 0x1BAC +#define MT6373_RG_LDO_VAUX18_HW0_OP_CFG_ADDR 0x1BAD +#define MT6373_RG_LDO_VAUX18_HW1_OP_CFG_ADDR 0x1BAD +#define MT6373_RG_LDO_VAUX18_HW2_OP_CFG_ADDR 0x1BAD +#define MT6373_RG_LDO_VAUX18_HW3_OP_CFG_ADDR 0x1BAD +#define MT6373_RG_LDO_VAUX18_HW4_OP_CFG_ADDR 0x1BAD +#define MT6373_RG_LDO_VAUX18_HW5_OP_CFG_ADDR 0x1BAD +#define MT6373_RG_LDO_VAUX18_HW6_OP_CFG_ADDR 0x1BAD +#define MT6373_RG_LDO_VAUX18_SW_OP_CFG_ADDR 0x1BAD +#define MT6373_RG_LDO_VAUX18_RC0_OP_MODE_ADDR 0x1BAE +#define MT6373_RG_LDO_VAUX18_RC1_OP_MODE_ADDR 0x1BAE +#define MT6373_RG_LDO_VAUX18_RC2_OP_MODE_ADDR 0x1BAE +#define MT6373_RG_LDO_VAUX18_RC3_OP_MODE_ADDR 0x1BAE +#define MT6373_RG_LDO_VAUX18_RC4_OP_MODE_ADDR 0x1BAE +#define MT6373_RG_LDO_VAUX18_RC5_OP_MODE_ADDR 0x1BAE +#define MT6373_RG_LDO_VAUX18_RC6_OP_MODE_ADDR 0x1BAE +#define MT6373_RG_LDO_VAUX18_RC7_OP_MODE_ADDR 0x1BAE +#define MT6373_RG_LDO_VAUX18_RC8_OP_MODE_ADDR 0x1BAF +#define MT6373_RG_LDO_VAUX18_RC9_OP_MODE_ADDR 0x1BAF +#define MT6373_RG_LDO_VAUX18_RC10_OP_MODE_ADDR 0x1BAF +#define MT6373_RG_LDO_VAUX18_RC11_OP_MODE_ADDR 0x1BAF +#define MT6373_RG_LDO_VAUX18_RC12_OP_MODE_ADDR 0x1BAF +#define MT6373_RG_LDO_VAUX18_RC13_OP_MODE_ADDR 0x1BAF +#define MT6373_RG_LDO_VAUX18_HW0_OP_MODE_ADDR 0x1BB0 +#define MT6373_RG_LDO_VAUX18_HW1_OP_MODE_ADDR 0x1BB0 +#define MT6373_RG_LDO_VAUX18_HW2_OP_MODE_ADDR 0x1BB0 +#define MT6373_RG_LDO_VAUX18_HW3_OP_MODE_ADDR 0x1BB0 +#define MT6373_RG_LDO_VAUX18_HW4_OP_MODE_ADDR 0x1BB0 +#define MT6373_RG_LDO_VAUX18_HW5_OP_MODE_ADDR 0x1BB0 +#define MT6373_RG_LDO_VAUX18_HW6_OP_MODE_ADDR 0x1BB0 +#define MT6373_RG_LDO_VRF13_AIF_ONLV_EN_ADDR 0x1BB2 +#define MT6373_RG_LDO_VRF13_AIF_ONLV_EN_SHIFT 3 +#define MT6373_RG_LDO_VRF13_AIF_RC0_OP_EN_ADDR 0x1BB6 +#define MT6373_RG_LDO_VRF13_AIF_RC1_OP_EN_ADDR 0x1BB6 +#define MT6373_RG_LDO_VRF13_AIF_RC2_OP_EN_ADDR 0x1BB6 +#define MT6373_RG_LDO_VRF13_AIF_RC3_OP_EN_ADDR 0x1BB6 +#define MT6373_RG_LDO_VRF13_AIF_RC4_OP_EN_ADDR 0x1BB6 +#define MT6373_RG_LDO_VRF13_AIF_RC5_OP_EN_ADDR 0x1BB6 +#define MT6373_RG_LDO_VRF13_AIF_RC6_OP_EN_ADDR 0x1BB6 +#define MT6373_RG_LDO_VRF13_AIF_RC7_OP_EN_ADDR 0x1BB6 +#define MT6373_RG_LDO_VRF13_AIF_RC8_OP_EN_ADDR 0x1BB7 +#define MT6373_RG_LDO_VRF13_AIF_RC9_OP_EN_ADDR 0x1BB7 +#define MT6373_RG_LDO_VRF13_AIF_RC10_OP_EN_ADDR 0x1BB7 +#define MT6373_RG_LDO_VRF13_AIF_RC11_OP_EN_ADDR 0x1BB7 +#define MT6373_RG_LDO_VRF13_AIF_RC12_OP_EN_ADDR 0x1BB7 +#define MT6373_RG_LDO_VRF13_AIF_RC13_OP_EN_ADDR 0x1BB7 +#define MT6373_RG_LDO_VRF13_AIF_HW0_OP_EN_ADDR 0x1BB8 +#define MT6373_RG_LDO_VRF13_AIF_HW1_OP_EN_ADDR 0x1BB8 +#define MT6373_RG_LDO_VRF13_AIF_HW2_OP_EN_ADDR 0x1BB8 +#define MT6373_RG_LDO_VRF13_AIF_HW3_OP_EN_ADDR 0x1BB8 +#define MT6373_RG_LDO_VRF13_AIF_HW4_OP_EN_ADDR 0x1BB8 +#define MT6373_RG_LDO_VRF13_AIF_HW5_OP_EN_ADDR 0x1BB8 +#define MT6373_RG_LDO_VRF13_AIF_HW6_OP_EN_ADDR 0x1BB8 +#define MT6373_RG_LDO_VRF13_AIF_SW_OP_EN_ADDR 0x1BB8 +#define MT6373_RG_LDO_VRF13_AIF_RC0_OP_CFG_ADDR 0x1BB9 +#define MT6373_RG_LDO_VRF13_AIF_RC1_OP_CFG_ADDR 0x1BB9 +#define MT6373_RG_LDO_VRF13_AIF_RC2_OP_CFG_ADDR 0x1BB9 +#define MT6373_RG_LDO_VRF13_AIF_RC3_OP_CFG_ADDR 0x1BB9 +#define MT6373_RG_LDO_VRF13_AIF_RC4_OP_CFG_ADDR 0x1BB9 +#define MT6373_RG_LDO_VRF13_AIF_RC5_OP_CFG_ADDR 0x1BB9 +#define MT6373_RG_LDO_VRF13_AIF_RC6_OP_CFG_ADDR 0x1BB9 +#define MT6373_RG_LDO_VRF13_AIF_RC7_OP_CFG_ADDR 0x1BB9 +#define MT6373_RG_LDO_VRF13_AIF_RC8_OP_CFG_ADDR 0x1BBA +#define MT6373_RG_LDO_VRF13_AIF_RC9_OP_CFG_ADDR 0x1BBA +#define MT6373_RG_LDO_VRF13_AIF_RC10_OP_CFG_ADDR 0x1BBA +#define MT6373_RG_LDO_VRF13_AIF_RC11_OP_CFG_ADDR 0x1BBA +#define MT6373_RG_LDO_VRF13_AIF_RC12_OP_CFG_ADDR 0x1BBA +#define MT6373_RG_LDO_VRF13_AIF_RC13_OP_CFG_ADDR 0x1BBA +#define MT6373_RG_LDO_VRF13_AIF_HW0_OP_CFG_ADDR 0x1BBB +#define MT6373_RG_LDO_VRF13_AIF_HW1_OP_CFG_ADDR 0x1BBB +#define MT6373_RG_LDO_VRF13_AIF_HW2_OP_CFG_ADDR 0x1BBB +#define MT6373_RG_LDO_VRF13_AIF_HW3_OP_CFG_ADDR 0x1BBB +#define MT6373_RG_LDO_VRF13_AIF_HW4_OP_CFG_ADDR 0x1BBB +#define MT6373_RG_LDO_VRF13_AIF_HW5_OP_CFG_ADDR 0x1BBB +#define MT6373_RG_LDO_VRF13_AIF_HW6_OP_CFG_ADDR 0x1BBB +#define MT6373_RG_LDO_VRF13_AIF_SW_OP_CFG_ADDR 0x1BBB +#define MT6373_RG_LDO_VRF13_AIF_RC0_OP_MODE_ADDR 0x1BBC +#define MT6373_RG_LDO_VRF13_AIF_RC1_OP_MODE_ADDR 0x1BBC +#define MT6373_RG_LDO_VRF13_AIF_RC2_OP_MODE_ADDR 0x1BBC +#define MT6373_RG_LDO_VRF13_AIF_RC3_OP_MODE_ADDR 0x1BBC +#define MT6373_RG_LDO_VRF13_AIF_RC4_OP_MODE_ADDR 0x1BBC +#define MT6373_RG_LDO_VRF13_AIF_RC5_OP_MODE_ADDR 0x1BBC +#define MT6373_RG_LDO_VRF13_AIF_RC6_OP_MODE_ADDR 0x1BBC +#define MT6373_RG_LDO_VRF13_AIF_RC7_OP_MODE_ADDR 0x1BBC +#define MT6373_RG_LDO_VRF13_AIF_RC8_OP_MODE_ADDR 0x1BBD +#define MT6373_RG_LDO_VRF13_AIF_RC9_OP_MODE_ADDR 0x1BBD +#define MT6373_RG_LDO_VRF13_AIF_RC10_OP_MODE_ADDR 0x1BBD +#define MT6373_RG_LDO_VRF13_AIF_RC11_OP_MODE_ADDR 0x1BBD +#define MT6373_RG_LDO_VRF13_AIF_RC12_OP_MODE_ADDR 0x1BBD +#define MT6373_RG_LDO_VRF13_AIF_RC13_OP_MODE_ADDR 0x1BBD +#define MT6373_RG_LDO_VRF13_AIF_HW0_OP_MODE_ADDR 0x1BBE +#define MT6373_RG_LDO_VRF13_AIF_HW1_OP_MODE_ADDR 0x1BBE +#define MT6373_RG_LDO_VRF13_AIF_HW2_OP_MODE_ADDR 0x1BBE +#define MT6373_RG_LDO_VRF13_AIF_HW3_OP_MODE_ADDR 0x1BBE +#define MT6373_RG_LDO_VRF13_AIF_HW4_OP_MODE_ADDR 0x1BBE +#define MT6373_RG_LDO_VRF13_AIF_HW5_OP_MODE_ADDR 0x1BBE +#define MT6373_RG_LDO_VRF13_AIF_HW6_OP_MODE_ADDR 0x1BBE +#define MT6373_RG_LDO_VRF18_AIF_ONLV_EN_ADDR 0x1BC0 +#define MT6373_RG_LDO_VRF18_AIF_ONLV_EN_SHIFT 3 +#define MT6373_RG_LDO_VRF18_AIF_RC0_OP_EN_ADDR 0x1BC4 +#define MT6373_RG_LDO_VRF18_AIF_RC1_OP_EN_ADDR 0x1BC4 +#define MT6373_RG_LDO_VRF18_AIF_RC2_OP_EN_ADDR 0x1BC4 +#define MT6373_RG_LDO_VRF18_AIF_RC3_OP_EN_ADDR 0x1BC4 +#define MT6373_RG_LDO_VRF18_AIF_RC4_OP_EN_ADDR 0x1BC4 +#define MT6373_RG_LDO_VRF18_AIF_RC5_OP_EN_ADDR 0x1BC4 +#define MT6373_RG_LDO_VRF18_AIF_RC6_OP_EN_ADDR 0x1BC4 +#define MT6373_RG_LDO_VRF18_AIF_RC7_OP_EN_ADDR 0x1BC4 +#define MT6373_RG_LDO_VRF18_AIF_RC8_OP_EN_ADDR 0x1BC5 +#define MT6373_RG_LDO_VRF18_AIF_RC9_OP_EN_ADDR 0x1BC5 +#define MT6373_RG_LDO_VRF18_AIF_RC10_OP_EN_ADDR 0x1BC5 +#define MT6373_RG_LDO_VRF18_AIF_RC11_OP_EN_ADDR 0x1BC5 +#define MT6373_RG_LDO_VRF18_AIF_RC12_OP_EN_ADDR 0x1BC5 +#define MT6373_RG_LDO_VRF18_AIF_RC13_OP_EN_ADDR 0x1BC5 +#define MT6373_RG_LDO_VRF18_AIF_HW0_OP_EN_ADDR 0x1BC6 +#define MT6373_RG_LDO_VRF18_AIF_HW1_OP_EN_ADDR 0x1BC6 +#define MT6373_RG_LDO_VRF18_AIF_HW2_OP_EN_ADDR 0x1BC6 +#define MT6373_RG_LDO_VRF18_AIF_HW3_OP_EN_ADDR 0x1BC6 +#define MT6373_RG_LDO_VRF18_AIF_HW4_OP_EN_ADDR 0x1BC6 +#define MT6373_RG_LDO_VRF18_AIF_HW5_OP_EN_ADDR 0x1BC6 +#define MT6373_RG_LDO_VRF18_AIF_HW6_OP_EN_ADDR 0x1BC6 +#define MT6373_RG_LDO_VRF18_AIF_SW_OP_EN_ADDR 0x1BC6 +#define MT6373_RG_LDO_VRF18_AIF_RC0_OP_CFG_ADDR 0x1BC7 +#define MT6373_RG_LDO_VRF18_AIF_RC1_OP_CFG_ADDR 0x1BC7 +#define MT6373_RG_LDO_VRF18_AIF_RC2_OP_CFG_ADDR 0x1BC7 +#define MT6373_RG_LDO_VRF18_AIF_RC3_OP_CFG_ADDR 0x1BC7 +#define MT6373_RG_LDO_VRF18_AIF_RC4_OP_CFG_ADDR 0x1BC7 +#define MT6373_RG_LDO_VRF18_AIF_RC5_OP_CFG_ADDR 0x1BC7 +#define MT6373_RG_LDO_VRF18_AIF_RC6_OP_CFG_ADDR 0x1BC7 +#define MT6373_RG_LDO_VRF18_AIF_RC7_OP_CFG_ADDR 0x1BC7 +#define MT6373_RG_LDO_VRF18_AIF_RC8_OP_CFG_ADDR 0x1BC8 +#define MT6373_RG_LDO_VRF18_AIF_RC9_OP_CFG_ADDR 0x1BC8 +#define MT6373_RG_LDO_VRF18_AIF_RC10_OP_CFG_ADDR 0x1BC8 +#define MT6373_RG_LDO_VRF18_AIF_RC11_OP_CFG_ADDR 0x1BC8 +#define MT6373_RG_LDO_VRF18_AIF_RC12_OP_CFG_ADDR 0x1BC8 +#define MT6373_RG_LDO_VRF18_AIF_RC13_OP_CFG_ADDR 0x1BC8 +#define MT6373_RG_LDO_VRF18_AIF_HW0_OP_CFG_ADDR 0x1BC9 +#define MT6373_RG_LDO_VRF18_AIF_HW1_OP_CFG_ADDR 0x1BC9 +#define MT6373_RG_LDO_VRF18_AIF_HW2_OP_CFG_ADDR 0x1BC9 +#define MT6373_RG_LDO_VRF18_AIF_HW3_OP_CFG_ADDR 0x1BC9 +#define MT6373_RG_LDO_VRF18_AIF_HW4_OP_CFG_ADDR 0x1BC9 +#define MT6373_RG_LDO_VRF18_AIF_HW5_OP_CFG_ADDR 0x1BC9 +#define MT6373_RG_LDO_VRF18_AIF_HW6_OP_CFG_ADDR 0x1BC9 +#define MT6373_RG_LDO_VRF18_AIF_SW_OP_CFG_ADDR 0x1BC9 +#define MT6373_RG_LDO_VRF18_AIF_RC0_OP_MODE_ADDR 0x1BCA +#define MT6373_RG_LDO_VRF18_AIF_RC1_OP_MODE_ADDR 0x1BCA +#define MT6373_RG_LDO_VRF18_AIF_RC2_OP_MODE_ADDR 0x1BCA +#define MT6373_RG_LDO_VRF18_AIF_RC3_OP_MODE_ADDR 0x1BCA +#define MT6373_RG_LDO_VRF18_AIF_RC4_OP_MODE_ADDR 0x1BCA +#define MT6373_RG_LDO_VRF18_AIF_RC5_OP_MODE_ADDR 0x1BCA +#define MT6373_RG_LDO_VRF18_AIF_RC6_OP_MODE_ADDR 0x1BCA +#define MT6373_RG_LDO_VRF18_AIF_RC7_OP_MODE_ADDR 0x1BCA +#define MT6373_RG_LDO_VRF18_AIF_RC8_OP_MODE_ADDR 0x1BCB +#define MT6373_RG_LDO_VRF18_AIF_RC9_OP_MODE_ADDR 0x1BCB +#define MT6373_RG_LDO_VRF18_AIF_RC10_OP_MODE_ADDR 0x1BCB +#define MT6373_RG_LDO_VRF18_AIF_RC11_OP_MODE_ADDR 0x1BCB +#define MT6373_RG_LDO_VRF18_AIF_RC12_OP_MODE_ADDR 0x1BCB +#define MT6373_RG_LDO_VRF18_AIF_RC13_OP_MODE_ADDR 0x1BCB +#define MT6373_RG_LDO_VRF18_AIF_HW0_OP_MODE_ADDR 0x1BCC +#define MT6373_RG_LDO_VRF18_AIF_HW1_OP_MODE_ADDR 0x1BCC +#define MT6373_RG_LDO_VRF18_AIF_HW2_OP_MODE_ADDR 0x1BCC +#define MT6373_RG_LDO_VRF18_AIF_HW3_OP_MODE_ADDR 0x1BCC +#define MT6373_RG_LDO_VRF18_AIF_HW4_OP_MODE_ADDR 0x1BCC +#define MT6373_RG_LDO_VRF18_AIF_HW5_OP_MODE_ADDR 0x1BCC +#define MT6373_RG_LDO_VRF18_AIF_HW6_OP_MODE_ADDR 0x1BCC +#define MT6373_RG_LDO_VRFIO18_AIF_ONLV_EN_ADDR 0x1BCE +#define MT6373_RG_LDO_VRFIO18_AIF_ONLV_EN_SHIFT 3 +#define MT6373_RG_LDO_VRFIO18_AIF_RC0_OP_EN_ADDR 0x1BD2 +#define MT6373_RG_LDO_VRFIO18_AIF_RC1_OP_EN_ADDR 0x1BD2 +#define MT6373_RG_LDO_VRFIO18_AIF_RC2_OP_EN_ADDR 0x1BD2 +#define MT6373_RG_LDO_VRFIO18_AIF_RC3_OP_EN_ADDR 0x1BD2 +#define MT6373_RG_LDO_VRFIO18_AIF_RC4_OP_EN_ADDR 0x1BD2 +#define MT6373_RG_LDO_VRFIO18_AIF_RC5_OP_EN_ADDR 0x1BD2 +#define MT6373_RG_LDO_VRFIO18_AIF_RC6_OP_EN_ADDR 0x1BD2 +#define MT6373_RG_LDO_VRFIO18_AIF_RC7_OP_EN_ADDR 0x1BD2 +#define MT6373_RG_LDO_VRFIO18_AIF_RC8_OP_EN_ADDR 0x1BD3 +#define MT6373_RG_LDO_VRFIO18_AIF_RC9_OP_EN_ADDR 0x1BD3 +#define MT6373_RG_LDO_VRFIO18_AIF_RC10_OP_EN_ADDR 0x1BD3 +#define MT6373_RG_LDO_VRFIO18_AIF_RC11_OP_EN_ADDR 0x1BD3 +#define MT6373_RG_LDO_VRFIO18_AIF_RC12_OP_EN_ADDR 0x1BD3 +#define MT6373_RG_LDO_VRFIO18_AIF_RC13_OP_EN_ADDR 0x1BD3 +#define MT6373_RG_LDO_VRFIO18_AIF_HW0_OP_EN_ADDR 0x1BD4 +#define MT6373_RG_LDO_VRFIO18_AIF_HW1_OP_EN_ADDR 0x1BD4 +#define MT6373_RG_LDO_VRFIO18_AIF_HW2_OP_EN_ADDR 0x1BD4 +#define MT6373_RG_LDO_VRFIO18_AIF_HW3_OP_EN_ADDR 0x1BD4 +#define MT6373_RG_LDO_VRFIO18_AIF_HW4_OP_EN_ADDR 0x1BD4 +#define MT6373_RG_LDO_VRFIO18_AIF_HW5_OP_EN_ADDR 0x1BD4 +#define MT6373_RG_LDO_VRFIO18_AIF_HW6_OP_EN_ADDR 0x1BD4 +#define MT6373_RG_LDO_VRFIO18_AIF_SW_OP_EN_ADDR 0x1BD4 +#define MT6373_RG_LDO_VRFIO18_AIF_RC0_OP_CFG_ADDR 0x1BD5 +#define MT6373_RG_LDO_VRFIO18_AIF_RC1_OP_CFG_ADDR 0x1BD5 +#define MT6373_RG_LDO_VRFIO18_AIF_RC2_OP_CFG_ADDR 0x1BD5 +#define MT6373_RG_LDO_VRFIO18_AIF_RC3_OP_CFG_ADDR 0x1BD5 +#define MT6373_RG_LDO_VRFIO18_AIF_RC4_OP_CFG_ADDR 0x1BD5 +#define MT6373_RG_LDO_VRFIO18_AIF_RC5_OP_CFG_ADDR 0x1BD5 +#define MT6373_RG_LDO_VRFIO18_AIF_RC6_OP_CFG_ADDR 0x1BD5 +#define MT6373_RG_LDO_VRFIO18_AIF_RC7_OP_CFG_ADDR 0x1BD5 +#define MT6373_RG_LDO_VRFIO18_AIF_RC8_OP_CFG_ADDR 0x1BD6 +#define MT6373_RG_LDO_VRFIO18_AIF_RC9_OP_CFG_ADDR 0x1BD6 +#define MT6373_RG_LDO_VRFIO18_AIF_RC10_OP_CFG_ADDR 0x1BD6 +#define MT6373_RG_LDO_VRFIO18_AIF_RC11_OP_CFG_ADDR 0x1BD6 +#define MT6373_RG_LDO_VRFIO18_AIF_RC12_OP_CFG_ADDR 0x1BD6 +#define MT6373_RG_LDO_VRFIO18_AIF_RC13_OP_CFG_ADDR 0x1BD6 +#define MT6373_RG_LDO_VRFIO18_AIF_HW0_OP_CFG_ADDR 0x1BD7 +#define MT6373_RG_LDO_VRFIO18_AIF_HW1_OP_CFG_ADDR 0x1BD7 +#define MT6373_RG_LDO_VRFIO18_AIF_HW2_OP_CFG_ADDR 0x1BD7 +#define MT6373_RG_LDO_VRFIO18_AIF_HW3_OP_CFG_ADDR 0x1BD7 +#define MT6373_RG_LDO_VRFIO18_AIF_HW4_OP_CFG_ADDR 0x1BD7 +#define MT6373_RG_LDO_VRFIO18_AIF_HW5_OP_CFG_ADDR 0x1BD7 +#define MT6373_RG_LDO_VRFIO18_AIF_HW6_OP_CFG_ADDR 0x1BD7 +#define MT6373_RG_LDO_VRFIO18_AIF_SW_OP_CFG_ADDR 0x1BD7 +#define MT6373_RG_LDO_VRFIO18_AIF_RC0_OP_MODE_ADDR 0x1BD8 +#define MT6373_RG_LDO_VRFIO18_AIF_RC1_OP_MODE_ADDR 0x1BD8 +#define MT6373_RG_LDO_VRFIO18_AIF_RC2_OP_MODE_ADDR 0x1BD8 +#define MT6373_RG_LDO_VRFIO18_AIF_RC3_OP_MODE_ADDR 0x1BD8 +#define MT6373_RG_LDO_VRFIO18_AIF_RC4_OP_MODE_ADDR 0x1BD8 +#define MT6373_RG_LDO_VRFIO18_AIF_RC5_OP_MODE_ADDR 0x1BD8 +#define MT6373_RG_LDO_VRFIO18_AIF_RC6_OP_MODE_ADDR 0x1BD8 +#define MT6373_RG_LDO_VRFIO18_AIF_RC7_OP_MODE_ADDR 0x1BD8 +#define MT6373_RG_LDO_VRFIO18_AIF_RC8_OP_MODE_ADDR 0x1BD9 +#define MT6373_RG_LDO_VRFIO18_AIF_RC9_OP_MODE_ADDR 0x1BD9 +#define MT6373_RG_LDO_VRFIO18_AIF_RC10_OP_MODE_ADDR 0x1BD9 +#define MT6373_RG_LDO_VRFIO18_AIF_RC11_OP_MODE_ADDR 0x1BD9 +#define MT6373_RG_LDO_VRFIO18_AIF_RC12_OP_MODE_ADDR 0x1BD9 +#define MT6373_RG_LDO_VRFIO18_AIF_RC13_OP_MODE_ADDR 0x1BD9 +#define MT6373_RG_LDO_VRFIO18_AIF_HW0_OP_MODE_ADDR 0x1BDA +#define MT6373_RG_LDO_VRFIO18_AIF_HW1_OP_MODE_ADDR 0x1BDA +#define MT6373_RG_LDO_VRFIO18_AIF_HW2_OP_MODE_ADDR 0x1BDA +#define MT6373_RG_LDO_VRFIO18_AIF_HW3_OP_MODE_ADDR 0x1BDA +#define MT6373_RG_LDO_VRFIO18_AIF_HW4_OP_MODE_ADDR 0x1BDA +#define MT6373_RG_LDO_VRFIO18_AIF_HW5_OP_MODE_ADDR 0x1BDA +#define MT6373_RG_LDO_VRFIO18_AIF_HW6_OP_MODE_ADDR 0x1BDA +#define MT6373_RG_LDO_VCN33_1_ONLV_EN_ADDR 0x1C08 +#define MT6373_RG_LDO_VCN33_1_ONLV_EN_SHIFT 3 +#define MT6373_RG_LDO_VCN33_1_RC0_OP_EN_ADDR 0x1C0C +#define MT6373_RG_LDO_VCN33_1_RC1_OP_EN_ADDR 0x1C0C +#define MT6373_RG_LDO_VCN33_1_RC2_OP_EN_ADDR 0x1C0C +#define MT6373_RG_LDO_VCN33_1_RC3_OP_EN_ADDR 0x1C0C +#define MT6373_RG_LDO_VCN33_1_RC4_OP_EN_ADDR 0x1C0C +#define MT6373_RG_LDO_VCN33_1_RC5_OP_EN_ADDR 0x1C0C +#define MT6373_RG_LDO_VCN33_1_RC6_OP_EN_ADDR 0x1C0C +#define MT6373_RG_LDO_VCN33_1_RC7_OP_EN_ADDR 0x1C0C +#define MT6373_RG_LDO_VCN33_1_RC8_OP_EN_ADDR 0x1C0D +#define MT6373_RG_LDO_VCN33_1_RC9_OP_EN_ADDR 0x1C0D +#define MT6373_RG_LDO_VCN33_1_RC10_OP_EN_ADDR 0x1C0D +#define MT6373_RG_LDO_VCN33_1_RC11_OP_EN_ADDR 0x1C0D +#define MT6373_RG_LDO_VCN33_1_RC12_OP_EN_ADDR 0x1C0D +#define MT6373_RG_LDO_VCN33_1_RC13_OP_EN_ADDR 0x1C0D +#define MT6373_RG_LDO_VCN33_1_HW0_OP_EN_ADDR 0x1C0E +#define MT6373_RG_LDO_VCN33_1_HW1_OP_EN_ADDR 0x1C0E +#define MT6373_RG_LDO_VCN33_1_HW2_OP_EN_ADDR 0x1C0E +#define MT6373_RG_LDO_VCN33_1_HW3_OP_EN_ADDR 0x1C0E +#define MT6373_RG_LDO_VCN33_1_HW4_OP_EN_ADDR 0x1C0E +#define MT6373_RG_LDO_VCN33_1_HW5_OP_EN_ADDR 0x1C0E +#define MT6373_RG_LDO_VCN33_1_HW6_OP_EN_ADDR 0x1C0E +#define MT6373_RG_LDO_VCN33_1_SW_OP_EN_ADDR 0x1C0E +#define MT6373_RG_LDO_VCN33_1_RC0_OP_CFG_ADDR 0x1C0F +#define MT6373_RG_LDO_VCN33_1_RC1_OP_CFG_ADDR 0x1C0F +#define MT6373_RG_LDO_VCN33_1_RC2_OP_CFG_ADDR 0x1C0F +#define MT6373_RG_LDO_VCN33_1_RC3_OP_CFG_ADDR 0x1C0F +#define MT6373_RG_LDO_VCN33_1_RC4_OP_CFG_ADDR 0x1C0F +#define MT6373_RG_LDO_VCN33_1_RC5_OP_CFG_ADDR 0x1C0F +#define MT6373_RG_LDO_VCN33_1_RC6_OP_CFG_ADDR 0x1C0F +#define MT6373_RG_LDO_VCN33_1_RC7_OP_CFG_ADDR 0x1C0F +#define MT6373_RG_LDO_VCN33_1_RC8_OP_CFG_ADDR 0x1C10 +#define MT6373_RG_LDO_VCN33_1_RC9_OP_CFG_ADDR 0x1C10 +#define MT6373_RG_LDO_VCN33_1_RC10_OP_CFG_ADDR 0x1C10 +#define MT6373_RG_LDO_VCN33_1_RC11_OP_CFG_ADDR 0x1C10 +#define MT6373_RG_LDO_VCN33_1_RC12_OP_CFG_ADDR 0x1C10 +#define MT6373_RG_LDO_VCN33_1_RC13_OP_CFG_ADDR 0x1C10 +#define MT6373_RG_LDO_VCN33_1_HW0_OP_CFG_ADDR 0x1C11 +#define MT6373_RG_LDO_VCN33_1_HW1_OP_CFG_ADDR 0x1C11 +#define MT6373_RG_LDO_VCN33_1_HW2_OP_CFG_ADDR 0x1C11 +#define MT6373_RG_LDO_VCN33_1_HW3_OP_CFG_ADDR 0x1C11 +#define MT6373_RG_LDO_VCN33_1_HW4_OP_CFG_ADDR 0x1C11 +#define MT6373_RG_LDO_VCN33_1_HW5_OP_CFG_ADDR 0x1C11 +#define MT6373_RG_LDO_VCN33_1_HW6_OP_CFG_ADDR 0x1C11 +#define MT6373_RG_LDO_VCN33_1_SW_OP_CFG_ADDR 0x1C11 +#define MT6373_RG_LDO_VCN33_1_RC0_OP_MODE_ADDR 0x1C12 +#define MT6373_RG_LDO_VCN33_1_RC1_OP_MODE_ADDR 0x1C12 +#define MT6373_RG_LDO_VCN33_1_RC2_OP_MODE_ADDR 0x1C12 +#define MT6373_RG_LDO_VCN33_1_RC3_OP_MODE_ADDR 0x1C12 +#define MT6373_RG_LDO_VCN33_1_RC4_OP_MODE_ADDR 0x1C12 +#define MT6373_RG_LDO_VCN33_1_RC5_OP_MODE_ADDR 0x1C12 +#define MT6373_RG_LDO_VCN33_1_RC6_OP_MODE_ADDR 0x1C12 +#define MT6373_RG_LDO_VCN33_1_RC7_OP_MODE_ADDR 0x1C12 +#define MT6373_RG_LDO_VCN33_1_RC8_OP_MODE_ADDR 0x1C13 +#define MT6373_RG_LDO_VCN33_1_RC9_OP_MODE_ADDR 0x1C13 +#define MT6373_RG_LDO_VCN33_1_RC10_OP_MODE_ADDR 0x1C13 +#define MT6373_RG_LDO_VCN33_1_RC11_OP_MODE_ADDR 0x1C13 +#define MT6373_RG_LDO_VCN33_1_RC12_OP_MODE_ADDR 0x1C13 +#define MT6373_RG_LDO_VCN33_1_RC13_OP_MODE_ADDR 0x1C13 +#define MT6373_RG_LDO_VCN33_1_HW0_OP_MODE_ADDR 0x1C14 +#define MT6373_RG_LDO_VCN33_1_HW1_OP_MODE_ADDR 0x1C14 +#define MT6373_RG_LDO_VCN33_1_HW2_OP_MODE_ADDR 0x1C14 +#define MT6373_RG_LDO_VCN33_1_HW3_OP_MODE_ADDR 0x1C14 +#define MT6373_RG_LDO_VCN33_1_HW4_OP_MODE_ADDR 0x1C14 +#define MT6373_RG_LDO_VCN33_1_HW5_OP_MODE_ADDR 0x1C14 +#define MT6373_RG_LDO_VCN33_1_HW6_OP_MODE_ADDR 0x1C14 +#define MT6373_RG_LDO_VCN33_2_ONLV_EN_ADDR 0x1C16 +#define MT6373_RG_LDO_VCN33_2_ONLV_EN_SHIFT 3 +#define MT6373_RG_LDO_VCN33_2_RC0_OP_EN_ADDR 0x1C1A +#define MT6373_RG_LDO_VCN33_2_RC1_OP_EN_ADDR 0x1C1A +#define MT6373_RG_LDO_VCN33_2_RC2_OP_EN_ADDR 0x1C1A +#define MT6373_RG_LDO_VCN33_2_RC3_OP_EN_ADDR 0x1C1A +#define MT6373_RG_LDO_VCN33_2_RC4_OP_EN_ADDR 0x1C1A +#define MT6373_RG_LDO_VCN33_2_RC5_OP_EN_ADDR 0x1C1A +#define MT6373_RG_LDO_VCN33_2_RC6_OP_EN_ADDR 0x1C1A +#define MT6373_RG_LDO_VCN33_2_RC7_OP_EN_ADDR 0x1C1A +#define MT6373_RG_LDO_VCN33_2_RC8_OP_EN_ADDR 0x1C1B +#define MT6373_RG_LDO_VCN33_2_RC9_OP_EN_ADDR 0x1C1B +#define MT6373_RG_LDO_VCN33_2_RC10_OP_EN_ADDR 0x1C1B +#define MT6373_RG_LDO_VCN33_2_RC11_OP_EN_ADDR 0x1C1B +#define MT6373_RG_LDO_VCN33_2_RC12_OP_EN_ADDR 0x1C1B +#define MT6373_RG_LDO_VCN33_2_RC13_OP_EN_ADDR 0x1C1B +#define MT6373_RG_LDO_VCN33_2_HW0_OP_EN_ADDR 0x1C1C +#define MT6373_RG_LDO_VCN33_2_HW1_OP_EN_ADDR 0x1C1C +#define MT6373_RG_LDO_VCN33_2_HW2_OP_EN_ADDR 0x1C1C +#define MT6373_RG_LDO_VCN33_2_HW3_OP_EN_ADDR 0x1C1C +#define MT6373_RG_LDO_VCN33_2_HW4_OP_EN_ADDR 0x1C1C +#define MT6373_RG_LDO_VCN33_2_HW5_OP_EN_ADDR 0x1C1C +#define MT6373_RG_LDO_VCN33_2_HW6_OP_EN_ADDR 0x1C1C +#define MT6373_RG_LDO_VCN33_2_SW_OP_EN_ADDR 0x1C1C +#define MT6373_RG_LDO_VCN33_2_RC0_OP_CFG_ADDR 0x1C1D +#define MT6373_RG_LDO_VCN33_2_RC1_OP_CFG_ADDR 0x1C1D +#define MT6373_RG_LDO_VCN33_2_RC2_OP_CFG_ADDR 0x1C1D +#define MT6373_RG_LDO_VCN33_2_RC3_OP_CFG_ADDR 0x1C1D +#define MT6373_RG_LDO_VCN33_2_RC4_OP_CFG_ADDR 0x1C1D +#define MT6373_RG_LDO_VCN33_2_RC5_OP_CFG_ADDR 0x1C1D +#define MT6373_RG_LDO_VCN33_2_RC6_OP_CFG_ADDR 0x1C1D +#define MT6373_RG_LDO_VCN33_2_RC7_OP_CFG_ADDR 0x1C1D +#define MT6373_RG_LDO_VCN33_2_RC8_OP_CFG_ADDR 0x1C1E +#define MT6373_RG_LDO_VCN33_2_RC9_OP_CFG_ADDR 0x1C1E +#define MT6373_RG_LDO_VCN33_2_RC10_OP_CFG_ADDR 0x1C1E +#define MT6373_RG_LDO_VCN33_2_RC11_OP_CFG_ADDR 0x1C1E +#define MT6373_RG_LDO_VCN33_2_RC12_OP_CFG_ADDR 0x1C1E +#define MT6373_RG_LDO_VCN33_2_RC13_OP_CFG_ADDR 0x1C1E +#define MT6373_RG_LDO_VCN33_2_HW0_OP_CFG_ADDR 0x1C1F +#define MT6373_RG_LDO_VCN33_2_HW1_OP_CFG_ADDR 0x1C1F +#define MT6373_RG_LDO_VCN33_2_HW2_OP_CFG_ADDR 0x1C1F +#define MT6373_RG_LDO_VCN33_2_HW3_OP_CFG_ADDR 0x1C1F +#define MT6373_RG_LDO_VCN33_2_HW4_OP_CFG_ADDR 0x1C1F +#define MT6373_RG_LDO_VCN33_2_HW5_OP_CFG_ADDR 0x1C1F +#define MT6373_RG_LDO_VCN33_2_HW6_OP_CFG_ADDR 0x1C1F +#define MT6373_RG_LDO_VCN33_2_SW_OP_CFG_ADDR 0x1C1F +#define MT6373_RG_LDO_VCN33_2_RC0_OP_MODE_ADDR 0x1C20 +#define MT6373_RG_LDO_VCN33_2_RC1_OP_MODE_ADDR 0x1C20 +#define MT6373_RG_LDO_VCN33_2_RC2_OP_MODE_ADDR 0x1C20 +#define MT6373_RG_LDO_VCN33_2_RC3_OP_MODE_ADDR 0x1C20 +#define MT6373_RG_LDO_VCN33_2_RC4_OP_MODE_ADDR 0x1C20 +#define MT6373_RG_LDO_VCN33_2_RC5_OP_MODE_ADDR 0x1C20 +#define MT6373_RG_LDO_VCN33_2_RC6_OP_MODE_ADDR 0x1C20 +#define MT6373_RG_LDO_VCN33_2_RC7_OP_MODE_ADDR 0x1C20 +#define MT6373_RG_LDO_VCN33_2_RC8_OP_MODE_ADDR 0x1C21 +#define MT6373_RG_LDO_VCN33_2_RC9_OP_MODE_ADDR 0x1C21 +#define MT6373_RG_LDO_VCN33_2_RC10_OP_MODE_ADDR 0x1C21 +#define MT6373_RG_LDO_VCN33_2_RC11_OP_MODE_ADDR 0x1C21 +#define MT6373_RG_LDO_VCN33_2_RC12_OP_MODE_ADDR 0x1C21 +#define MT6373_RG_LDO_VCN33_2_RC13_OP_MODE_ADDR 0x1C21 +#define MT6373_RG_LDO_VCN33_2_HW0_OP_MODE_ADDR 0x1C22 +#define MT6373_RG_LDO_VCN33_2_HW1_OP_MODE_ADDR 0x1C22 +#define MT6373_RG_LDO_VCN33_2_HW2_OP_MODE_ADDR 0x1C22 +#define MT6373_RG_LDO_VCN33_2_HW3_OP_MODE_ADDR 0x1C22 +#define MT6373_RG_LDO_VCN33_2_HW4_OP_MODE_ADDR 0x1C22 +#define MT6373_RG_LDO_VCN33_2_HW5_OP_MODE_ADDR 0x1C22 +#define MT6373_RG_LDO_VCN33_2_HW6_OP_MODE_ADDR 0x1C22 +#define MT6373_RG_LDO_VCN33_3_ONLV_EN_ADDR 0x1C24 +#define MT6373_RG_LDO_VCN33_3_ONLV_EN_SHIFT 3 +#define MT6373_RG_LDO_VCN33_3_RC0_OP_EN_ADDR 0x1C28 +#define MT6373_RG_LDO_VCN33_3_RC1_OP_EN_ADDR 0x1C28 +#define MT6373_RG_LDO_VCN33_3_RC2_OP_EN_ADDR 0x1C28 +#define MT6373_RG_LDO_VCN33_3_RC3_OP_EN_ADDR 0x1C28 +#define MT6373_RG_LDO_VCN33_3_RC4_OP_EN_ADDR 0x1C28 +#define MT6373_RG_LDO_VCN33_3_RC5_OP_EN_ADDR 0x1C28 +#define MT6373_RG_LDO_VCN33_3_RC6_OP_EN_ADDR 0x1C28 +#define MT6373_RG_LDO_VCN33_3_RC7_OP_EN_ADDR 0x1C28 +#define MT6373_RG_LDO_VCN33_3_RC8_OP_EN_ADDR 0x1C29 +#define MT6373_RG_LDO_VCN33_3_RC9_OP_EN_ADDR 0x1C29 +#define MT6373_RG_LDO_VCN33_3_RC10_OP_EN_ADDR 0x1C29 +#define MT6373_RG_LDO_VCN33_3_RC11_OP_EN_ADDR 0x1C29 +#define MT6373_RG_LDO_VCN33_3_RC12_OP_EN_ADDR 0x1C29 +#define MT6373_RG_LDO_VCN33_3_RC13_OP_EN_ADDR 0x1C29 +#define MT6373_RG_LDO_VCN33_3_HW0_OP_EN_ADDR 0x1C2A +#define MT6373_RG_LDO_VCN33_3_HW1_OP_EN_ADDR 0x1C2A +#define MT6373_RG_LDO_VCN33_3_HW2_OP_EN_ADDR 0x1C2A +#define MT6373_RG_LDO_VCN33_3_HW3_OP_EN_ADDR 0x1C2A +#define MT6373_RG_LDO_VCN33_3_HW4_OP_EN_ADDR 0x1C2A +#define MT6373_RG_LDO_VCN33_3_HW5_OP_EN_ADDR 0x1C2A +#define MT6373_RG_LDO_VCN33_3_HW6_OP_EN_ADDR 0x1C2A +#define MT6373_RG_LDO_VCN33_3_SW_OP_EN_ADDR 0x1C2A +#define MT6373_RG_LDO_VCN33_3_RC0_OP_CFG_ADDR 0x1C2B +#define MT6373_RG_LDO_VCN33_3_RC1_OP_CFG_ADDR 0x1C2B +#define MT6373_RG_LDO_VCN33_3_RC2_OP_CFG_ADDR 0x1C2B +#define MT6373_RG_LDO_VCN33_3_RC3_OP_CFG_ADDR 0x1C2B +#define MT6373_RG_LDO_VCN33_3_RC4_OP_CFG_ADDR 0x1C2B +#define MT6373_RG_LDO_VCN33_3_RC5_OP_CFG_ADDR 0x1C2B +#define MT6373_RG_LDO_VCN33_3_RC6_OP_CFG_ADDR 0x1C2B +#define MT6373_RG_LDO_VCN33_3_RC7_OP_CFG_ADDR 0x1C2B +#define MT6373_RG_LDO_VCN33_3_RC8_OP_CFG_ADDR 0x1C2C +#define MT6373_RG_LDO_VCN33_3_RC9_OP_CFG_ADDR 0x1C2C +#define MT6373_RG_LDO_VCN33_3_RC10_OP_CFG_ADDR 0x1C2C +#define MT6373_RG_LDO_VCN33_3_RC11_OP_CFG_ADDR 0x1C2C +#define MT6373_RG_LDO_VCN33_3_RC12_OP_CFG_ADDR 0x1C2C +#define MT6373_RG_LDO_VCN33_3_RC13_OP_CFG_ADDR 0x1C2C +#define MT6373_RG_LDO_VCN33_3_HW0_OP_CFG_ADDR 0x1C2D +#define MT6373_RG_LDO_VCN33_3_HW1_OP_CFG_ADDR 0x1C2D +#define MT6373_RG_LDO_VCN33_3_HW2_OP_CFG_ADDR 0x1C2D +#define MT6373_RG_LDO_VCN33_3_HW3_OP_CFG_ADDR 0x1C2D +#define MT6373_RG_LDO_VCN33_3_HW4_OP_CFG_ADDR 0x1C2D +#define MT6373_RG_LDO_VCN33_3_HW5_OP_CFG_ADDR 0x1C2D +#define MT6373_RG_LDO_VCN33_3_HW6_OP_CFG_ADDR 0x1C2D +#define MT6373_RG_LDO_VCN33_3_SW_OP_CFG_ADDR 0x1C2D +#define MT6373_RG_LDO_VCN33_3_RC0_OP_MODE_ADDR 0x1C2E +#define MT6373_RG_LDO_VCN33_3_RC1_OP_MODE_ADDR 0x1C2E +#define MT6373_RG_LDO_VCN33_3_RC2_OP_MODE_ADDR 0x1C2E +#define MT6373_RG_LDO_VCN33_3_RC3_OP_MODE_ADDR 0x1C2E +#define MT6373_RG_LDO_VCN33_3_RC4_OP_MODE_ADDR 0x1C2E +#define MT6373_RG_LDO_VCN33_3_RC5_OP_MODE_ADDR 0x1C2E +#define MT6373_RG_LDO_VCN33_3_RC6_OP_MODE_ADDR 0x1C2E +#define MT6373_RG_LDO_VCN33_3_RC7_OP_MODE_ADDR 0x1C2E +#define MT6373_RG_LDO_VCN33_3_RC8_OP_MODE_ADDR 0x1C2F +#define MT6373_RG_LDO_VCN33_3_RC9_OP_MODE_ADDR 0x1C2F +#define MT6373_RG_LDO_VCN33_3_RC10_OP_MODE_ADDR 0x1C2F +#define MT6373_RG_LDO_VCN33_3_RC11_OP_MODE_ADDR 0x1C2F +#define MT6373_RG_LDO_VCN33_3_RC12_OP_MODE_ADDR 0x1C2F +#define MT6373_RG_LDO_VCN33_3_RC13_OP_MODE_ADDR 0x1C2F +#define MT6373_RG_LDO_VCN33_3_HW0_OP_MODE_ADDR 0x1C30 +#define MT6373_RG_LDO_VCN33_3_HW1_OP_MODE_ADDR 0x1C30 +#define MT6373_RG_LDO_VCN33_3_HW2_OP_MODE_ADDR 0x1C30 +#define MT6373_RG_LDO_VCN33_3_HW3_OP_MODE_ADDR 0x1C30 +#define MT6373_RG_LDO_VCN33_3_HW4_OP_MODE_ADDR 0x1C30 +#define MT6373_RG_LDO_VCN33_3_HW5_OP_MODE_ADDR 0x1C30 +#define MT6373_RG_LDO_VCN33_3_HW6_OP_MODE_ADDR 0x1C30 +#define MT6373_RG_LDO_VCN18IO_ONLV_EN_ADDR 0x1C32 +#define MT6373_RG_LDO_VCN18IO_ONLV_EN_SHIFT 3 +#define MT6373_RG_LDO_VCN18IO_RC0_OP_EN_ADDR 0x1C36 +#define MT6373_RG_LDO_VCN18IO_RC1_OP_EN_ADDR 0x1C36 +#define MT6373_RG_LDO_VCN18IO_RC2_OP_EN_ADDR 0x1C36 +#define MT6373_RG_LDO_VCN18IO_RC3_OP_EN_ADDR 0x1C36 +#define MT6373_RG_LDO_VCN18IO_RC4_OP_EN_ADDR 0x1C36 +#define MT6373_RG_LDO_VCN18IO_RC5_OP_EN_ADDR 0x1C36 +#define MT6373_RG_LDO_VCN18IO_RC6_OP_EN_ADDR 0x1C36 +#define MT6373_RG_LDO_VCN18IO_RC7_OP_EN_ADDR 0x1C36 +#define MT6373_RG_LDO_VCN18IO_RC8_OP_EN_ADDR 0x1C37 +#define MT6373_RG_LDO_VCN18IO_RC9_OP_EN_ADDR 0x1C37 +#define MT6373_RG_LDO_VCN18IO_RC10_OP_EN_ADDR 0x1C37 +#define MT6373_RG_LDO_VCN18IO_RC11_OP_EN_ADDR 0x1C37 +#define MT6373_RG_LDO_VCN18IO_RC12_OP_EN_ADDR 0x1C37 +#define MT6373_RG_LDO_VCN18IO_RC13_OP_EN_ADDR 0x1C37 +#define MT6373_RG_LDO_VCN18IO_HW0_OP_EN_ADDR 0x1C38 +#define MT6373_RG_LDO_VCN18IO_HW1_OP_EN_ADDR 0x1C38 +#define MT6373_RG_LDO_VCN18IO_HW2_OP_EN_ADDR 0x1C38 +#define MT6373_RG_LDO_VCN18IO_HW3_OP_EN_ADDR 0x1C38 +#define MT6373_RG_LDO_VCN18IO_HW4_OP_EN_ADDR 0x1C38 +#define MT6373_RG_LDO_VCN18IO_HW5_OP_EN_ADDR 0x1C38 +#define MT6373_RG_LDO_VCN18IO_HW6_OP_EN_ADDR 0x1C38 +#define MT6373_RG_LDO_VCN18IO_SW_OP_EN_ADDR 0x1C38 +#define MT6373_RG_LDO_VCN18IO_RC0_OP_CFG_ADDR 0x1C39 +#define MT6373_RG_LDO_VCN18IO_RC1_OP_CFG_ADDR 0x1C39 +#define MT6373_RG_LDO_VCN18IO_RC2_OP_CFG_ADDR 0x1C39 +#define MT6373_RG_LDO_VCN18IO_RC3_OP_CFG_ADDR 0x1C39 +#define MT6373_RG_LDO_VCN18IO_RC4_OP_CFG_ADDR 0x1C39 +#define MT6373_RG_LDO_VCN18IO_RC5_OP_CFG_ADDR 0x1C39 +#define MT6373_RG_LDO_VCN18IO_RC6_OP_CFG_ADDR 0x1C39 +#define MT6373_RG_LDO_VCN18IO_RC7_OP_CFG_ADDR 0x1C39 +#define MT6373_RG_LDO_VCN18IO_RC8_OP_CFG_ADDR 0x1C3A +#define MT6373_RG_LDO_VCN18IO_RC9_OP_CFG_ADDR 0x1C3A +#define MT6373_RG_LDO_VCN18IO_RC10_OP_CFG_ADDR 0x1C3A +#define MT6373_RG_LDO_VCN18IO_RC11_OP_CFG_ADDR 0x1C3A +#define MT6373_RG_LDO_VCN18IO_RC12_OP_CFG_ADDR 0x1C3A +#define MT6373_RG_LDO_VCN18IO_RC13_OP_CFG_ADDR 0x1C3A +#define MT6373_RG_LDO_VCN18IO_HW0_OP_CFG_ADDR 0x1C3B +#define MT6373_RG_LDO_VCN18IO_HW1_OP_CFG_ADDR 0x1C3B +#define MT6373_RG_LDO_VCN18IO_HW2_OP_CFG_ADDR 0x1C3B +#define MT6373_RG_LDO_VCN18IO_HW3_OP_CFG_ADDR 0x1C3B +#define MT6373_RG_LDO_VCN18IO_HW4_OP_CFG_ADDR 0x1C3B +#define MT6373_RG_LDO_VCN18IO_HW5_OP_CFG_ADDR 0x1C3B +#define MT6373_RG_LDO_VCN18IO_HW6_OP_CFG_ADDR 0x1C3B +#define MT6373_RG_LDO_VCN18IO_SW_OP_CFG_ADDR 0x1C3B +#define MT6373_RG_LDO_VCN18IO_RC0_OP_MODE_ADDR 0x1C3C +#define MT6373_RG_LDO_VCN18IO_RC1_OP_MODE_ADDR 0x1C3C +#define MT6373_RG_LDO_VCN18IO_RC2_OP_MODE_ADDR 0x1C3C +#define MT6373_RG_LDO_VCN18IO_RC3_OP_MODE_ADDR 0x1C3C +#define MT6373_RG_LDO_VCN18IO_RC4_OP_MODE_ADDR 0x1C3C +#define MT6373_RG_LDO_VCN18IO_RC5_OP_MODE_ADDR 0x1C3C +#define MT6373_RG_LDO_VCN18IO_RC6_OP_MODE_ADDR 0x1C3C +#define MT6373_RG_LDO_VCN18IO_RC7_OP_MODE_ADDR 0x1C3C +#define MT6373_RG_LDO_VCN18IO_RC8_OP_MODE_ADDR 0x1C3D +#define MT6373_RG_LDO_VCN18IO_RC9_OP_MODE_ADDR 0x1C3D +#define MT6373_RG_LDO_VCN18IO_RC10_OP_MODE_ADDR 0x1C3D +#define MT6373_RG_LDO_VCN18IO_RC11_OP_MODE_ADDR 0x1C3D +#define MT6373_RG_LDO_VCN18IO_RC12_OP_MODE_ADDR 0x1C3D +#define MT6373_RG_LDO_VCN18IO_RC13_OP_MODE_ADDR 0x1C3D +#define MT6373_RG_LDO_VCN18IO_HW0_OP_MODE_ADDR 0x1C3E +#define MT6373_RG_LDO_VCN18IO_HW1_OP_MODE_ADDR 0x1C3E +#define MT6373_RG_LDO_VCN18IO_HW2_OP_MODE_ADDR 0x1C3E +#define MT6373_RG_LDO_VCN18IO_HW3_OP_MODE_ADDR 0x1C3E +#define MT6373_RG_LDO_VCN18IO_HW4_OP_MODE_ADDR 0x1C3E +#define MT6373_RG_LDO_VCN18IO_HW5_OP_MODE_ADDR 0x1C3E +#define MT6373_RG_LDO_VCN18IO_HW6_OP_MODE_ADDR 0x1C3E +#define MT6373_RG_LDO_VRF09_AIF_ONLV_EN_ADDR 0x1C40 +#define MT6373_RG_LDO_VRF09_AIF_ONLV_EN_SHIFT 3 +#define MT6373_RG_LDO_VRF09_AIF_RC0_OP_EN_ADDR 0x1C44 +#define MT6373_RG_LDO_VRF09_AIF_RC1_OP_EN_ADDR 0x1C44 +#define MT6373_RG_LDO_VRF09_AIF_RC2_OP_EN_ADDR 0x1C44 +#define MT6373_RG_LDO_VRF09_AIF_RC3_OP_EN_ADDR 0x1C44 +#define MT6373_RG_LDO_VRF09_AIF_RC4_OP_EN_ADDR 0x1C44 +#define MT6373_RG_LDO_VRF09_AIF_RC5_OP_EN_ADDR 0x1C44 +#define MT6373_RG_LDO_VRF09_AIF_RC6_OP_EN_ADDR 0x1C44 +#define MT6373_RG_LDO_VRF09_AIF_RC7_OP_EN_ADDR 0x1C44 +#define MT6373_RG_LDO_VRF09_AIF_RC8_OP_EN_ADDR 0x1C45 +#define MT6373_RG_LDO_VRF09_AIF_RC9_OP_EN_ADDR 0x1C45 +#define MT6373_RG_LDO_VRF09_AIF_RC10_OP_EN_ADDR 0x1C45 +#define MT6373_RG_LDO_VRF09_AIF_RC11_OP_EN_ADDR 0x1C45 +#define MT6373_RG_LDO_VRF09_AIF_RC12_OP_EN_ADDR 0x1C45 +#define MT6373_RG_LDO_VRF09_AIF_RC13_OP_EN_ADDR 0x1C45 +#define MT6373_RG_LDO_VRF09_AIF_HW0_OP_EN_ADDR 0x1C46 +#define MT6373_RG_LDO_VRF09_AIF_HW1_OP_EN_ADDR 0x1C46 +#define MT6373_RG_LDO_VRF09_AIF_HW2_OP_EN_ADDR 0x1C46 +#define MT6373_RG_LDO_VRF09_AIF_HW3_OP_EN_ADDR 0x1C46 +#define MT6373_RG_LDO_VRF09_AIF_HW4_OP_EN_ADDR 0x1C46 +#define MT6373_RG_LDO_VRF09_AIF_HW5_OP_EN_ADDR 0x1C46 +#define MT6373_RG_LDO_VRF09_AIF_HW6_OP_EN_ADDR 0x1C46 +#define MT6373_RG_LDO_VRF09_AIF_SW_OP_EN_ADDR 0x1C46 +#define MT6373_RG_LDO_VRF09_AIF_RC0_OP_CFG_ADDR 0x1C47 +#define MT6373_RG_LDO_VRF09_AIF_RC1_OP_CFG_ADDR 0x1C47 +#define MT6373_RG_LDO_VRF09_AIF_RC2_OP_CFG_ADDR 0x1C47 +#define MT6373_RG_LDO_VRF09_AIF_RC3_OP_CFG_ADDR 0x1C47 +#define MT6373_RG_LDO_VRF09_AIF_RC4_OP_CFG_ADDR 0x1C47 +#define MT6373_RG_LDO_VRF09_AIF_RC5_OP_CFG_ADDR 0x1C47 +#define MT6373_RG_LDO_VRF09_AIF_RC6_OP_CFG_ADDR 0x1C47 +#define MT6373_RG_LDO_VRF09_AIF_RC7_OP_CFG_ADDR 0x1C47 +#define MT6373_RG_LDO_VRF09_AIF_RC8_OP_CFG_ADDR 0x1C48 +#define MT6373_RG_LDO_VRF09_AIF_RC9_OP_CFG_ADDR 0x1C48 +#define MT6373_RG_LDO_VRF09_AIF_RC10_OP_CFG_ADDR 0x1C48 +#define MT6373_RG_LDO_VRF09_AIF_RC11_OP_CFG_ADDR 0x1C48 +#define MT6373_RG_LDO_VRF09_AIF_RC12_OP_CFG_ADDR 0x1C48 +#define MT6373_RG_LDO_VRF09_AIF_RC13_OP_CFG_ADDR 0x1C48 +#define MT6373_RG_LDO_VRF09_AIF_HW0_OP_CFG_ADDR 0x1C49 +#define MT6373_RG_LDO_VRF09_AIF_HW1_OP_CFG_ADDR 0x1C49 +#define MT6373_RG_LDO_VRF09_AIF_HW2_OP_CFG_ADDR 0x1C49 +#define MT6373_RG_LDO_VRF09_AIF_HW3_OP_CFG_ADDR 0x1C49 +#define MT6373_RG_LDO_VRF09_AIF_HW4_OP_CFG_ADDR 0x1C49 +#define MT6373_RG_LDO_VRF09_AIF_HW5_OP_CFG_ADDR 0x1C49 +#define MT6373_RG_LDO_VRF09_AIF_HW6_OP_CFG_ADDR 0x1C49 +#define MT6373_RG_LDO_VRF09_AIF_SW_OP_CFG_ADDR 0x1C49 +#define MT6373_RG_LDO_VRF09_AIF_RC0_OP_MODE_ADDR 0x1C4A +#define MT6373_RG_LDO_VRF09_AIF_RC1_OP_MODE_ADDR 0x1C4A +#define MT6373_RG_LDO_VRF09_AIF_RC2_OP_MODE_ADDR 0x1C4A +#define MT6373_RG_LDO_VRF09_AIF_RC3_OP_MODE_ADDR 0x1C4A +#define MT6373_RG_LDO_VRF09_AIF_RC4_OP_MODE_ADDR 0x1C4A +#define MT6373_RG_LDO_VRF09_AIF_RC5_OP_MODE_ADDR 0x1C4A +#define MT6373_RG_LDO_VRF09_AIF_RC6_OP_MODE_ADDR 0x1C4A +#define MT6373_RG_LDO_VRF09_AIF_RC7_OP_MODE_ADDR 0x1C4A +#define MT6373_RG_LDO_VRF09_AIF_RC8_OP_MODE_ADDR 0x1C4B +#define MT6373_RG_LDO_VRF09_AIF_RC9_OP_MODE_ADDR 0x1C4B +#define MT6373_RG_LDO_VRF09_AIF_RC10_OP_MODE_ADDR 0x1C4B +#define MT6373_RG_LDO_VRF09_AIF_RC11_OP_MODE_ADDR 0x1C4B +#define MT6373_RG_LDO_VRF09_AIF_RC12_OP_MODE_ADDR 0x1C4B +#define MT6373_RG_LDO_VRF09_AIF_RC13_OP_MODE_ADDR 0x1C4B +#define MT6373_RG_LDO_VRF09_AIF_HW0_OP_MODE_ADDR 0x1C4C +#define MT6373_RG_LDO_VRF09_AIF_HW1_OP_MODE_ADDR 0x1C4C +#define MT6373_RG_LDO_VRF09_AIF_HW2_OP_MODE_ADDR 0x1C4C +#define MT6373_RG_LDO_VRF09_AIF_HW3_OP_MODE_ADDR 0x1C4C +#define MT6373_RG_LDO_VRF09_AIF_HW4_OP_MODE_ADDR 0x1C4C +#define MT6373_RG_LDO_VRF09_AIF_HW5_OP_MODE_ADDR 0x1C4C +#define MT6373_RG_LDO_VRF09_AIF_HW6_OP_MODE_ADDR 0x1C4C +#define MT6373_RG_LDO_VRF12_AIF_ONLV_EN_ADDR 0x1C4E +#define MT6373_RG_LDO_VRF12_AIF_ONLV_EN_SHIFT 3 +#define MT6373_RG_LDO_VRF12_AIF_RC0_OP_EN_ADDR 0x1C52 +#define MT6373_RG_LDO_VRF12_AIF_RC1_OP_EN_ADDR 0x1C52 +#define MT6373_RG_LDO_VRF12_AIF_RC2_OP_EN_ADDR 0x1C52 +#define MT6373_RG_LDO_VRF12_AIF_RC3_OP_EN_ADDR 0x1C52 +#define MT6373_RG_LDO_VRF12_AIF_RC4_OP_EN_ADDR 0x1C52 +#define MT6373_RG_LDO_VRF12_AIF_RC5_OP_EN_ADDR 0x1C52 +#define MT6373_RG_LDO_VRF12_AIF_RC6_OP_EN_ADDR 0x1C52 +#define MT6373_RG_LDO_VRF12_AIF_RC7_OP_EN_ADDR 0x1C52 +#define MT6373_RG_LDO_VRF12_AIF_RC8_OP_EN_ADDR 0x1C53 +#define MT6373_RG_LDO_VRF12_AIF_RC9_OP_EN_ADDR 0x1C53 +#define MT6373_RG_LDO_VRF12_AIF_RC10_OP_EN_ADDR 0x1C53 +#define MT6373_RG_LDO_VRF12_AIF_RC11_OP_EN_ADDR 0x1C53 +#define MT6373_RG_LDO_VRF12_AIF_RC12_OP_EN_ADDR 0x1C53 +#define MT6373_RG_LDO_VRF12_AIF_RC13_OP_EN_ADDR 0x1C53 +#define MT6373_RG_LDO_VRF12_AIF_HW0_OP_EN_ADDR 0x1C54 +#define MT6373_RG_LDO_VRF12_AIF_HW1_OP_EN_ADDR 0x1C54 +#define MT6373_RG_LDO_VRF12_AIF_HW2_OP_EN_ADDR 0x1C54 +#define MT6373_RG_LDO_VRF12_AIF_HW3_OP_EN_ADDR 0x1C54 +#define MT6373_RG_LDO_VRF12_AIF_HW4_OP_EN_ADDR 0x1C54 +#define MT6373_RG_LDO_VRF12_AIF_HW5_OP_EN_ADDR 0x1C54 +#define MT6373_RG_LDO_VRF12_AIF_HW6_OP_EN_ADDR 0x1C54 +#define MT6373_RG_LDO_VRF12_AIF_SW_OP_EN_ADDR 0x1C54 +#define MT6373_RG_LDO_VRF12_AIF_RC0_OP_CFG_ADDR 0x1C55 +#define MT6373_RG_LDO_VRF12_AIF_RC1_OP_CFG_ADDR 0x1C55 +#define MT6373_RG_LDO_VRF12_AIF_RC2_OP_CFG_ADDR 0x1C55 +#define MT6373_RG_LDO_VRF12_AIF_RC3_OP_CFG_ADDR 0x1C55 +#define MT6373_RG_LDO_VRF12_AIF_RC4_OP_CFG_ADDR 0x1C55 +#define MT6373_RG_LDO_VRF12_AIF_RC5_OP_CFG_ADDR 0x1C55 +#define MT6373_RG_LDO_VRF12_AIF_RC6_OP_CFG_ADDR 0x1C55 +#define MT6373_RG_LDO_VRF12_AIF_RC7_OP_CFG_ADDR 0x1C55 +#define MT6373_RG_LDO_VRF12_AIF_RC8_OP_CFG_ADDR 0x1C56 +#define MT6373_RG_LDO_VRF12_AIF_RC9_OP_CFG_ADDR 0x1C56 +#define MT6373_RG_LDO_VRF12_AIF_RC10_OP_CFG_ADDR 0x1C56 +#define MT6373_RG_LDO_VRF12_AIF_RC11_OP_CFG_ADDR 0x1C56 +#define MT6373_RG_LDO_VRF12_AIF_RC12_OP_CFG_ADDR 0x1C56 +#define MT6373_RG_LDO_VRF12_AIF_RC13_OP_CFG_ADDR 0x1C56 +#define MT6373_RG_LDO_VRF12_AIF_HW0_OP_CFG_ADDR 0x1C57 +#define MT6373_RG_LDO_VRF12_AIF_HW1_OP_CFG_ADDR 0x1C57 +#define MT6373_RG_LDO_VRF12_AIF_HW2_OP_CFG_ADDR 0x1C57 +#define MT6373_RG_LDO_VRF12_AIF_HW3_OP_CFG_ADDR 0x1C57 +#define MT6373_RG_LDO_VRF12_AIF_HW4_OP_CFG_ADDR 0x1C57 +#define MT6373_RG_LDO_VRF12_AIF_HW5_OP_CFG_ADDR 0x1C57 +#define MT6373_RG_LDO_VRF12_AIF_HW6_OP_CFG_ADDR 0x1C57 +#define MT6373_RG_LDO_VRF12_AIF_SW_OP_CFG_ADDR 0x1C57 +#define MT6373_RG_LDO_VRF12_AIF_RC0_OP_MODE_ADDR 0x1C58 +#define MT6373_RG_LDO_VRF12_AIF_RC1_OP_MODE_ADDR 0x1C58 +#define MT6373_RG_LDO_VRF12_AIF_RC2_OP_MODE_ADDR 0x1C58 +#define MT6373_RG_LDO_VRF12_AIF_RC3_OP_MODE_ADDR 0x1C58 +#define MT6373_RG_LDO_VRF12_AIF_RC4_OP_MODE_ADDR 0x1C58 +#define MT6373_RG_LDO_VRF12_AIF_RC5_OP_MODE_ADDR 0x1C58 +#define MT6373_RG_LDO_VRF12_AIF_RC6_OP_MODE_ADDR 0x1C58 +#define MT6373_RG_LDO_VRF12_AIF_RC7_OP_MODE_ADDR 0x1C58 +#define MT6373_RG_LDO_VRF12_AIF_RC8_OP_MODE_ADDR 0x1C59 +#define MT6373_RG_LDO_VRF12_AIF_RC9_OP_MODE_ADDR 0x1C59 +#define MT6373_RG_LDO_VRF12_AIF_RC10_OP_MODE_ADDR 0x1C59 +#define MT6373_RG_LDO_VRF12_AIF_RC11_OP_MODE_ADDR 0x1C59 +#define MT6373_RG_LDO_VRF12_AIF_RC12_OP_MODE_ADDR 0x1C59 +#define MT6373_RG_LDO_VRF12_AIF_RC13_OP_MODE_ADDR 0x1C59 +#define MT6373_RG_LDO_VRF12_AIF_HW0_OP_MODE_ADDR 0x1C5A +#define MT6373_RG_LDO_VRF12_AIF_HW1_OP_MODE_ADDR 0x1C5A +#define MT6373_RG_LDO_VRF12_AIF_HW2_OP_MODE_ADDR 0x1C5A +#define MT6373_RG_LDO_VRF12_AIF_HW3_OP_MODE_ADDR 0x1C5A +#define MT6373_RG_LDO_VRF12_AIF_HW4_OP_MODE_ADDR 0x1C5A +#define MT6373_RG_LDO_VRF12_AIF_HW5_OP_MODE_ADDR 0x1C5A +#define MT6373_RG_LDO_VRF12_AIF_HW6_OP_MODE_ADDR 0x1C5A +#define MT6373_RG_LDO_VANT18_ONLV_EN_ADDR 0x1C88 +#define MT6373_RG_LDO_VANT18_ONLV_EN_SHIFT 3 +#define MT6373_RG_LDO_VANT18_RC0_OP_EN_ADDR 0x1C8C +#define MT6373_RG_LDO_VANT18_RC1_OP_EN_ADDR 0x1C8C +#define MT6373_RG_LDO_VANT18_RC2_OP_EN_ADDR 0x1C8C +#define MT6373_RG_LDO_VANT18_RC3_OP_EN_ADDR 0x1C8C +#define MT6373_RG_LDO_VANT18_RC4_OP_EN_ADDR 0x1C8C +#define MT6373_RG_LDO_VANT18_RC5_OP_EN_ADDR 0x1C8C +#define MT6373_RG_LDO_VANT18_RC6_OP_EN_ADDR 0x1C8C +#define MT6373_RG_LDO_VANT18_RC7_OP_EN_ADDR 0x1C8C +#define MT6373_RG_LDO_VANT18_RC8_OP_EN_ADDR 0x1C8D +#define MT6373_RG_LDO_VANT18_RC9_OP_EN_ADDR 0x1C8D +#define MT6373_RG_LDO_VANT18_RC10_OP_EN_ADDR 0x1C8D +#define MT6373_RG_LDO_VANT18_RC11_OP_EN_ADDR 0x1C8D +#define MT6373_RG_LDO_VANT18_RC12_OP_EN_ADDR 0x1C8D +#define MT6373_RG_LDO_VANT18_RC13_OP_EN_ADDR 0x1C8D +#define MT6373_RG_LDO_VANT18_HW0_OP_EN_ADDR 0x1C8E +#define MT6373_RG_LDO_VANT18_HW1_OP_EN_ADDR 0x1C8E +#define MT6373_RG_LDO_VANT18_HW2_OP_EN_ADDR 0x1C8E +#define MT6373_RG_LDO_VANT18_HW3_OP_EN_ADDR 0x1C8E +#define MT6373_RG_LDO_VANT18_HW4_OP_EN_ADDR 0x1C8E +#define MT6373_RG_LDO_VANT18_HW5_OP_EN_ADDR 0x1C8E +#define MT6373_RG_LDO_VANT18_HW6_OP_EN_ADDR 0x1C8E +#define MT6373_RG_LDO_VANT18_SW_OP_EN_ADDR 0x1C8E +#define MT6373_RG_LDO_VANT18_RC0_OP_CFG_ADDR 0x1C8F +#define MT6373_RG_LDO_VANT18_RC1_OP_CFG_ADDR 0x1C8F +#define MT6373_RG_LDO_VANT18_RC2_OP_CFG_ADDR 0x1C8F +#define MT6373_RG_LDO_VANT18_RC3_OP_CFG_ADDR 0x1C8F +#define MT6373_RG_LDO_VANT18_RC4_OP_CFG_ADDR 0x1C8F +#define MT6373_RG_LDO_VANT18_RC5_OP_CFG_ADDR 0x1C8F +#define MT6373_RG_LDO_VANT18_RC6_OP_CFG_ADDR 0x1C8F +#define MT6373_RG_LDO_VANT18_RC7_OP_CFG_ADDR 0x1C8F +#define MT6373_RG_LDO_VANT18_RC8_OP_CFG_ADDR 0x1C90 +#define MT6373_RG_LDO_VANT18_RC9_OP_CFG_ADDR 0x1C90 +#define MT6373_RG_LDO_VANT18_RC10_OP_CFG_ADDR 0x1C90 +#define MT6373_RG_LDO_VANT18_RC11_OP_CFG_ADDR 0x1C90 +#define MT6373_RG_LDO_VANT18_RC12_OP_CFG_ADDR 0x1C90 +#define MT6373_RG_LDO_VANT18_RC13_OP_CFG_ADDR 0x1C90 +#define MT6373_RG_LDO_VANT18_HW0_OP_CFG_ADDR 0x1C91 +#define MT6373_RG_LDO_VANT18_HW1_OP_CFG_ADDR 0x1C91 +#define MT6373_RG_LDO_VANT18_HW2_OP_CFG_ADDR 0x1C91 +#define MT6373_RG_LDO_VANT18_HW3_OP_CFG_ADDR 0x1C91 +#define MT6373_RG_LDO_VANT18_HW4_OP_CFG_ADDR 0x1C91 +#define MT6373_RG_LDO_VANT18_HW5_OP_CFG_ADDR 0x1C91 +#define MT6373_RG_LDO_VANT18_HW6_OP_CFG_ADDR 0x1C91 +#define MT6373_RG_LDO_VANT18_SW_OP_CFG_ADDR 0x1C91 +#define MT6373_RG_LDO_VANT18_RC0_OP_MODE_ADDR 0x1C92 +#define MT6373_RG_LDO_VANT18_RC1_OP_MODE_ADDR 0x1C92 +#define MT6373_RG_LDO_VANT18_RC2_OP_MODE_ADDR 0x1C92 +#define MT6373_RG_LDO_VANT18_RC3_OP_MODE_ADDR 0x1C92 +#define MT6373_RG_LDO_VANT18_RC4_OP_MODE_ADDR 0x1C92 +#define MT6373_RG_LDO_VANT18_RC5_OP_MODE_ADDR 0x1C92 +#define MT6373_RG_LDO_VANT18_RC6_OP_MODE_ADDR 0x1C92 +#define MT6373_RG_LDO_VANT18_RC7_OP_MODE_ADDR 0x1C92 +#define MT6373_RG_LDO_VANT18_RC8_OP_MODE_ADDR 0x1C93 +#define MT6373_RG_LDO_VANT18_RC9_OP_MODE_ADDR 0x1C93 +#define MT6373_RG_LDO_VANT18_RC10_OP_MODE_ADDR 0x1C93 +#define MT6373_RG_LDO_VANT18_RC11_OP_MODE_ADDR 0x1C93 +#define MT6373_RG_LDO_VANT18_RC12_OP_MODE_ADDR 0x1C93 +#define MT6373_RG_LDO_VANT18_RC13_OP_MODE_ADDR 0x1C93 +#define MT6373_RG_LDO_VANT18_HW0_OP_MODE_ADDR 0x1C94 +#define MT6373_RG_LDO_VANT18_HW1_OP_MODE_ADDR 0x1C94 +#define MT6373_RG_LDO_VANT18_HW2_OP_MODE_ADDR 0x1C94 +#define MT6373_RG_LDO_VANT18_HW3_OP_MODE_ADDR 0x1C94 +#define MT6373_RG_LDO_VANT18_HW4_OP_MODE_ADDR 0x1C94 +#define MT6373_RG_LDO_VANT18_HW5_OP_MODE_ADDR 0x1C94 +#define MT6373_RG_LDO_VANT18_HW6_OP_MODE_ADDR 0x1C94 +#define MT6373_RG_LDO_VMDDR_ONLV_EN_ADDR 0x1C96 +#define MT6373_RG_LDO_VMDDR_ONLV_EN_SHIFT 3 +#define MT6373_RG_LDO_VMDDR_RC0_OP_EN_ADDR 0x1C9A +#define MT6373_RG_LDO_VMDDR_RC1_OP_EN_ADDR 0x1C9A +#define MT6373_RG_LDO_VMDDR_RC2_OP_EN_ADDR 0x1C9A +#define MT6373_RG_LDO_VMDDR_RC3_OP_EN_ADDR 0x1C9A +#define MT6373_RG_LDO_VMDDR_RC4_OP_EN_ADDR 0x1C9A +#define MT6373_RG_LDO_VMDDR_RC5_OP_EN_ADDR 0x1C9A +#define MT6373_RG_LDO_VMDDR_RC6_OP_EN_ADDR 0x1C9A +#define MT6373_RG_LDO_VMDDR_RC7_OP_EN_ADDR 0x1C9A +#define MT6373_RG_LDO_VMDDR_RC8_OP_EN_ADDR 0x1C9B +#define MT6373_RG_LDO_VMDDR_RC9_OP_EN_ADDR 0x1C9B +#define MT6373_RG_LDO_VMDDR_RC10_OP_EN_ADDR 0x1C9B +#define MT6373_RG_LDO_VMDDR_RC11_OP_EN_ADDR 0x1C9B +#define MT6373_RG_LDO_VMDDR_RC12_OP_EN_ADDR 0x1C9B +#define MT6373_RG_LDO_VMDDR_RC13_OP_EN_ADDR 0x1C9B +#define MT6373_RG_LDO_VMDDR_HW0_OP_EN_ADDR 0x1C9C +#define MT6373_RG_LDO_VMDDR_HW1_OP_EN_ADDR 0x1C9C +#define MT6373_RG_LDO_VMDDR_HW2_OP_EN_ADDR 0x1C9C +#define MT6373_RG_LDO_VMDDR_HW3_OP_EN_ADDR 0x1C9C +#define MT6373_RG_LDO_VMDDR_HW4_OP_EN_ADDR 0x1C9C +#define MT6373_RG_LDO_VMDDR_HW5_OP_EN_ADDR 0x1C9C +#define MT6373_RG_LDO_VMDDR_HW6_OP_EN_ADDR 0x1C9C +#define MT6373_RG_LDO_VMDDR_SW_OP_EN_ADDR 0x1C9C +#define MT6373_RG_LDO_VMDDR_RC0_OP_CFG_ADDR 0x1C9D +#define MT6373_RG_LDO_VMDDR_RC1_OP_CFG_ADDR 0x1C9D +#define MT6373_RG_LDO_VMDDR_RC2_OP_CFG_ADDR 0x1C9D +#define MT6373_RG_LDO_VMDDR_RC3_OP_CFG_ADDR 0x1C9D +#define MT6373_RG_LDO_VMDDR_RC4_OP_CFG_ADDR 0x1C9D +#define MT6373_RG_LDO_VMDDR_RC5_OP_CFG_ADDR 0x1C9D +#define MT6373_RG_LDO_VMDDR_RC6_OP_CFG_ADDR 0x1C9D +#define MT6373_RG_LDO_VMDDR_RC7_OP_CFG_ADDR 0x1C9D +#define MT6373_RG_LDO_VMDDR_RC8_OP_CFG_ADDR 0x1C9E +#define MT6373_RG_LDO_VMDDR_RC9_OP_CFG_ADDR 0x1C9E +#define MT6373_RG_LDO_VMDDR_RC10_OP_CFG_ADDR 0x1C9E +#define MT6373_RG_LDO_VMDDR_RC11_OP_CFG_ADDR 0x1C9E +#define MT6373_RG_LDO_VMDDR_RC12_OP_CFG_ADDR 0x1C9E +#define MT6373_RG_LDO_VMDDR_RC13_OP_CFG_ADDR 0x1C9E +#define MT6373_RG_LDO_VMDDR_HW0_OP_CFG_ADDR 0x1C9F +#define MT6373_RG_LDO_VMDDR_HW1_OP_CFG_ADDR 0x1C9F +#define MT6373_RG_LDO_VMDDR_HW2_OP_CFG_ADDR 0x1C9F +#define MT6373_RG_LDO_VMDDR_HW3_OP_CFG_ADDR 0x1C9F +#define MT6373_RG_LDO_VMDDR_HW4_OP_CFG_ADDR 0x1C9F +#define MT6373_RG_LDO_VMDDR_HW5_OP_CFG_ADDR 0x1C9F +#define MT6373_RG_LDO_VMDDR_HW6_OP_CFG_ADDR 0x1C9F +#define MT6373_RG_LDO_VMDDR_SW_OP_CFG_ADDR 0x1C9F +#define MT6373_RG_LDO_VMDDR_RC0_OP_MODE_ADDR 0x1CA0 +#define MT6373_RG_LDO_VMDDR_RC1_OP_MODE_ADDR 0x1CA0 +#define MT6373_RG_LDO_VMDDR_RC2_OP_MODE_ADDR 0x1CA0 +#define MT6373_RG_LDO_VMDDR_RC3_OP_MODE_ADDR 0x1CA0 +#define MT6373_RG_LDO_VMDDR_RC4_OP_MODE_ADDR 0x1CA0 +#define MT6373_RG_LDO_VMDDR_RC5_OP_MODE_ADDR 0x1CA0 +#define MT6373_RG_LDO_VMDDR_RC6_OP_MODE_ADDR 0x1CA0 +#define MT6373_RG_LDO_VMDDR_RC7_OP_MODE_ADDR 0x1CA0 +#define MT6373_RG_LDO_VMDDR_RC8_OP_MODE_ADDR 0x1CA1 +#define MT6373_RG_LDO_VMDDR_RC9_OP_MODE_ADDR 0x1CA1 +#define MT6373_RG_LDO_VMDDR_RC10_OP_MODE_ADDR 0x1CA1 +#define MT6373_RG_LDO_VMDDR_RC11_OP_MODE_ADDR 0x1CA1 +#define MT6373_RG_LDO_VMDDR_RC12_OP_MODE_ADDR 0x1CA1 +#define MT6373_RG_LDO_VMDDR_RC13_OP_MODE_ADDR 0x1CA1 +#define MT6373_RG_LDO_VMDDR_HW0_OP_MODE_ADDR 0x1CA2 +#define MT6373_RG_LDO_VMDDR_HW1_OP_MODE_ADDR 0x1CA2 +#define MT6373_RG_LDO_VMDDR_HW2_OP_MODE_ADDR 0x1CA2 +#define MT6373_RG_LDO_VMDDR_HW3_OP_MODE_ADDR 0x1CA2 +#define MT6373_RG_LDO_VMDDR_HW4_OP_MODE_ADDR 0x1CA2 +#define MT6373_RG_LDO_VMDDR_HW5_OP_MODE_ADDR 0x1CA2 +#define MT6373_RG_LDO_VMDDR_HW6_OP_MODE_ADDR 0x1CA2 +#define MT6373_RG_LDO_VEFUSE_ONLV_EN_ADDR 0x1CA4 +#define MT6373_RG_LDO_VEFUSE_ONLV_EN_SHIFT 3 +#define MT6373_RG_LDO_VEFUSE_RC0_OP_EN_ADDR 0x1CA8 +#define MT6373_RG_LDO_VEFUSE_RC1_OP_EN_ADDR 0x1CA8 +#define MT6373_RG_LDO_VEFUSE_RC2_OP_EN_ADDR 0x1CA8 +#define MT6373_RG_LDO_VEFUSE_RC3_OP_EN_ADDR 0x1CA8 +#define MT6373_RG_LDO_VEFUSE_RC4_OP_EN_ADDR 0x1CA8 +#define MT6373_RG_LDO_VEFUSE_RC5_OP_EN_ADDR 0x1CA8 +#define MT6373_RG_LDO_VEFUSE_RC6_OP_EN_ADDR 0x1CA8 +#define MT6373_RG_LDO_VEFUSE_RC7_OP_EN_ADDR 0x1CA8 +#define MT6373_RG_LDO_VEFUSE_RC8_OP_EN_ADDR 0x1CA9 +#define MT6373_RG_LDO_VEFUSE_RC9_OP_EN_ADDR 0x1CA9 +#define MT6373_RG_LDO_VEFUSE_RC10_OP_EN_ADDR 0x1CA9 +#define MT6373_RG_LDO_VEFUSE_RC11_OP_EN_ADDR 0x1CA9 +#define MT6373_RG_LDO_VEFUSE_RC12_OP_EN_ADDR 0x1CA9 +#define MT6373_RG_LDO_VEFUSE_RC13_OP_EN_ADDR 0x1CA9 +#define MT6373_RG_LDO_VEFUSE_HW0_OP_EN_ADDR 0x1CAA +#define MT6373_RG_LDO_VEFUSE_HW1_OP_EN_ADDR 0x1CAA +#define MT6373_RG_LDO_VEFUSE_HW2_OP_EN_ADDR 0x1CAA +#define MT6373_RG_LDO_VEFUSE_HW3_OP_EN_ADDR 0x1CAA +#define MT6373_RG_LDO_VEFUSE_HW4_OP_EN_ADDR 0x1CAA +#define MT6373_RG_LDO_VEFUSE_HW5_OP_EN_ADDR 0x1CAA +#define MT6373_RG_LDO_VEFUSE_HW6_OP_EN_ADDR 0x1CAA +#define MT6373_RG_LDO_VEFUSE_SW_OP_EN_ADDR 0x1CAA +#define MT6373_RG_LDO_VEFUSE_RC0_OP_CFG_ADDR 0x1CAB +#define MT6373_RG_LDO_VEFUSE_RC1_OP_CFG_ADDR 0x1CAB +#define MT6373_RG_LDO_VEFUSE_RC2_OP_CFG_ADDR 0x1CAB +#define MT6373_RG_LDO_VEFUSE_RC3_OP_CFG_ADDR 0x1CAB +#define MT6373_RG_LDO_VEFUSE_RC4_OP_CFG_ADDR 0x1CAB +#define MT6373_RG_LDO_VEFUSE_RC5_OP_CFG_ADDR 0x1CAB +#define MT6373_RG_LDO_VEFUSE_RC6_OP_CFG_ADDR 0x1CAB +#define MT6373_RG_LDO_VEFUSE_RC7_OP_CFG_ADDR 0x1CAB +#define MT6373_RG_LDO_VEFUSE_RC8_OP_CFG_ADDR 0x1CAC +#define MT6373_RG_LDO_VEFUSE_RC9_OP_CFG_ADDR 0x1CAC +#define MT6373_RG_LDO_VEFUSE_RC10_OP_CFG_ADDR 0x1CAC +#define MT6373_RG_LDO_VEFUSE_RC11_OP_CFG_ADDR 0x1CAC +#define MT6373_RG_LDO_VEFUSE_RC12_OP_CFG_ADDR 0x1CAC +#define MT6373_RG_LDO_VEFUSE_RC13_OP_CFG_ADDR 0x1CAC +#define MT6373_RG_LDO_VEFUSE_HW0_OP_CFG_ADDR 0x1CAD +#define MT6373_RG_LDO_VEFUSE_HW1_OP_CFG_ADDR 0x1CAD +#define MT6373_RG_LDO_VEFUSE_HW2_OP_CFG_ADDR 0x1CAD +#define MT6373_RG_LDO_VEFUSE_HW3_OP_CFG_ADDR 0x1CAD +#define MT6373_RG_LDO_VEFUSE_HW4_OP_CFG_ADDR 0x1CAD +#define MT6373_RG_LDO_VEFUSE_HW5_OP_CFG_ADDR 0x1CAD +#define MT6373_RG_LDO_VEFUSE_HW6_OP_CFG_ADDR 0x1CAD +#define MT6373_RG_LDO_VEFUSE_SW_OP_CFG_ADDR 0x1CAD +#define MT6373_RG_LDO_VEFUSE_RC0_OP_MODE_ADDR 0x1CAE +#define MT6373_RG_LDO_VEFUSE_RC1_OP_MODE_ADDR 0x1CAE +#define MT6373_RG_LDO_VEFUSE_RC2_OP_MODE_ADDR 0x1CAE +#define MT6373_RG_LDO_VEFUSE_RC3_OP_MODE_ADDR 0x1CAE +#define MT6373_RG_LDO_VEFUSE_RC4_OP_MODE_ADDR 0x1CAE +#define MT6373_RG_LDO_VEFUSE_RC5_OP_MODE_ADDR 0x1CAE +#define MT6373_RG_LDO_VEFUSE_RC6_OP_MODE_ADDR 0x1CAE +#define MT6373_RG_LDO_VEFUSE_RC7_OP_MODE_ADDR 0x1CAE +#define MT6373_RG_LDO_VEFUSE_RC8_OP_MODE_ADDR 0x1CAF +#define MT6373_RG_LDO_VEFUSE_RC9_OP_MODE_ADDR 0x1CAF +#define MT6373_RG_LDO_VEFUSE_RC10_OP_MODE_ADDR 0x1CAF +#define MT6373_RG_LDO_VEFUSE_RC11_OP_MODE_ADDR 0x1CAF +#define MT6373_RG_LDO_VEFUSE_RC12_OP_MODE_ADDR 0x1CAF +#define MT6373_RG_LDO_VEFUSE_RC13_OP_MODE_ADDR 0x1CAF +#define MT6373_RG_LDO_VEFUSE_HW0_OP_MODE_ADDR 0x1CB0 +#define MT6373_RG_LDO_VEFUSE_HW1_OP_MODE_ADDR 0x1CB0 +#define MT6373_RG_LDO_VEFUSE_HW2_OP_MODE_ADDR 0x1CB0 +#define MT6373_RG_LDO_VEFUSE_HW3_OP_MODE_ADDR 0x1CB0 +#define MT6373_RG_LDO_VEFUSE_HW4_OP_MODE_ADDR 0x1CB0 +#define MT6373_RG_LDO_VEFUSE_HW5_OP_MODE_ADDR 0x1CB0 +#define MT6373_RG_LDO_VEFUSE_HW6_OP_MODE_ADDR 0x1CB0 +#define MT6373_RG_LDO_VMCH_ONLV_EN_ADDR 0x1CB2 +#define MT6373_RG_LDO_VMCH_ONLV_EN_SHIFT 3 +#define MT6373_RG_LDO_VMCH_RC0_OP_EN_ADDR 0x1CB6 +#define MT6373_RG_LDO_VMCH_RC1_OP_EN_ADDR 0x1CB6 +#define MT6373_RG_LDO_VMCH_RC2_OP_EN_ADDR 0x1CB6 +#define MT6373_RG_LDO_VMCH_RC3_OP_EN_ADDR 0x1CB6 +#define MT6373_RG_LDO_VMCH_RC4_OP_EN_ADDR 0x1CB6 +#define MT6373_RG_LDO_VMCH_RC5_OP_EN_ADDR 0x1CB6 +#define MT6373_RG_LDO_VMCH_RC6_OP_EN_ADDR 0x1CB6 +#define MT6373_RG_LDO_VMCH_RC7_OP_EN_ADDR 0x1CB6 +#define MT6373_RG_LDO_VMCH_RC8_OP_EN_ADDR 0x1CB7 +#define MT6373_RG_LDO_VMCH_RC9_OP_EN_ADDR 0x1CB7 +#define MT6373_RG_LDO_VMCH_RC10_OP_EN_ADDR 0x1CB7 +#define MT6373_RG_LDO_VMCH_RC11_OP_EN_ADDR 0x1CB7 +#define MT6373_RG_LDO_VMCH_RC12_OP_EN_ADDR 0x1CB7 +#define MT6373_RG_LDO_VMCH_RC13_OP_EN_ADDR 0x1CB7 +#define MT6373_RG_LDO_VMCH_HW0_OP_EN_ADDR 0x1CB8 +#define MT6373_RG_LDO_VMCH_HW1_OP_EN_ADDR 0x1CB8 +#define MT6373_RG_LDO_VMCH_HW2_OP_EN_ADDR 0x1CB8 +#define MT6373_RG_LDO_VMCH_HW3_OP_EN_ADDR 0x1CB8 +#define MT6373_RG_LDO_VMCH_HW4_OP_EN_ADDR 0x1CB8 +#define MT6373_RG_LDO_VMCH_HW5_OP_EN_ADDR 0x1CB8 +#define MT6373_RG_LDO_VMCH_HW6_OP_EN_ADDR 0x1CB8 +#define MT6373_RG_LDO_VMCH_SW_OP_EN_ADDR 0x1CB8 +#define MT6373_RG_LDO_VMCH_RC0_OP_CFG_ADDR 0x1CB9 +#define MT6373_RG_LDO_VMCH_RC1_OP_CFG_ADDR 0x1CB9 +#define MT6373_RG_LDO_VMCH_RC2_OP_CFG_ADDR 0x1CB9 +#define MT6373_RG_LDO_VMCH_RC3_OP_CFG_ADDR 0x1CB9 +#define MT6373_RG_LDO_VMCH_RC4_OP_CFG_ADDR 0x1CB9 +#define MT6373_RG_LDO_VMCH_RC5_OP_CFG_ADDR 0x1CB9 +#define MT6373_RG_LDO_VMCH_RC6_OP_CFG_ADDR 0x1CB9 +#define MT6373_RG_LDO_VMCH_RC7_OP_CFG_ADDR 0x1CB9 +#define MT6373_RG_LDO_VMCH_RC8_OP_CFG_ADDR 0x1CBA +#define MT6373_RG_LDO_VMCH_RC9_OP_CFG_ADDR 0x1CBA +#define MT6373_RG_LDO_VMCH_RC10_OP_CFG_ADDR 0x1CBA +#define MT6373_RG_LDO_VMCH_RC11_OP_CFG_ADDR 0x1CBA +#define MT6373_RG_LDO_VMCH_RC12_OP_CFG_ADDR 0x1CBA +#define MT6373_RG_LDO_VMCH_RC13_OP_CFG_ADDR 0x1CBA +#define MT6373_RG_LDO_VMCH_HW0_OP_CFG_ADDR 0x1CBB +#define MT6373_RG_LDO_VMCH_HW1_OP_CFG_ADDR 0x1CBB +#define MT6373_RG_LDO_VMCH_HW2_OP_CFG_ADDR 0x1CBB +#define MT6373_RG_LDO_VMCH_HW3_OP_CFG_ADDR 0x1CBB +#define MT6373_RG_LDO_VMCH_HW4_OP_CFG_ADDR 0x1CBB +#define MT6373_RG_LDO_VMCH_HW5_OP_CFG_ADDR 0x1CBB +#define MT6373_RG_LDO_VMCH_HW6_OP_CFG_ADDR 0x1CBB +#define MT6373_RG_LDO_VMCH_SW_OP_CFG_ADDR 0x1CBB +#define MT6373_RG_LDO_VMCH_RC0_OP_MODE_ADDR 0x1CBC +#define MT6373_RG_LDO_VMCH_RC1_OP_MODE_ADDR 0x1CBC +#define MT6373_RG_LDO_VMCH_RC2_OP_MODE_ADDR 0x1CBC +#define MT6373_RG_LDO_VMCH_RC3_OP_MODE_ADDR 0x1CBC +#define MT6373_RG_LDO_VMCH_RC4_OP_MODE_ADDR 0x1CBC +#define MT6373_RG_LDO_VMCH_RC5_OP_MODE_ADDR 0x1CBC +#define MT6373_RG_LDO_VMCH_RC6_OP_MODE_ADDR 0x1CBC +#define MT6373_RG_LDO_VMCH_RC7_OP_MODE_ADDR 0x1CBC +#define MT6373_RG_LDO_VMCH_RC8_OP_MODE_ADDR 0x1CBD +#define MT6373_RG_LDO_VMCH_RC9_OP_MODE_ADDR 0x1CBD +#define MT6373_RG_LDO_VMCH_RC10_OP_MODE_ADDR 0x1CBD +#define MT6373_RG_LDO_VMCH_RC11_OP_MODE_ADDR 0x1CBD +#define MT6373_RG_LDO_VMCH_RC12_OP_MODE_ADDR 0x1CBD +#define MT6373_RG_LDO_VMCH_RC13_OP_MODE_ADDR 0x1CBD +#define MT6373_RG_LDO_VMCH_HW0_OP_MODE_ADDR 0x1CBE +#define MT6373_RG_LDO_VMCH_HW1_OP_MODE_ADDR 0x1CBE +#define MT6373_RG_LDO_VMCH_HW2_OP_MODE_ADDR 0x1CBE +#define MT6373_RG_LDO_VMCH_HW3_OP_MODE_ADDR 0x1CBE +#define MT6373_RG_LDO_VMCH_HW4_OP_MODE_ADDR 0x1CBE +#define MT6373_RG_LDO_VMCH_HW5_OP_MODE_ADDR 0x1CBE +#define MT6373_RG_LDO_VMCH_HW6_OP_MODE_ADDR 0x1CBE +#define MT6373_RG_LDO_VMC_ONLV_EN_ADDR 0x1CC1 +#define MT6373_RG_LDO_VMC_ONLV_EN_SHIFT 3 +#define MT6373_RG_LDO_VMC_RC0_OP_EN_ADDR 0x1CC5 +#define MT6373_RG_LDO_VMC_RC1_OP_EN_ADDR 0x1CC5 +#define MT6373_RG_LDO_VMC_RC2_OP_EN_ADDR 0x1CC5 +#define MT6373_RG_LDO_VMC_RC3_OP_EN_ADDR 0x1CC5 +#define MT6373_RG_LDO_VMC_RC4_OP_EN_ADDR 0x1CC5 +#define MT6373_RG_LDO_VMC_RC5_OP_EN_ADDR 0x1CC5 +#define MT6373_RG_LDO_VMC_RC6_OP_EN_ADDR 0x1CC5 +#define MT6373_RG_LDO_VMC_RC7_OP_EN_ADDR 0x1CC5 +#define MT6373_RG_LDO_VMC_RC8_OP_EN_ADDR 0x1CC6 +#define MT6373_RG_LDO_VMC_RC9_OP_EN_ADDR 0x1CC6 +#define MT6373_RG_LDO_VMC_RC10_OP_EN_ADDR 0x1CC6 +#define MT6373_RG_LDO_VMC_RC11_OP_EN_ADDR 0x1CC6 +#define MT6373_RG_LDO_VMC_RC12_OP_EN_ADDR 0x1CC6 +#define MT6373_RG_LDO_VMC_RC13_OP_EN_ADDR 0x1CC6 +#define MT6373_RG_LDO_VMC_HW0_OP_EN_ADDR 0x1CC7 +#define MT6373_RG_LDO_VMC_HW1_OP_EN_ADDR 0x1CC7 +#define MT6373_RG_LDO_VMC_HW2_OP_EN_ADDR 0x1CC7 +#define MT6373_RG_LDO_VMC_HW3_OP_EN_ADDR 0x1CC7 +#define MT6373_RG_LDO_VMC_HW4_OP_EN_ADDR 0x1CC7 +#define MT6373_RG_LDO_VMC_HW5_OP_EN_ADDR 0x1CC7 +#define MT6373_RG_LDO_VMC_HW6_OP_EN_ADDR 0x1CC7 +#define MT6373_RG_LDO_VMC_SW_OP_EN_ADDR 0x1CC7 +#define MT6373_RG_LDO_VMC_RC0_OP_CFG_ADDR 0x1CC8 +#define MT6373_RG_LDO_VMC_RC1_OP_CFG_ADDR 0x1CC8 +#define MT6373_RG_LDO_VMC_RC2_OP_CFG_ADDR 0x1CC8 +#define MT6373_RG_LDO_VMC_RC3_OP_CFG_ADDR 0x1CC8 +#define MT6373_RG_LDO_VMC_RC4_OP_CFG_ADDR 0x1CC8 +#define MT6373_RG_LDO_VMC_RC5_OP_CFG_ADDR 0x1CC8 +#define MT6373_RG_LDO_VMC_RC6_OP_CFG_ADDR 0x1CC8 +#define MT6373_RG_LDO_VMC_RC7_OP_CFG_ADDR 0x1CC8 +#define MT6373_RG_LDO_VMC_RC8_OP_CFG_ADDR 0x1CC9 +#define MT6373_RG_LDO_VMC_RC9_OP_CFG_ADDR 0x1CC9 +#define MT6373_RG_LDO_VMC_RC10_OP_CFG_ADDR 0x1CC9 +#define MT6373_RG_LDO_VMC_RC11_OP_CFG_ADDR 0x1CC9 +#define MT6373_RG_LDO_VMC_RC12_OP_CFG_ADDR 0x1CC9 +#define MT6373_RG_LDO_VMC_RC13_OP_CFG_ADDR 0x1CC9 +#define MT6373_RG_LDO_VMC_HW0_OP_CFG_ADDR 0x1CCA +#define MT6373_RG_LDO_VMC_HW1_OP_CFG_ADDR 0x1CCA +#define MT6373_RG_LDO_VMC_HW2_OP_CFG_ADDR 0x1CCA +#define MT6373_RG_LDO_VMC_HW3_OP_CFG_ADDR 0x1CCA +#define MT6373_RG_LDO_VMC_HW4_OP_CFG_ADDR 0x1CCA +#define MT6373_RG_LDO_VMC_HW5_OP_CFG_ADDR 0x1CCA +#define MT6373_RG_LDO_VMC_HW6_OP_CFG_ADDR 0x1CCA +#define MT6373_RG_LDO_VMC_SW_OP_CFG_ADDR 0x1CCA +#define MT6373_RG_LDO_VMC_RC0_OP_MODE_ADDR 0x1CCB +#define MT6373_RG_LDO_VMC_RC1_OP_MODE_ADDR 0x1CCB +#define MT6373_RG_LDO_VMC_RC2_OP_MODE_ADDR 0x1CCB +#define MT6373_RG_LDO_VMC_RC3_OP_MODE_ADDR 0x1CCB +#define MT6373_RG_LDO_VMC_RC4_OP_MODE_ADDR 0x1CCB +#define MT6373_RG_LDO_VMC_RC5_OP_MODE_ADDR 0x1CCB +#define MT6373_RG_LDO_VMC_RC6_OP_MODE_ADDR 0x1CCB +#define MT6373_RG_LDO_VMC_RC7_OP_MODE_ADDR 0x1CCB +#define MT6373_RG_LDO_VMC_RC8_OP_MODE_ADDR 0x1CCC +#define MT6373_RG_LDO_VMC_RC9_OP_MODE_ADDR 0x1CCC +#define MT6373_RG_LDO_VMC_RC10_OP_MODE_ADDR 0x1CCC +#define MT6373_RG_LDO_VMC_RC11_OP_MODE_ADDR 0x1CCC +#define MT6373_RG_LDO_VMC_RC12_OP_MODE_ADDR 0x1CCC +#define MT6373_RG_LDO_VMC_RC13_OP_MODE_ADDR 0x1CCC +#define MT6373_RG_LDO_VMC_HW0_OP_MODE_ADDR 0x1CCD +#define MT6373_RG_LDO_VMC_HW1_OP_MODE_ADDR 0x1CCD +#define MT6373_RG_LDO_VMC_HW2_OP_MODE_ADDR 0x1CCD +#define MT6373_RG_LDO_VMC_HW3_OP_MODE_ADDR 0x1CCD +#define MT6373_RG_LDO_VMC_HW4_OP_MODE_ADDR 0x1CCD +#define MT6373_RG_LDO_VMC_HW5_OP_MODE_ADDR 0x1CCD +#define MT6373_RG_LDO_VMC_HW6_OP_MODE_ADDR 0x1CCD +#define MT6373_RG_LDO_VIBR_ONLV_EN_ADDR 0x1CCF +#define MT6373_RG_LDO_VIBR_ONLV_EN_SHIFT 3 +#define MT6373_RG_LDO_VIBR_RC0_OP_EN_ADDR 0x1CD3 +#define MT6373_RG_LDO_VIBR_RC1_OP_EN_ADDR 0x1CD3 +#define MT6373_RG_LDO_VIBR_RC2_OP_EN_ADDR 0x1CD3 +#define MT6373_RG_LDO_VIBR_RC3_OP_EN_ADDR 0x1CD3 +#define MT6373_RG_LDO_VIBR_RC4_OP_EN_ADDR 0x1CD3 +#define MT6373_RG_LDO_VIBR_RC5_OP_EN_ADDR 0x1CD3 +#define MT6373_RG_LDO_VIBR_RC6_OP_EN_ADDR 0x1CD3 +#define MT6373_RG_LDO_VIBR_RC7_OP_EN_ADDR 0x1CD3 +#define MT6373_RG_LDO_VIBR_RC8_OP_EN_ADDR 0x1CD4 +#define MT6373_RG_LDO_VIBR_RC9_OP_EN_ADDR 0x1CD4 +#define MT6373_RG_LDO_VIBR_RC10_OP_EN_ADDR 0x1CD4 +#define MT6373_RG_LDO_VIBR_RC11_OP_EN_ADDR 0x1CD4 +#define MT6373_RG_LDO_VIBR_RC12_OP_EN_ADDR 0x1CD4 +#define MT6373_RG_LDO_VIBR_RC13_OP_EN_ADDR 0x1CD4 +#define MT6373_RG_LDO_VIBR_HW0_OP_EN_ADDR 0x1CD5 +#define MT6373_RG_LDO_VIBR_HW1_OP_EN_ADDR 0x1CD5 +#define MT6373_RG_LDO_VIBR_HW2_OP_EN_ADDR 0x1CD5 +#define MT6373_RG_LDO_VIBR_HW3_OP_EN_ADDR 0x1CD5 +#define MT6373_RG_LDO_VIBR_HW4_OP_EN_ADDR 0x1CD5 +#define MT6373_RG_LDO_VIBR_HW5_OP_EN_ADDR 0x1CD5 +#define MT6373_RG_LDO_VIBR_HW6_OP_EN_ADDR 0x1CD5 +#define MT6373_RG_LDO_VIBR_SW_OP_EN_ADDR 0x1CD5 +#define MT6373_RG_LDO_VIBR_RC0_OP_CFG_ADDR 0x1CD6 +#define MT6373_RG_LDO_VIBR_RC1_OP_CFG_ADDR 0x1CD6 +#define MT6373_RG_LDO_VIBR_RC2_OP_CFG_ADDR 0x1CD6 +#define MT6373_RG_LDO_VIBR_RC3_OP_CFG_ADDR 0x1CD6 +#define MT6373_RG_LDO_VIBR_RC4_OP_CFG_ADDR 0x1CD6 +#define MT6373_RG_LDO_VIBR_RC5_OP_CFG_ADDR 0x1CD6 +#define MT6373_RG_LDO_VIBR_RC6_OP_CFG_ADDR 0x1CD6 +#define MT6373_RG_LDO_VIBR_RC7_OP_CFG_ADDR 0x1CD6 +#define MT6373_RG_LDO_VIBR_RC8_OP_CFG_ADDR 0x1CD7 +#define MT6373_RG_LDO_VIBR_RC9_OP_CFG_ADDR 0x1CD7 +#define MT6373_RG_LDO_VIBR_RC10_OP_CFG_ADDR 0x1CD7 +#define MT6373_RG_LDO_VIBR_RC11_OP_CFG_ADDR 0x1CD7 +#define MT6373_RG_LDO_VIBR_RC12_OP_CFG_ADDR 0x1CD7 +#define MT6373_RG_LDO_VIBR_RC13_OP_CFG_ADDR 0x1CD7 +#define MT6373_RG_LDO_VIBR_HW0_OP_CFG_ADDR 0x1CD8 +#define MT6373_RG_LDO_VIBR_HW1_OP_CFG_ADDR 0x1CD8 +#define MT6373_RG_LDO_VIBR_HW2_OP_CFG_ADDR 0x1CD8 +#define MT6373_RG_LDO_VIBR_HW3_OP_CFG_ADDR 0x1CD8 +#define MT6373_RG_LDO_VIBR_HW4_OP_CFG_ADDR 0x1CD8 +#define MT6373_RG_LDO_VIBR_HW5_OP_CFG_ADDR 0x1CD8 +#define MT6373_RG_LDO_VIBR_HW6_OP_CFG_ADDR 0x1CD8 +#define MT6373_RG_LDO_VIBR_SW_OP_CFG_ADDR 0x1CD8 +#define MT6373_RG_LDO_VIBR_RC0_OP_MODE_ADDR 0x1CD9 +#define MT6373_RG_LDO_VIBR_RC1_OP_MODE_ADDR 0x1CD9 +#define MT6373_RG_LDO_VIBR_RC2_OP_MODE_ADDR 0x1CD9 +#define MT6373_RG_LDO_VIBR_RC3_OP_MODE_ADDR 0x1CD9 +#define MT6373_RG_LDO_VIBR_RC4_OP_MODE_ADDR 0x1CD9 +#define MT6373_RG_LDO_VIBR_RC5_OP_MODE_ADDR 0x1CD9 +#define MT6373_RG_LDO_VIBR_RC6_OP_MODE_ADDR 0x1CD9 +#define MT6373_RG_LDO_VIBR_RC7_OP_MODE_ADDR 0x1CD9 +#define MT6373_RG_LDO_VIBR_RC8_OP_MODE_ADDR 0x1CDA +#define MT6373_RG_LDO_VIBR_RC9_OP_MODE_ADDR 0x1CDA +#define MT6373_RG_LDO_VIBR_RC10_OP_MODE_ADDR 0x1CDA +#define MT6373_RG_LDO_VIBR_RC11_OP_MODE_ADDR 0x1CDA +#define MT6373_RG_LDO_VIBR_RC12_OP_MODE_ADDR 0x1CDA +#define MT6373_RG_LDO_VIBR_RC13_OP_MODE_ADDR 0x1CDA +#define MT6373_RG_LDO_VIBR_HW0_OP_MODE_ADDR 0x1CDB +#define MT6373_RG_LDO_VIBR_HW1_OP_MODE_ADDR 0x1CDB +#define MT6373_RG_LDO_VIBR_HW2_OP_MODE_ADDR 0x1CDB +#define MT6373_RG_LDO_VIBR_HW3_OP_MODE_ADDR 0x1CDB +#define MT6373_RG_LDO_VIBR_HW4_OP_MODE_ADDR 0x1CDB +#define MT6373_RG_LDO_VIBR_HW5_OP_MODE_ADDR 0x1CDB +#define MT6373_RG_LDO_VIBR_HW6_OP_MODE_ADDR 0x1CDB +#define MT6373_RG_LDO_VIO28_ONLV_EN_ADDR 0x1D08 +#define MT6373_RG_LDO_VIO28_ONLV_EN_SHIFT 3 +#define MT6373_RG_LDO_VIO28_RC0_OP_EN_ADDR 0x1D0C +#define MT6373_RG_LDO_VIO28_RC1_OP_EN_ADDR 0x1D0C +#define MT6373_RG_LDO_VIO28_RC2_OP_EN_ADDR 0x1D0C +#define MT6373_RG_LDO_VIO28_RC3_OP_EN_ADDR 0x1D0C +#define MT6373_RG_LDO_VIO28_RC4_OP_EN_ADDR 0x1D0C +#define MT6373_RG_LDO_VIO28_RC5_OP_EN_ADDR 0x1D0C +#define MT6373_RG_LDO_VIO28_RC6_OP_EN_ADDR 0x1D0C +#define MT6373_RG_LDO_VIO28_RC7_OP_EN_ADDR 0x1D0C +#define MT6373_RG_LDO_VIO28_RC8_OP_EN_ADDR 0x1D0D +#define MT6373_RG_LDO_VIO28_RC9_OP_EN_ADDR 0x1D0D +#define MT6373_RG_LDO_VIO28_RC10_OP_EN_ADDR 0x1D0D +#define MT6373_RG_LDO_VIO28_RC11_OP_EN_ADDR 0x1D0D +#define MT6373_RG_LDO_VIO28_RC12_OP_EN_ADDR 0x1D0D +#define MT6373_RG_LDO_VIO28_RC13_OP_EN_ADDR 0x1D0D +#define MT6373_RG_LDO_VIO28_HW0_OP_EN_ADDR 0x1D0E +#define MT6373_RG_LDO_VIO28_HW1_OP_EN_ADDR 0x1D0E +#define MT6373_RG_LDO_VIO28_HW2_OP_EN_ADDR 0x1D0E +#define MT6373_RG_LDO_VIO28_HW3_OP_EN_ADDR 0x1D0E +#define MT6373_RG_LDO_VIO28_HW4_OP_EN_ADDR 0x1D0E +#define MT6373_RG_LDO_VIO28_HW5_OP_EN_ADDR 0x1D0E +#define MT6373_RG_LDO_VIO28_HW6_OP_EN_ADDR 0x1D0E +#define MT6373_RG_LDO_VIO28_SW_OP_EN_ADDR 0x1D0E +#define MT6373_RG_LDO_VIO28_RC0_OP_CFG_ADDR 0x1D0F +#define MT6373_RG_LDO_VIO28_RC1_OP_CFG_ADDR 0x1D0F +#define MT6373_RG_LDO_VIO28_RC2_OP_CFG_ADDR 0x1D0F +#define MT6373_RG_LDO_VIO28_RC3_OP_CFG_ADDR 0x1D0F +#define MT6373_RG_LDO_VIO28_RC4_OP_CFG_ADDR 0x1D0F +#define MT6373_RG_LDO_VIO28_RC5_OP_CFG_ADDR 0x1D0F +#define MT6373_RG_LDO_VIO28_RC6_OP_CFG_ADDR 0x1D0F +#define MT6373_RG_LDO_VIO28_RC7_OP_CFG_ADDR 0x1D0F +#define MT6373_RG_LDO_VIO28_RC8_OP_CFG_ADDR 0x1D10 +#define MT6373_RG_LDO_VIO28_RC9_OP_CFG_ADDR 0x1D10 +#define MT6373_RG_LDO_VIO28_RC10_OP_CFG_ADDR 0x1D10 +#define MT6373_RG_LDO_VIO28_RC11_OP_CFG_ADDR 0x1D10 +#define MT6373_RG_LDO_VIO28_RC12_OP_CFG_ADDR 0x1D10 +#define MT6373_RG_LDO_VIO28_RC13_OP_CFG_ADDR 0x1D10 +#define MT6373_RG_LDO_VIO28_HW0_OP_CFG_ADDR 0x1D11 +#define MT6373_RG_LDO_VIO28_HW1_OP_CFG_ADDR 0x1D11 +#define MT6373_RG_LDO_VIO28_HW2_OP_CFG_ADDR 0x1D11 +#define MT6373_RG_LDO_VIO28_HW3_OP_CFG_ADDR 0x1D11 +#define MT6373_RG_LDO_VIO28_HW4_OP_CFG_ADDR 0x1D11 +#define MT6373_RG_LDO_VIO28_HW5_OP_CFG_ADDR 0x1D11 +#define MT6373_RG_LDO_VIO28_HW6_OP_CFG_ADDR 0x1D11 +#define MT6373_RG_LDO_VIO28_SW_OP_CFG_ADDR 0x1D11 +#define MT6373_RG_LDO_VIO28_RC0_OP_MODE_ADDR 0x1D12 +#define MT6373_RG_LDO_VIO28_RC1_OP_MODE_ADDR 0x1D12 +#define MT6373_RG_LDO_VIO28_RC2_OP_MODE_ADDR 0x1D12 +#define MT6373_RG_LDO_VIO28_RC3_OP_MODE_ADDR 0x1D12 +#define MT6373_RG_LDO_VIO28_RC4_OP_MODE_ADDR 0x1D12 +#define MT6373_RG_LDO_VIO28_RC5_OP_MODE_ADDR 0x1D12 +#define MT6373_RG_LDO_VIO28_RC6_OP_MODE_ADDR 0x1D12 +#define MT6373_RG_LDO_VIO28_RC7_OP_MODE_ADDR 0x1D12 +#define MT6373_RG_LDO_VIO28_RC8_OP_MODE_ADDR 0x1D13 +#define MT6373_RG_LDO_VIO28_RC9_OP_MODE_ADDR 0x1D13 +#define MT6373_RG_LDO_VIO28_RC10_OP_MODE_ADDR 0x1D13 +#define MT6373_RG_LDO_VIO28_RC11_OP_MODE_ADDR 0x1D13 +#define MT6373_RG_LDO_VIO28_RC12_OP_MODE_ADDR 0x1D13 +#define MT6373_RG_LDO_VIO28_RC13_OP_MODE_ADDR 0x1D13 +#define MT6373_RG_LDO_VIO28_HW0_OP_MODE_ADDR 0x1D14 +#define MT6373_RG_LDO_VIO28_HW1_OP_MODE_ADDR 0x1D14 +#define MT6373_RG_LDO_VIO28_HW2_OP_MODE_ADDR 0x1D14 +#define MT6373_RG_LDO_VIO28_HW3_OP_MODE_ADDR 0x1D14 +#define MT6373_RG_LDO_VIO28_HW4_OP_MODE_ADDR 0x1D14 +#define MT6373_RG_LDO_VIO28_HW5_OP_MODE_ADDR 0x1D14 +#define MT6373_RG_LDO_VIO28_HW6_OP_MODE_ADDR 0x1D14 +#define MT6373_RG_LDO_VFP_ONLV_EN_ADDR 0x1D16 +#define MT6373_RG_LDO_VFP_ONLV_EN_SHIFT 3 +#define MT6373_RG_LDO_VFP_RC0_OP_EN_ADDR 0x1D1A +#define MT6373_RG_LDO_VFP_RC1_OP_EN_ADDR 0x1D1A +#define MT6373_RG_LDO_VFP_RC2_OP_EN_ADDR 0x1D1A +#define MT6373_RG_LDO_VFP_RC3_OP_EN_ADDR 0x1D1A +#define MT6373_RG_LDO_VFP_RC4_OP_EN_ADDR 0x1D1A +#define MT6373_RG_LDO_VFP_RC5_OP_EN_ADDR 0x1D1A +#define MT6373_RG_LDO_VFP_RC6_OP_EN_ADDR 0x1D1A +#define MT6373_RG_LDO_VFP_RC7_OP_EN_ADDR 0x1D1A +#define MT6373_RG_LDO_VFP_RC8_OP_EN_ADDR 0x1D1B +#define MT6373_RG_LDO_VFP_RC9_OP_EN_ADDR 0x1D1B +#define MT6373_RG_LDO_VFP_RC10_OP_EN_ADDR 0x1D1B +#define MT6373_RG_LDO_VFP_RC11_OP_EN_ADDR 0x1D1B +#define MT6373_RG_LDO_VFP_RC12_OP_EN_ADDR 0x1D1B +#define MT6373_RG_LDO_VFP_RC13_OP_EN_ADDR 0x1D1B +#define MT6373_RG_LDO_VFP_HW0_OP_EN_ADDR 0x1D1C +#define MT6373_RG_LDO_VFP_HW1_OP_EN_ADDR 0x1D1C +#define MT6373_RG_LDO_VFP_HW2_OP_EN_ADDR 0x1D1C +#define MT6373_RG_LDO_VFP_HW3_OP_EN_ADDR 0x1D1C +#define MT6373_RG_LDO_VFP_HW4_OP_EN_ADDR 0x1D1C +#define MT6373_RG_LDO_VFP_HW5_OP_EN_ADDR 0x1D1C +#define MT6373_RG_LDO_VFP_HW6_OP_EN_ADDR 0x1D1C +#define MT6373_RG_LDO_VFP_SW_OP_EN_ADDR 0x1D1C +#define MT6373_RG_LDO_VFP_RC0_OP_CFG_ADDR 0x1D1D +#define MT6373_RG_LDO_VFP_RC1_OP_CFG_ADDR 0x1D1D +#define MT6373_RG_LDO_VFP_RC2_OP_CFG_ADDR 0x1D1D +#define MT6373_RG_LDO_VFP_RC3_OP_CFG_ADDR 0x1D1D +#define MT6373_RG_LDO_VFP_RC4_OP_CFG_ADDR 0x1D1D +#define MT6373_RG_LDO_VFP_RC5_OP_CFG_ADDR 0x1D1D +#define MT6373_RG_LDO_VFP_RC6_OP_CFG_ADDR 0x1D1D +#define MT6373_RG_LDO_VFP_RC7_OP_CFG_ADDR 0x1D1D +#define MT6373_RG_LDO_VFP_RC8_OP_CFG_ADDR 0x1D1E +#define MT6373_RG_LDO_VFP_RC9_OP_CFG_ADDR 0x1D1E +#define MT6373_RG_LDO_VFP_RC10_OP_CFG_ADDR 0x1D1E +#define MT6373_RG_LDO_VFP_RC11_OP_CFG_ADDR 0x1D1E +#define MT6373_RG_LDO_VFP_RC12_OP_CFG_ADDR 0x1D1E +#define MT6373_RG_LDO_VFP_RC13_OP_CFG_ADDR 0x1D1E +#define MT6373_RG_LDO_VFP_HW0_OP_CFG_ADDR 0x1D1F +#define MT6373_RG_LDO_VFP_HW1_OP_CFG_ADDR 0x1D1F +#define MT6373_RG_LDO_VFP_HW2_OP_CFG_ADDR 0x1D1F +#define MT6373_RG_LDO_VFP_HW3_OP_CFG_ADDR 0x1D1F +#define MT6373_RG_LDO_VFP_HW4_OP_CFG_ADDR 0x1D1F +#define MT6373_RG_LDO_VFP_HW5_OP_CFG_ADDR 0x1D1F +#define MT6373_RG_LDO_VFP_HW6_OP_CFG_ADDR 0x1D1F +#define MT6373_RG_LDO_VFP_SW_OP_CFG_ADDR 0x1D1F +#define MT6373_RG_LDO_VFP_RC0_OP_MODE_ADDR 0x1D20 +#define MT6373_RG_LDO_VFP_RC1_OP_MODE_ADDR 0x1D20 +#define MT6373_RG_LDO_VFP_RC2_OP_MODE_ADDR 0x1D20 +#define MT6373_RG_LDO_VFP_RC3_OP_MODE_ADDR 0x1D20 +#define MT6373_RG_LDO_VFP_RC4_OP_MODE_ADDR 0x1D20 +#define MT6373_RG_LDO_VFP_RC5_OP_MODE_ADDR 0x1D20 +#define MT6373_RG_LDO_VFP_RC6_OP_MODE_ADDR 0x1D20 +#define MT6373_RG_LDO_VFP_RC7_OP_MODE_ADDR 0x1D20 +#define MT6373_RG_LDO_VFP_RC8_OP_MODE_ADDR 0x1D21 +#define MT6373_RG_LDO_VFP_RC9_OP_MODE_ADDR 0x1D21 +#define MT6373_RG_LDO_VFP_RC10_OP_MODE_ADDR 0x1D21 +#define MT6373_RG_LDO_VFP_RC11_OP_MODE_ADDR 0x1D21 +#define MT6373_RG_LDO_VFP_RC12_OP_MODE_ADDR 0x1D21 +#define MT6373_RG_LDO_VFP_RC13_OP_MODE_ADDR 0x1D21 +#define MT6373_RG_LDO_VFP_HW0_OP_MODE_ADDR 0x1D22 +#define MT6373_RG_LDO_VFP_HW1_OP_MODE_ADDR 0x1D22 +#define MT6373_RG_LDO_VFP_HW2_OP_MODE_ADDR 0x1D22 +#define MT6373_RG_LDO_VFP_HW3_OP_MODE_ADDR 0x1D22 +#define MT6373_RG_LDO_VFP_HW4_OP_MODE_ADDR 0x1D22 +#define MT6373_RG_LDO_VFP_HW5_OP_MODE_ADDR 0x1D22 +#define MT6373_RG_LDO_VFP_HW6_OP_MODE_ADDR 0x1D22 +#define MT6373_RG_LDO_VTP_ONLV_EN_ADDR 0x1D24 +#define MT6373_RG_LDO_VTP_ONLV_EN_SHIFT 3 +#define MT6373_RG_LDO_VTP_RC0_OP_EN_ADDR 0x1D28 +#define MT6373_RG_LDO_VTP_RC1_OP_EN_ADDR 0x1D28 +#define MT6373_RG_LDO_VTP_RC2_OP_EN_ADDR 0x1D28 +#define MT6373_RG_LDO_VTP_RC3_OP_EN_ADDR 0x1D28 +#define MT6373_RG_LDO_VTP_RC4_OP_EN_ADDR 0x1D28 +#define MT6373_RG_LDO_VTP_RC5_OP_EN_ADDR 0x1D28 +#define MT6373_RG_LDO_VTP_RC6_OP_EN_ADDR 0x1D28 +#define MT6373_RG_LDO_VTP_RC7_OP_EN_ADDR 0x1D28 +#define MT6373_RG_LDO_VTP_RC8_OP_EN_ADDR 0x1D29 +#define MT6373_RG_LDO_VTP_RC9_OP_EN_ADDR 0x1D29 +#define MT6373_RG_LDO_VTP_RC10_OP_EN_ADDR 0x1D29 +#define MT6373_RG_LDO_VTP_RC11_OP_EN_ADDR 0x1D29 +#define MT6373_RG_LDO_VTP_RC12_OP_EN_ADDR 0x1D29 +#define MT6373_RG_LDO_VTP_RC13_OP_EN_ADDR 0x1D29 +#define MT6373_RG_LDO_VTP_HW0_OP_EN_ADDR 0x1D2A +#define MT6373_RG_LDO_VTP_HW1_OP_EN_ADDR 0x1D2A +#define MT6373_RG_LDO_VTP_HW2_OP_EN_ADDR 0x1D2A +#define MT6373_RG_LDO_VTP_HW3_OP_EN_ADDR 0x1D2A +#define MT6373_RG_LDO_VTP_HW4_OP_EN_ADDR 0x1D2A +#define MT6373_RG_LDO_VTP_HW5_OP_EN_ADDR 0x1D2A +#define MT6373_RG_LDO_VTP_HW6_OP_EN_ADDR 0x1D2A +#define MT6373_RG_LDO_VTP_SW_OP_EN_ADDR 0x1D2A +#define MT6373_RG_LDO_VTP_RC0_OP_CFG_ADDR 0x1D2B +#define MT6373_RG_LDO_VTP_RC1_OP_CFG_ADDR 0x1D2B +#define MT6373_RG_LDO_VTP_RC2_OP_CFG_ADDR 0x1D2B +#define MT6373_RG_LDO_VTP_RC3_OP_CFG_ADDR 0x1D2B +#define MT6373_RG_LDO_VTP_RC4_OP_CFG_ADDR 0x1D2B +#define MT6373_RG_LDO_VTP_RC5_OP_CFG_ADDR 0x1D2B +#define MT6373_RG_LDO_VTP_RC6_OP_CFG_ADDR 0x1D2B +#define MT6373_RG_LDO_VTP_RC7_OP_CFG_ADDR 0x1D2B +#define MT6373_RG_LDO_VTP_RC8_OP_CFG_ADDR 0x1D2C +#define MT6373_RG_LDO_VTP_RC9_OP_CFG_ADDR 0x1D2C +#define MT6373_RG_LDO_VTP_RC10_OP_CFG_ADDR 0x1D2C +#define MT6373_RG_LDO_VTP_RC11_OP_CFG_ADDR 0x1D2C +#define MT6373_RG_LDO_VTP_RC12_OP_CFG_ADDR 0x1D2C +#define MT6373_RG_LDO_VTP_RC13_OP_CFG_ADDR 0x1D2C +#define MT6373_RG_LDO_VTP_HW0_OP_CFG_ADDR 0x1D2D +#define MT6373_RG_LDO_VTP_HW1_OP_CFG_ADDR 0x1D2D +#define MT6373_RG_LDO_VTP_HW2_OP_CFG_ADDR 0x1D2D +#define MT6373_RG_LDO_VTP_HW3_OP_CFG_ADDR 0x1D2D +#define MT6373_RG_LDO_VTP_HW4_OP_CFG_ADDR 0x1D2D +#define MT6373_RG_LDO_VTP_HW5_OP_CFG_ADDR 0x1D2D +#define MT6373_RG_LDO_VTP_HW6_OP_CFG_ADDR 0x1D2D +#define MT6373_RG_LDO_VTP_SW_OP_CFG_ADDR 0x1D2D +#define MT6373_RG_LDO_VTP_RC0_OP_MODE_ADDR 0x1D2E +#define MT6373_RG_LDO_VTP_RC1_OP_MODE_ADDR 0x1D2E +#define MT6373_RG_LDO_VTP_RC2_OP_MODE_ADDR 0x1D2E +#define MT6373_RG_LDO_VTP_RC3_OP_MODE_ADDR 0x1D2E +#define MT6373_RG_LDO_VTP_RC4_OP_MODE_ADDR 0x1D2E +#define MT6373_RG_LDO_VTP_RC5_OP_MODE_ADDR 0x1D2E +#define MT6373_RG_LDO_VTP_RC6_OP_MODE_ADDR 0x1D2E +#define MT6373_RG_LDO_VTP_RC7_OP_MODE_ADDR 0x1D2E +#define MT6373_RG_LDO_VTP_RC8_OP_MODE_ADDR 0x1D2F +#define MT6373_RG_LDO_VTP_RC9_OP_MODE_ADDR 0x1D2F +#define MT6373_RG_LDO_VTP_RC10_OP_MODE_ADDR 0x1D2F +#define MT6373_RG_LDO_VTP_RC11_OP_MODE_ADDR 0x1D2F +#define MT6373_RG_LDO_VTP_RC12_OP_MODE_ADDR 0x1D2F +#define MT6373_RG_LDO_VTP_RC13_OP_MODE_ADDR 0x1D2F +#define MT6373_RG_LDO_VTP_HW0_OP_MODE_ADDR 0x1D30 +#define MT6373_RG_LDO_VTP_HW1_OP_MODE_ADDR 0x1D30 +#define MT6373_RG_LDO_VTP_HW2_OP_MODE_ADDR 0x1D30 +#define MT6373_RG_LDO_VTP_HW3_OP_MODE_ADDR 0x1D30 +#define MT6373_RG_LDO_VTP_HW4_OP_MODE_ADDR 0x1D30 +#define MT6373_RG_LDO_VTP_HW5_OP_MODE_ADDR 0x1D30 +#define MT6373_RG_LDO_VTP_HW6_OP_MODE_ADDR 0x1D30 +#define MT6373_RG_LDO_VSIM1_ONLV_EN_ADDR 0x1D32 +#define MT6373_RG_LDO_VSIM1_ONLV_EN_SHIFT 3 +#define MT6373_RG_LDO_VSIM1_RC0_OP_EN_ADDR 0x1D36 +#define MT6373_RG_LDO_VSIM1_RC1_OP_EN_ADDR 0x1D36 +#define MT6373_RG_LDO_VSIM1_RC2_OP_EN_ADDR 0x1D36 +#define MT6373_RG_LDO_VSIM1_RC3_OP_EN_ADDR 0x1D36 +#define MT6373_RG_LDO_VSIM1_RC4_OP_EN_ADDR 0x1D36 +#define MT6373_RG_LDO_VSIM1_RC5_OP_EN_ADDR 0x1D36 +#define MT6373_RG_LDO_VSIM1_RC6_OP_EN_ADDR 0x1D36 +#define MT6373_RG_LDO_VSIM1_RC7_OP_EN_ADDR 0x1D36 +#define MT6373_RG_LDO_VSIM1_RC8_OP_EN_ADDR 0x1D37 +#define MT6373_RG_LDO_VSIM1_RC9_OP_EN_ADDR 0x1D37 +#define MT6373_RG_LDO_VSIM1_RC10_OP_EN_ADDR 0x1D37 +#define MT6373_RG_LDO_VSIM1_RC11_OP_EN_ADDR 0x1D37 +#define MT6373_RG_LDO_VSIM1_RC12_OP_EN_ADDR 0x1D37 +#define MT6373_RG_LDO_VSIM1_RC13_OP_EN_ADDR 0x1D37 +#define MT6373_RG_LDO_VSIM1_HW0_OP_EN_ADDR 0x1D38 +#define MT6373_RG_LDO_VSIM1_HW1_OP_EN_ADDR 0x1D38 +#define MT6373_RG_LDO_VSIM1_HW2_OP_EN_ADDR 0x1D38 +#define MT6373_RG_LDO_VSIM1_HW3_OP_EN_ADDR 0x1D38 +#define MT6373_RG_LDO_VSIM1_HW4_OP_EN_ADDR 0x1D38 +#define MT6373_RG_LDO_VSIM1_HW5_OP_EN_ADDR 0x1D38 +#define MT6373_RG_LDO_VSIM1_HW6_OP_EN_ADDR 0x1D38 +#define MT6373_RG_LDO_VSIM1_SW_OP_EN_ADDR 0x1D38 +#define MT6373_RG_LDO_VSIM1_RC0_OP_CFG_ADDR 0x1D39 +#define MT6373_RG_LDO_VSIM1_RC1_OP_CFG_ADDR 0x1D39 +#define MT6373_RG_LDO_VSIM1_RC2_OP_CFG_ADDR 0x1D39 +#define MT6373_RG_LDO_VSIM1_RC3_OP_CFG_ADDR 0x1D39 +#define MT6373_RG_LDO_VSIM1_RC4_OP_CFG_ADDR 0x1D39 +#define MT6373_RG_LDO_VSIM1_RC5_OP_CFG_ADDR 0x1D39 +#define MT6373_RG_LDO_VSIM1_RC6_OP_CFG_ADDR 0x1D39 +#define MT6373_RG_LDO_VSIM1_RC7_OP_CFG_ADDR 0x1D39 +#define MT6373_RG_LDO_VSIM1_RC8_OP_CFG_ADDR 0x1D3A +#define MT6373_RG_LDO_VSIM1_RC9_OP_CFG_ADDR 0x1D3A +#define MT6373_RG_LDO_VSIM1_RC10_OP_CFG_ADDR 0x1D3A +#define MT6373_RG_LDO_VSIM1_RC11_OP_CFG_ADDR 0x1D3A +#define MT6373_RG_LDO_VSIM1_RC12_OP_CFG_ADDR 0x1D3A +#define MT6373_RG_LDO_VSIM1_RC13_OP_CFG_ADDR 0x1D3A +#define MT6373_RG_LDO_VSIM1_HW0_OP_CFG_ADDR 0x1D3B +#define MT6373_RG_LDO_VSIM1_HW1_OP_CFG_ADDR 0x1D3B +#define MT6373_RG_LDO_VSIM1_HW2_OP_CFG_ADDR 0x1D3B +#define MT6373_RG_LDO_VSIM1_HW3_OP_CFG_ADDR 0x1D3B +#define MT6373_RG_LDO_VSIM1_HW4_OP_CFG_ADDR 0x1D3B +#define MT6373_RG_LDO_VSIM1_HW5_OP_CFG_ADDR 0x1D3B +#define MT6373_RG_LDO_VSIM1_HW6_OP_CFG_ADDR 0x1D3B +#define MT6373_RG_LDO_VSIM1_SW_OP_CFG_ADDR 0x1D3B +#define MT6373_RG_LDO_VSIM1_RC0_OP_MODE_ADDR 0x1D3C +#define MT6373_RG_LDO_VSIM1_RC1_OP_MODE_ADDR 0x1D3C +#define MT6373_RG_LDO_VSIM1_RC2_OP_MODE_ADDR 0x1D3C +#define MT6373_RG_LDO_VSIM1_RC3_OP_MODE_ADDR 0x1D3C +#define MT6373_RG_LDO_VSIM1_RC4_OP_MODE_ADDR 0x1D3C +#define MT6373_RG_LDO_VSIM1_RC5_OP_MODE_ADDR 0x1D3C +#define MT6373_RG_LDO_VSIM1_RC6_OP_MODE_ADDR 0x1D3C +#define MT6373_RG_LDO_VSIM1_RC7_OP_MODE_ADDR 0x1D3C +#define MT6373_RG_LDO_VSIM1_RC8_OP_MODE_ADDR 0x1D3D +#define MT6373_RG_LDO_VSIM1_RC9_OP_MODE_ADDR 0x1D3D +#define MT6373_RG_LDO_VSIM1_RC10_OP_MODE_ADDR 0x1D3D +#define MT6373_RG_LDO_VSIM1_RC11_OP_MODE_ADDR 0x1D3D +#define MT6373_RG_LDO_VSIM1_RC12_OP_MODE_ADDR 0x1D3D +#define MT6373_RG_LDO_VSIM1_RC13_OP_MODE_ADDR 0x1D3D +#define MT6373_RG_LDO_VSIM1_HW0_OP_MODE_ADDR 0x1D3E +#define MT6373_RG_LDO_VSIM1_HW1_OP_MODE_ADDR 0x1D3E +#define MT6373_RG_LDO_VSIM1_HW2_OP_MODE_ADDR 0x1D3E +#define MT6373_RG_LDO_VSIM1_HW3_OP_MODE_ADDR 0x1D3E +#define MT6373_RG_LDO_VSIM1_HW4_OP_MODE_ADDR 0x1D3E +#define MT6373_RG_LDO_VSIM1_HW5_OP_MODE_ADDR 0x1D3E +#define MT6373_RG_LDO_VSIM1_HW6_OP_MODE_ADDR 0x1D3E +#define MT6373_RG_LDO_VSIM2_ONLV_EN_ADDR 0x1D41 +#define MT6373_RG_LDO_VSIM2_ONLV_EN_SHIFT 3 +#define MT6373_RG_LDO_VSIM2_RC0_OP_EN_ADDR 0x1D45 +#define MT6373_RG_LDO_VSIM2_RC1_OP_EN_ADDR 0x1D45 +#define MT6373_RG_LDO_VSIM2_RC2_OP_EN_ADDR 0x1D45 +#define MT6373_RG_LDO_VSIM2_RC3_OP_EN_ADDR 0x1D45 +#define MT6373_RG_LDO_VSIM2_RC4_OP_EN_ADDR 0x1D45 +#define MT6373_RG_LDO_VSIM2_RC5_OP_EN_ADDR 0x1D45 +#define MT6373_RG_LDO_VSIM2_RC6_OP_EN_ADDR 0x1D45 +#define MT6373_RG_LDO_VSIM2_RC7_OP_EN_ADDR 0x1D45 +#define MT6373_RG_LDO_VSIM2_RC8_OP_EN_ADDR 0x1D46 +#define MT6373_RG_LDO_VSIM2_RC9_OP_EN_ADDR 0x1D46 +#define MT6373_RG_LDO_VSIM2_RC10_OP_EN_ADDR 0x1D46 +#define MT6373_RG_LDO_VSIM2_RC11_OP_EN_ADDR 0x1D46 +#define MT6373_RG_LDO_VSIM2_RC12_OP_EN_ADDR 0x1D46 +#define MT6373_RG_LDO_VSIM2_RC13_OP_EN_ADDR 0x1D46 +#define MT6373_RG_LDO_VSIM2_HW0_OP_EN_ADDR 0x1D47 +#define MT6373_RG_LDO_VSIM2_HW1_OP_EN_ADDR 0x1D47 +#define MT6373_RG_LDO_VSIM2_HW2_OP_EN_ADDR 0x1D47 +#define MT6373_RG_LDO_VSIM2_HW3_OP_EN_ADDR 0x1D47 +#define MT6373_RG_LDO_VSIM2_HW4_OP_EN_ADDR 0x1D47 +#define MT6373_RG_LDO_VSIM2_HW5_OP_EN_ADDR 0x1D47 +#define MT6373_RG_LDO_VSIM2_HW6_OP_EN_ADDR 0x1D47 +#define MT6373_RG_LDO_VSIM2_SW_OP_EN_ADDR 0x1D47 +#define MT6373_RG_LDO_VSIM2_RC0_OP_CFG_ADDR 0x1D48 +#define MT6373_RG_LDO_VSIM2_RC1_OP_CFG_ADDR 0x1D48 +#define MT6373_RG_LDO_VSIM2_RC2_OP_CFG_ADDR 0x1D48 +#define MT6373_RG_LDO_VSIM2_RC3_OP_CFG_ADDR 0x1D48 +#define MT6373_RG_LDO_VSIM2_RC4_OP_CFG_ADDR 0x1D48 +#define MT6373_RG_LDO_VSIM2_RC5_OP_CFG_ADDR 0x1D48 +#define MT6373_RG_LDO_VSIM2_RC6_OP_CFG_ADDR 0x1D48 +#define MT6373_RG_LDO_VSIM2_RC7_OP_CFG_ADDR 0x1D48 +#define MT6373_RG_LDO_VSIM2_RC8_OP_CFG_ADDR 0x1D49 +#define MT6373_RG_LDO_VSIM2_RC9_OP_CFG_ADDR 0x1D49 +#define MT6373_RG_LDO_VSIM2_RC10_OP_CFG_ADDR 0x1D49 +#define MT6373_RG_LDO_VSIM2_RC11_OP_CFG_ADDR 0x1D49 +#define MT6373_RG_LDO_VSIM2_RC12_OP_CFG_ADDR 0x1D49 +#define MT6373_RG_LDO_VSIM2_RC13_OP_CFG_ADDR 0x1D49 +#define MT6373_RG_LDO_VSIM2_HW0_OP_CFG_ADDR 0x1D4A +#define MT6373_RG_LDO_VSIM2_HW1_OP_CFG_ADDR 0x1D4A +#define MT6373_RG_LDO_VSIM2_HW2_OP_CFG_ADDR 0x1D4A +#define MT6373_RG_LDO_VSIM2_HW3_OP_CFG_ADDR 0x1D4A +#define MT6373_RG_LDO_VSIM2_HW4_OP_CFG_ADDR 0x1D4A +#define MT6373_RG_LDO_VSIM2_HW5_OP_CFG_ADDR 0x1D4A +#define MT6373_RG_LDO_VSIM2_HW6_OP_CFG_ADDR 0x1D4A +#define MT6373_RG_LDO_VSIM2_SW_OP_CFG_ADDR 0x1D4A +#define MT6373_RG_LDO_VSIM2_RC0_OP_MODE_ADDR 0x1D4B +#define MT6373_RG_LDO_VSIM2_RC1_OP_MODE_ADDR 0x1D4B +#define MT6373_RG_LDO_VSIM2_RC2_OP_MODE_ADDR 0x1D4B +#define MT6373_RG_LDO_VSIM2_RC3_OP_MODE_ADDR 0x1D4B +#define MT6373_RG_LDO_VSIM2_RC4_OP_MODE_ADDR 0x1D4B +#define MT6373_RG_LDO_VSIM2_RC5_OP_MODE_ADDR 0x1D4B +#define MT6373_RG_LDO_VSIM2_RC6_OP_MODE_ADDR 0x1D4B +#define MT6373_RG_LDO_VSIM2_RC7_OP_MODE_ADDR 0x1D4B +#define MT6373_RG_LDO_VSIM2_RC8_OP_MODE_ADDR 0x1D4C +#define MT6373_RG_LDO_VSIM2_RC9_OP_MODE_ADDR 0x1D4C +#define MT6373_RG_LDO_VSIM2_RC10_OP_MODE_ADDR 0x1D4C +#define MT6373_RG_LDO_VSIM2_RC11_OP_MODE_ADDR 0x1D4C +#define MT6373_RG_LDO_VSIM2_RC12_OP_MODE_ADDR 0x1D4C +#define MT6373_RG_LDO_VSIM2_RC13_OP_MODE_ADDR 0x1D4C +#define MT6373_RG_LDO_VSIM2_HW0_OP_MODE_ADDR 0x1D4D +#define MT6373_RG_LDO_VSIM2_HW1_OP_MODE_ADDR 0x1D4D +#define MT6373_RG_LDO_VSIM2_HW2_OP_MODE_ADDR 0x1D4D +#define MT6373_RG_LDO_VSIM2_HW3_OP_MODE_ADDR 0x1D4D +#define MT6373_RG_LDO_VSIM2_HW4_OP_MODE_ADDR 0x1D4D +#define MT6373_RG_LDO_VSIM2_HW5_OP_MODE_ADDR 0x1D4D +#define MT6373_RG_LDO_VSIM2_HW6_OP_MODE_ADDR 0x1D4D +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_ONLV_EN_ADDR 0x1D88 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_ONLV_EN_SHIFT 3 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_VOSEL_SLEEP_ADDR 0x1D8D +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC0_OP_EN_ADDR 0x1D94 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC1_OP_EN_ADDR 0x1D94 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC2_OP_EN_ADDR 0x1D94 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC3_OP_EN_ADDR 0x1D94 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC4_OP_EN_ADDR 0x1D94 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC5_OP_EN_ADDR 0x1D94 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC6_OP_EN_ADDR 0x1D94 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC7_OP_EN_ADDR 0x1D94 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC8_OP_EN_ADDR 0x1D95 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC9_OP_EN_ADDR 0x1D95 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC10_OP_EN_ADDR 0x1D95 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC11_OP_EN_ADDR 0x1D95 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC12_OP_EN_ADDR 0x1D95 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC13_OP_EN_ADDR 0x1D95 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW0_OP_EN_ADDR 0x1D96 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW1_OP_EN_ADDR 0x1D96 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW2_OP_EN_ADDR 0x1D96 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW3_OP_EN_ADDR 0x1D96 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW4_OP_EN_ADDR 0x1D96 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW5_OP_EN_ADDR 0x1D96 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW6_OP_EN_ADDR 0x1D96 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_SW_OP_EN_ADDR 0x1D96 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC0_OP_CFG_ADDR 0x1D97 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC1_OP_CFG_ADDR 0x1D97 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC2_OP_CFG_ADDR 0x1D97 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC3_OP_CFG_ADDR 0x1D97 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC4_OP_CFG_ADDR 0x1D97 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC5_OP_CFG_ADDR 0x1D97 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC6_OP_CFG_ADDR 0x1D97 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC7_OP_CFG_ADDR 0x1D97 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC8_OP_CFG_ADDR 0x1D98 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC9_OP_CFG_ADDR 0x1D98 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC10_OP_CFG_ADDR 0x1D98 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC11_OP_CFG_ADDR 0x1D98 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC12_OP_CFG_ADDR 0x1D98 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC13_OP_CFG_ADDR 0x1D98 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW0_OP_CFG_ADDR 0x1D99 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW1_OP_CFG_ADDR 0x1D99 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW2_OP_CFG_ADDR 0x1D99 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW3_OP_CFG_ADDR 0x1D99 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW4_OP_CFG_ADDR 0x1D99 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW5_OP_CFG_ADDR 0x1D99 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW6_OP_CFG_ADDR 0x1D99 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_SW_OP_CFG_ADDR 0x1D99 +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC0_OP_MODE_ADDR 0x1D9A +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC1_OP_MODE_ADDR 0x1D9A +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC2_OP_MODE_ADDR 0x1D9A +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC3_OP_MODE_ADDR 0x1D9A +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC4_OP_MODE_ADDR 0x1D9A +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC5_OP_MODE_ADDR 0x1D9A +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC6_OP_MODE_ADDR 0x1D9A +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC7_OP_MODE_ADDR 0x1D9A +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC8_OP_MODE_ADDR 0x1D9B +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC9_OP_MODE_ADDR 0x1D9B +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC10_OP_MODE_ADDR 0x1D9B +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC11_OP_MODE_ADDR 0x1D9B +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC12_OP_MODE_ADDR 0x1D9B +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC13_OP_MODE_ADDR 0x1D9B +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW0_OP_MODE_ADDR 0x1D9C +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW1_OP_MODE_ADDR 0x1D9C +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW2_OP_MODE_ADDR 0x1D9C +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW3_OP_MODE_ADDR 0x1D9C +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW4_OP_MODE_ADDR 0x1D9C +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW5_OP_MODE_ADDR 0x1D9C +#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW6_OP_MODE_ADDR 0x1D9C + +#endif /* MT6373_LOWPOWER_REG_H */ diff --git a/plat/mediatek/include/drivers/pmic/pmic_psc.h b/plat/mediatek/include/drivers/pmic/pmic_psc.h new file mode 100644 index 000000000..e57dc33ae --- /dev/null +++ b/plat/mediatek/include/drivers/pmic/pmic_psc.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2025, Mediatek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PMIC_PSC_H +#define PMIC_PSC_H + +#include + +enum pmic_psc_reg_name { + RG_PWRHOLD, + RG_CRST, + RG_SMART_RST_SDN_EN, + RG_SMART_RST_MODE, +}; + +struct pmic_psc_reg { + uint16_t reg_addr; + uint16_t reg_mask; + uint16_t reg_shift; +}; + +struct pmic_psc_config { + int (*read_field)(uint32_t reg, uint32_t *val, uint32_t mask, uint32_t shift); + int (*write_field)(uint32_t reg, uint32_t val, uint32_t mask, uint32_t shift); + const struct pmic_psc_reg *regs; + const uint32_t reg_size; +}; + +#define PMIC_PSC_REG(_reg_name, addr, shift) \ + [_reg_name] = { \ + .reg_addr = addr, \ + .reg_mask = 0x1, \ + .reg_shift = shift, \ + } + +int enable_pmic_smart_reset(bool enable); +int enable_pmic_smart_reset_shutdown(bool enable); +int platform_cold_reset(void); +int platform_power_hold(bool hold); +int pmic_psc_register(const struct pmic_psc_config *psc); + +#endif /* PMIC_PSC_H */ diff --git a/plat/mediatek/include/drivers/pmic/pmic_set_lowpower.h b/plat/mediatek/include/drivers/pmic/pmic_set_lowpower.h new file mode 100644 index 000000000..f79612de7 --- /dev/null +++ b/plat/mediatek/include/drivers/pmic/pmic_set_lowpower.h @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2025, Mediatek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PMIC_SET_LOWPOWER_H +#define PMIC_SET_LOWPOWER_H + +#include + +#include + +#include "mt6316_lowpower_reg.h" +#include "mt6363_lowpower_reg.h" +#include "mt6373_lowpower_reg.h" + +#define OP_MODE_MU 0 +#define OP_MODE_LP 1 + +#define HW_OFF 0 +#define HW_ON 0 +#define HW_LP 1 +#define HW_ONLV (0x10 | 1) +#define NORMAL_OP_CFG 0x10 + +enum { + RC0 = 0, + RC1, + RC2, + RC3, + RC4, + RC5, + RC6, + RC7, + RC8 = 0, + RC9, + RC10, + RC11, + RC12, + RC13, + HW0 = 0, + HW1, + HW2, + HW3, + HW4, + HW5, + HW6, + HW7, + HW8 = 0, + HW9, + HW10, + HW11, + HW12, + HW13, +}; + +#define VOTER_EN_SET 1 +#define VOTER_EN_CLR 2 + +enum { + VOTER_EN_LO_BIT0 = 0, + VOTER_EN_LO_BIT1, + VOTER_EN_LO_BIT2, + VOTER_EN_LO_BIT3, + VOTER_EN_LO_BIT4, + VOTER_EN_LO_BIT5, + VOTER_EN_LO_BIT6, + VOTER_EN_LO_BIT7, + VOTER_EN_HI_BIT0 = 0, + VOTER_EN_HI_BIT1, + VOTER_EN_HI_BIT2, + VOTER_EN_HI_BIT3, +}; + +enum { + MT6363_SLAVE = SPMI_SLAVE_4, + MT6368_SLAVE = SPMI_SLAVE_5, + MT6369_SLAVE = SPMI_SLAVE_5, + MT6373_SLAVE = SPMI_SLAVE_5, + MT6316_S6_SLAVE = SPMI_SLAVE_6, + MT6316_S7_SLAVE = SPMI_SLAVE_7, + MT6316_S8_SLAVE = SPMI_SLAVE_8, + MT6316_S15_SLAVE = SPMI_SLAVE_15, + MT6319_S6_SLAVE = SPMI_SLAVE_6, + MT6319_S7_SLAVE = SPMI_SLAVE_7, + MT6319_S8_SLAVE = SPMI_SLAVE_8, + MT6319_S15_SLAVE = SPMI_SLAVE_15, +}; + +extern struct spmi_device *lowpower_sdev[SPMI_MAX_SLAVE_ID]; + +#define PMIC_BUCK_SET_LP(_chip, _name, _user, _en, _mode, _cfg) \ +{ \ + uint8_t val = 0; \ + struct spmi_device *sdev = lowpower_sdev[_chip##_SLAVE]; \ + if (sdev && \ + !spmi_ext_register_readl(sdev, _chip##_RG_BUCK_##_name##_HW0_OP_CFG_ADDR, &val, 1) && \ + !(val & NORMAL_OP_CFG)) {\ + if ((_cfg) == HW_ONLV) { \ + pmic_spmi_update_bits(sdev, \ + _chip##_RG_BUCK_##_name##_ONLV_EN_ADDR, \ + (1 << _chip##_RG_BUCK_##_name##_ONLV_EN_SHIFT), \ + (1 << _chip##_RG_BUCK_##_name##_ONLV_EN_SHIFT)); \ + } else if ((_cfg) == HW_LP) { \ + pmic_spmi_update_bits(sdev, \ + _chip##_RG_BUCK_##_name##_ONLV_EN_ADDR, \ + (1 << _chip##_RG_BUCK_##_name##_ONLV_EN_SHIFT), \ + 0); \ + } \ + pmic_spmi_update_bits(sdev, \ + _chip##_RG_BUCK_##_name##_##_user##_OP_CFG_ADDR, \ + 1 << (_user), \ + ((_cfg) & 0x1) ? 1 << (_user) : 0); \ + pmic_spmi_update_bits(sdev, \ + _chip##_RG_BUCK_##_name##_##_user##_OP_MODE_ADDR, \ + 1 << (_user), \ + (_mode) ? 1 << (_user) : 0); \ + pmic_spmi_update_bits(sdev, \ + _chip##_RG_BUCK_##_name##_##_user##_OP_EN_ADDR, \ + 1 << (_user), \ + (_en) ? 1 << (_user) : 0); \ + } \ +} + +#define PMIC_LDO_SET_LP(_chip, _name, _user, _en, _mode, _cfg) \ +{ \ + uint8_t val = 0; \ + struct spmi_device *sdev = lowpower_sdev[_chip##_SLAVE]; \ + if (sdev && \ + !spmi_ext_register_readl(sdev, _chip##_RG_LDO_##_name##_HW0_OP_CFG_ADDR, &val, 1) && \ + !(val & NORMAL_OP_CFG)) {\ + if ((_cfg) == HW_ONLV) { \ + pmic_spmi_update_bits(sdev, \ + _chip##_RG_LDO_##_name##_ONLV_EN_ADDR, \ + (1 << _chip##_RG_LDO_##_name##_ONLV_EN_SHIFT), \ + (1 << _chip##_RG_LDO_##_name##_ONLV_EN_SHIFT)); \ + } else { \ + pmic_spmi_update_bits(sdev, \ + _chip##_RG_LDO_##_name##_ONLV_EN_ADDR, \ + (1 << _chip##_RG_LDO_##_name##_ONLV_EN_SHIFT), \ + 0); \ + } \ + pmic_spmi_update_bits(sdev, \ + _chip##_RG_LDO_##_name##_##_user##_OP_CFG_ADDR, \ + 1 << (_user), \ + ((_cfg) & 0x1) ? 1 << (_user) : 0); \ + pmic_spmi_update_bits(sdev, \ + _chip##_RG_LDO_##_name##_##_user##_OP_MODE_ADDR, \ + 1 << (_user), \ + (_mode) ? 1 << (_user) : 0); \ + pmic_spmi_update_bits(sdev, \ + _chip##_RG_LDO_##_name##_##_user##_OP_EN_ADDR, \ + 1 << (_user), \ + (_en) ? 1 << (_user) : 0); \ + } \ +} + +#define PMIC_SLVID_BUCK_SET_LP(_chip, _slvid, _name, _user, _en, _mode, _cfg) \ +{ \ + struct spmi_device *sdev = lowpower_sdev[_chip##_##_slvid##_SLAVE]; \ + if (sdev) {\ + pmic_spmi_update_bits(sdev, \ + _chip##_RG_BUCK_##_name##_##_user##_OP_CFG_ADDR, \ + 1 << (_user), \ + (_cfg) ? 1 << (_user) : 0); \ + pmic_spmi_update_bits(sdev, \ + _chip##_RG_BUCK_##_name##_##_user##_OP_MODE_ADDR, \ + 1 << (_user), \ + (_mode) ? 1 << (_user) : 0); \ + pmic_spmi_update_bits(sdev, \ + _chip##_RG_BUCK_##_name##_##_user##_OP_EN_ADDR, \ + 1 << (_user), \ + (_en) ? 1 << (_user) : 0); \ + } \ +} + +#define PMIC_BUCK_VOTER_EN(_chip, _name, _user, _cfg) \ +{ \ + struct spmi_device *sdev = lowpower_sdev[_chip##_SLAVE]; \ + if (sdev) {\ + pmic_spmi_update_bits(sdev, \ + _chip##_RG_BUCK_##_name##_##_user##_ADDR + (_cfg), \ + 1 << (_user), \ + 1 << (_user)); \ + } \ +} + +static inline int pmic_spmi_update_bits(struct spmi_device *sdev, uint16_t reg, + uint8_t mask, uint8_t val) +{ + uint8_t org = 0; + int ret = 0; + + ret = spmi_ext_register_readl(sdev, reg, &org, 1); + if (ret < 0) + return ret; + + org &= ~mask; + org |= val & mask; + + ret = spmi_ext_register_writel(sdev, reg, &org, 1); + return ret; +} + +#endif /* PMIC_SET_LOWPOWER_H */ diff --git a/plat/mediatek/include/drivers/pmic/pmic_shutdown_cfg.h b/plat/mediatek/include/drivers/pmic/pmic_shutdown_cfg.h new file mode 100644 index 000000000..bffb882fd --- /dev/null +++ b/plat/mediatek/include/drivers/pmic/pmic_shutdown_cfg.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025, Mediatek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PMIC_SHUTDOWN_CFG_H +#define PMIC_SHUTDOWN_CFG_H + +#pragma weak spmi_shutdown +int spmi_shutdown(void); +int pmic_shutdown_cfg(void); + +#endif /* PMIC_SHUTDOWN_CFG_H */ diff --git a/plat/mediatek/include/drivers/pmic/pmic_swap_api.h b/plat/mediatek/include/drivers/pmic/pmic_swap_api.h new file mode 100644 index 000000000..fb6720818 --- /dev/null +++ b/plat/mediatek/include/drivers/pmic/pmic_swap_api.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025, Mediatek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PMIC_SWAP_API_H +#define PMIC_SWAP_API_H + +#include + +#include + +bool is_second_pmic_pp_swap(void); + +#endif /* PMIC_SWAP_API_H */ diff --git a/plat/mediatek/mt8196/plat_config.mk b/plat/mediatek/mt8196/plat_config.mk index 0239a3f65..a793f1bee 100644 --- a/plat/mediatek/mt8196/plat_config.mk +++ b/plat/mediatek/mt8196/plat_config.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2024, MediaTek Inc. All rights reserved. +# Copyright (c) 2025, MediaTek Inc. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -47,6 +47,12 @@ CONFIG_MTK_SUPPORT_SYSTEM_SUSPEND := y CONFIG_MTK_TINYSYS_VCP := y CPU_PM_TINYSYS_SUPPORT := y MTK_PUBEVENT_ENABLE := y +CONFIG_MTK_PMIC := y +CONFIG_MTK_PMIC_LOWPOWER := y +CONFIG_MTK_PMIC_SHUTDOWN_CFG := y +CONFIG_MTK_PMIC_SPT_SUPPORT := n + +PMIC_CHIP := mt6363 ENABLE_FEAT_AMU := 1 ENABLE_FEAT_ECV := 1 diff --git a/plat/mediatek/mt8196/platform.mk b/plat/mediatek/mt8196/platform.mk index 8ae8e285d..7e1633e74 100644 --- a/plat/mediatek/mt8196/platform.mk +++ b/plat/mediatek/mt8196/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2024, MediaTek Inc. All rights reserved. +# Copyright (c) 2025, MediaTek Inc. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -33,6 +33,7 @@ MODULES-y += $(MTK_PLAT)/drivers/timer MODULES-y += $(MTK_PLAT)/drivers/vcp MODULES-y += $(MTK_PLAT)/helpers MODULES-y += $(MTK_PLAT)/topology +MODULES-$(CONFIG_MTK_PMIC) += $(MTK_PLAT)/drivers/pmic ifneq ($(MTKLIB_PATH),) LDFLAGS += -L $(dir $(MTKLIB_PATH))