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AArch32: Add generic changes in BL2
This patch adds generic changes in BL2 to support AArch32 state. New AArch32 specific assembly/C files are introduced and some files are moved to AArch32/64 specific folders. BL2 for AArch64 is refactored but functionally identical. BL2 executes in Secure SVC mode in AArch32 state. Change-Id: Ifaacbc2a91f8640876385b953adb24744d9dbde3
This commit is contained in:
Yatharth Kochar
parent
83fc4a930b
commit
d48c12e928
4 changed files with 201 additions and 5 deletions
39
bl2/aarch32/bl2_arch_setup.c
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39
bl2/aarch32/bl2_arch_setup.c
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@ -0,0 +1,39 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*******************************************************************************
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* Place holder function to perform any Secure SVC specific architectural
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* setup. At the moment there is nothing to do.
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******************************************************************************/
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void bl2_arch_setup(void)
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{
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}
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145
bl2/aarch32/bl2_entrypoint.S
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145
bl2/aarch32/bl2_entrypoint.S
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@ -0,0 +1,145 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl_common.h>
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.globl bl2_vector_table
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.globl bl2_entrypoint
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vector_base bl2_vector_table
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b bl2_entrypoint
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b report_exception /* Undef */
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b report_exception /* SVC call */
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b report_exception /* Prefetch abort */
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b report_exception /* Data abort */
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b report_exception /* Reserved */
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b report_exception /* IRQ */
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b report_exception /* FIQ */
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func bl2_entrypoint
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/*---------------------------------------------
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* Save from r1 the extents of the trusted ram
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* available to BL2 for future use.
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* r0 is not currently used.
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* ---------------------------------------------
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*/
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mov r11, r1
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/* ---------------------------------------------
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* Set the exception vector to something sane.
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* ---------------------------------------------
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*/
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ldr r0, =bl2_vector_table
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stcopr r0, VBAR
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isb
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/* -----------------------------------------------------
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* Enable the instruction cache
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* -----------------------------------------------------
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*/
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ldcopr r0, SCTLR
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orr r0, r0, #SCTLR_I_BIT
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stcopr r0, SCTLR
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isb
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/* ---------------------------------------------
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* Since BL2 executes after BL1, it is assumed
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* here that BL1 has already has done the
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* necessary register initializations.
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* ---------------------------------------------
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*/
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/* ---------------------------------------------
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* Invalidate the RW memory used by the BL2
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* image. This includes the data and NOBITS
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* sections. This is done to safeguard against
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* possible corruption of this memory by dirty
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* cache lines in a system cache as a result of
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* use by an earlier boot loader stage.
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* ---------------------------------------------
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*/
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ldr r0, =__RW_START__
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ldr r1, =__RW_END__
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sub r1, r1, r0
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bl inv_dcache_range
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/* ---------------------------------------------
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* Zero out NOBITS sections. There are 2 of them:
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* - the .bss section;
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* - the coherent memory section.
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* ---------------------------------------------
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*/
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ldr r0, =__BSS_START__
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ldr r1, =__BSS_SIZE__
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bl zeromem
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#if USE_COHERENT_MEM
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ldr r0, =__COHERENT_RAM_START__
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ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__
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bl zeromem
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#endif
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/* --------------------------------------------
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* Allocate a stack whose memory will be marked
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* as Normal-IS-WBWA when the MMU is enabled.
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* There is no risk of reading stale stack
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* memory after enabling the MMU as only the
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* primary cpu is running at the moment.
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* --------------------------------------------
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*/
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bl plat_set_my_stack
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/* ---------------------------------------------
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* Perform early platform setup & platform
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* specific early arch. setup e.g. mmu setup
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* ---------------------------------------------
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*/
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mov r0, r11
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bl bl2_early_platform_setup
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bl bl2_plat_arch_setup
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/* ---------------------------------------------
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* Jump to main function.
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* ---------------------------------------------
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*/
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bl bl2_main
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/* ---------------------------------------------
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* Should never reach this point.
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* ---------------------------------------------
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*/
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bl plat_panic_handler
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endfunc bl2_entrypoint
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13
bl2/bl2.mk
13
bl2/bl2.mk
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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@ -29,10 +29,13 @@
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#
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BL2_SOURCES += bl2/bl2_main.c \
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bl2/aarch64/bl2_entrypoint.S \
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bl2/aarch64/bl2_arch_setup.c \
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common/aarch64/early_exceptions.S \
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lib/locks/exclusive/aarch64/spinlock.S
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bl2/${ARCH}/bl2_entrypoint.S \
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bl2/${ARCH}/bl2_arch_setup.c \
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lib/locks/exclusive/${ARCH}/spinlock.S
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ifeq (${ARCH},aarch64)
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BL2_SOURCES += common/aarch64/early_exceptions.S
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endif
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ifeq (${LOAD_IMAGE_V2},1)
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BL2_SOURCES += bl2/bl2_image_load_v2.c
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@ -60,6 +60,15 @@ void bl2_main(void)
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/* Load the subsequent bootloader images. */
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next_bl_ep_info = bl2_load_images();
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#ifdef AARCH32
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/*
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* For AArch32 state BL1 and BL2 share the MMU setup.
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* Given that BL2 does not map BL1 regions, MMU needs
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* to be disabled in order to go back to BL1.
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*/
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disable_mmu_icache_secure();
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#endif /* AARCH32 */
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/*
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* Run next BL image via an SMC to BL1. Information on how to pass
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* control to the BL32 (if present) and BL33 software images will
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