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fix(errata): workaround for Cortex-A510 erratum 2042739

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Cortex-A510 erratum 2042739 is a Cat B erratum that applies to revisions
r0p0, r0p1 and r0p2 and is fixed in r0p3.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2397239

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I1d2ebee3914396e1e298eb45bdab35ce9e194ad9
This commit is contained in:
johpow01 2022-01-07 17:12:31 -06:00 • committed by John Powell
parent d5e2512c6b
commit d48088acbe
4 changed files with 50 additions and 0 deletions
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4
docs/design/cpu-specific-build-macros.rst
View file

@ -484,6 +484,10 @@ For Cortex-A510, the following errata build flags are defined :
Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1,
r0p2, r0p3 and r1p0, it is fixed in r1p1.
- ``ERRATA_A510_2042739``: This applies errata 2042739 workaround to
Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and
r0p2, it is fixed in r0p3.
DSU Errata Workarounds
----------------------

2
include/lib/cpus/aarch64/cortex_a510.h
View file

@ -13,6 +13,8 @@
* CPU Extended Control register specific definitions
******************************************************************************/
#define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4
#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT U(19)
#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE U(1)
/*******************************************************************************
* CPU Power Control register specific definitions

36
lib/cpus/aarch64/cortex_a510.S
View file

@ -80,6 +80,36 @@ func check_errata_2288014
b cpu_rev_var_ls
endfunc check_errata_2288014
/* --------------------------------------------------
* Errata Workaround for Cortex-A510 Errata #2042739.
* This applies only to revisions r0p0, r0p1 and r0p2.
* (fixed in r0p3)
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0, x1, x17
* --------------------------------------------------
*/
func errata_cortex_a510_2042739_wa
/* Check workaround compatibility. */
mov x17, x30
bl check_errata_2042739
cbz x0, 1f
/* Apply the workaround by disabling ReadPreferUnique. */
mrs x0, CORTEX_A510_CPUECTLR_EL1
mov x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE
bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, #1
msr CORTEX_A510_CPUECTLR_EL1, x0
1:
ret x17
endfunc errata_cortex_a510_2042739_wa
func check_errata_2042739
/* Applies to revisions r0p0 - r0p2 */
mov x1, #0x02
b cpu_rev_var_ls
endfunc check_errata_2042739
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
@ -112,6 +142,7 @@ func cortex_a510_errata_report
*/
report_errata ERRATA_A510_1922240, cortex_a510, 1922240
report_errata ERRATA_A510_2288014, cortex_a510, 2288014
report_errata ERRATA_A510_2042739, cortex_a510, 2042739
ldp x8, x30, [sp], #16
ret
@ -139,6 +170,11 @@ func cortex_a510_reset_func
bl errata_cortex_a510_2288014_wa
#endif
#if ERRATA_A510_2042739
mov x0, x18
bl errata_cortex_a510_2042739_wa
#endif
ret x19
endfunc cortex_a510_reset_func

8
lib/cpus/cpu-ops.mk
View file

@ -539,6 +539,10 @@ ERRATA_A510_1922240 ?=0
# fixed in r1p1.
ERRATA_A510_2288014 ?=0
# Flag to apply erratum 2042739 workaround during reset. This erratum applies
# to revisions r0p0, r0p1 and r0p2 of the Cortex-A510 cpu and is fixed in r0p3.
ERRATA_A510_2042739 ?=0
# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
# Applying the workaround results in higher DSU power consumption on idle.
ERRATA_DSU_798953 ?=0
@ -1004,6 +1008,10 @@ $(eval $(call add_define,ERRATA_A510_1922240))
$(eval $(call assert_boolean,ERRATA_A510_2288014))
$(eval $(call add_define,ERRATA_A510_2288014))
# Process ERRATA_A510_2042739 flag
$(eval $(call assert_boolean,ERRATA_A510_2042739))
$(eval $(call add_define,ERRATA_A510_2042739))
# Process ERRATA_DSU_798953 flag
$(eval $(call assert_boolean,ERRATA_DSU_798953))
$(eval $(call add_define,ERRATA_DSU_798953))