mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-23 13:36:05 +00:00
feat(fvp): enable errata management interface
Errata ABI feature specific build flag, flag to enable CPUs in the cpu list, flags to test non-arm interconnect based errata flags when enabled from a platform level. Added to the FVP platform makefile to test the errata abi feature implementation. The flags to enable CPUs in the cpu list will be removed once synchronized with the errata framework. Change-Id: I30877a22ac1348906a6ddfb26f9e8839912d3572 Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
This commit is contained in:
parent
ab062f0510
commit
d3bed15851
2 changed files with 65 additions and 0 deletions
61
plat/arm/board/fvp/fvp_cpu_errata.mk
Normal file
61
plat/arm/board/fvp/fvp_cpu_errata.mk
Normal file
|
@ -0,0 +1,61 @@
|
|||
#
|
||||
# Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
|
||||
#/*
|
||||
# * TODO: below lines of code to be removed
|
||||
# * after abi and framework are synchronized
|
||||
# */
|
||||
|
||||
ifeq (${ERRATA_ABI_SUPPORT}, 1)
|
||||
# enable the cpu macros for errata abi interface
|
||||
ifeq (${ARCH}, aarch64)
|
||||
ifeq (${HW_ASSISTED_COHERENCY}, 0)
|
||||
CORTEX_A35_H_INC := 1
|
||||
CORTEX_A53_H_INC := 1
|
||||
CORTEX_A57_H_INC := 1
|
||||
CORTEX_A72_H_INC := 1
|
||||
CORTEX_A73_H_INC := 1
|
||||
$(eval $(call add_define, CORTEX_A35_H_INC))
|
||||
$(eval $(call add_define, CORTEX_A53_H_INC))
|
||||
$(eval $(call add_define, CORTEX_A57_H_INC))
|
||||
$(eval $(call add_define, CORTEX_A72_H_INC))
|
||||
$(eval $(call add_define, CORTEX_A73_H_INC))
|
||||
else
|
||||
ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0)
|
||||
CORTEX_A76_H_INC := 1
|
||||
CORTEX_A77_H_INC := 1
|
||||
CORTEX_A78_H_INC := 1
|
||||
NEOVERSE_N1_H_INC := 1
|
||||
NEOVERSE_V1_H_INC := 1
|
||||
CORTEX_A78_AE_H_INC := 1
|
||||
CORTEX_A510_H_INC := 1
|
||||
CORTEX_A710_H_INC := 1
|
||||
CORTEX_A715_H_INC := 1
|
||||
CORTEX_A78C_H_INC := 1
|
||||
CORTEX_X2_H_INC := 1
|
||||
$(eval $(call add_define, CORTEX_A76_H_INC))
|
||||
$(eval $(call add_define, CORTEX_A77_H_INC))
|
||||
$(eval $(call add_define, CORTEX_A78_H_INC))
|
||||
$(eval $(call add_define, NEOVERSE_N1_H_INC))
|
||||
$(eval $(call add_define, NEOVERSE_V1_H_INC))
|
||||
$(eval $(call add_define, CORTEX_A78_AE_H_INC))
|
||||
$(eval $(call add_define, CORTEX_A510_H_INC))
|
||||
$(eval $(call add_define, CORTEX_A710_H_INC))
|
||||
$(eval $(call add_define, CORTEX_A715_H_INC))
|
||||
$(eval $(call add_define, CORTEX_A78C_H_INC))
|
||||
$(eval $(call add_define, CORTEX_X2_H_INC))
|
||||
endif
|
||||
CORTEX_A55_H_INC := 1
|
||||
CORTEX_A75_H_INC := 1
|
||||
$(eval $(call add_define, CORTEX_A55_H_INC))
|
||||
$(eval $(call add_define, CORTEX_A75_H_INC))
|
||||
endif
|
||||
else
|
||||
CORTEX_A32_H_INC := 1
|
||||
$(eval $(call add_define, CORTEX_A32_H_INC))
|
||||
endif
|
||||
endif
|
|
@ -516,3 +516,7 @@ endif
|
|||
ifeq (${SPD},spmd)
|
||||
BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c
|
||||
endif
|
||||
|
||||
ifeq (${ERRATA_ABI_SUPPORT}, 1)
|
||||
include plat/arm/board/fvp/fvp_cpu_errata.mk
|
||||
endif
|
||||
|
|
Loading…
Add table
Reference in a new issue