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feat(nxp/common/rcpm): add RCPM2 registers definition

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Added some RCPM2 register offset definiton for register: IPSTPCR,
IPSTPACKR and POWMGTDCR, also added OVRD bit definiton of register
POWMGTDCR.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I301bc1401e053c2089b5eb3672c6e649c805a2ab
This commit is contained in:
Jiafei Pan 2021-10-21 15:28:37 +08:00
parent 0259a3e828
commit d374060abe
1 changed files with 17 additions and 0 deletions
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17
plat/nxp/common/include/default/ch_2/soc_default_helper_macros.h
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@ -56,6 +56,23 @@
#define RCPM_POWMGTCSR_OFFSET 0x130 #define RCPM_POWMGTCSR_OFFSET 0x130
#define RCPM_IPPDEXPCR0_OFFSET 0x140 #define RCPM_IPPDEXPCR0_OFFSET 0x140
#define RCPM_POWMGTCSR_LPM20_REQ 0x00100000 #define RCPM_POWMGTCSR_LPM20_REQ 0x00100000
#define RCPM2_IPSTPCR0_OFFSET 0x8
#define RCPM2_IPSTPCR1_OFFSET 0xC
#define RCPM2_IPSTPCR2_OFFSET 0x10
#define RCPM2_IPSTPCR3_OFFSET 0x14
#define RCPM2_IPSTPCR4_OFFSET 0x28
#define RCPM2_IPSTPACKR0_OFFSET 0x18
#define RCPM2_IPSTPACKR1_OFFSET 0x1C
#define RCPM2_IPSTPACKR2_OFFSET 0x20
#define RCPM2_IPSTPACKR3_OFFSET 0x24
#define RCPM2_IPSTPACKR4_OFFSET 0x2C
#define RCPM2_POWMGTDCR_OFFSET 0x0
/* bitfield masks */
#define POWMGTDCR_OVRD_EN 0x80000000
#endif /* NXP_RCPM_ADDR */ #endif /* NXP_RCPM_ADDR */
#define DCFG_SBEESR2_ADDR 0x20140534 #define DCFG_SBEESR2_ADDR 0x20140534