mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 10:04:26 +00:00
Merge changes from topic "msm8916-plats" into integration
* changes: docs(msm8916): document new platforms feat(msm8916): add port for MDM9607 refactor(msm8916): handle single core platforms feat(msm8916): add port for MSM8939 feat(msm8916): power on L2 caches for secondary clusters feat(msm8916): initialize CCI-400 for multiple clusters refactor(msm8916): handle multiple CPU clusters feat(msm8916): add port for MSM8909 feat(msm8916): clear CACHE_LOCK for MMU-500 r2p0+ style(msm8916): add missing braces to while statements
This commit is contained in:
Manish V Badarkhe
TrustedFirmware Code Review
commit
d1b5ada888
23 changed files with 448 additions and 86 deletions
|
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@ -698,7 +698,10 @@ QTI MSM8916 platform port
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:|M|: Nikita Travkin <nikita@trvn.ru>
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:|G|: `TravMurav`_
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:|F|: docs/plat/qti-msm8916.rst
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:|F|: plat/qti/mdm9607/
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:|F|: plat/qti/msm8909/
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:|F|: plat/qti/msm8916/
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:|F|: plat/qti/msm8939/
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Raspberry Pi 3 platform port
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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|
|
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@ -1,16 +1,27 @@
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Qualcomm Snapdragon 410 (MSM8916/APQ8016)
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=========================================
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Qualcomm MSM8916
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================
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The MSM8916 platform port in TF-A supports multiple similar Qualcomm SoCs:
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The `Qualcomm Snapdragon 410`_ is Qualcomm's first 64-bit SoC, released in 2014
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with four ARM Cortex-A53 cores. There are differents variants (MSM8916,
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APQ8016(E), ...) that are all very similar. A popular device based on APQ8016E
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is the `DragonBoard 410c`_ single-board computer, but the SoC is also used in
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various mid-range smartphones/tablets.
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+-----------------------+----------------+-------------------+-----------------+
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| System-on-Chip (SoC) | TF-A Platform | Application CPU | Supports |
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+=======================+================+===================+=================+
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| `Snapdragon 410`_ |``PLAT=msm8916``| 4x ARM Cortex-A53 | AArch64/AArch32 |
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| (MSM8x16, APQ8016(E)) | | | |
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| (`DragonBoard 410c`_) | | | |
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+-----------------------+----------------+-------------------+-----------------+
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| `Snapdragon 615`_ |``PLAT=msm8939``| 4x ARM Cortex-A53 | AArch64/AArch32 |
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| (MSM8x39, APQ8039) | | 4x ARM Cortex-A53 | |
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+-----------------------+----------------+-------------------+-----------------+
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| `Snapdragon 210`_ |``PLAT=msm8909``| 4x ARM Cortex-A7 | AArch32 only |
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| (MSM8x09, APQ8009) | | | |
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+-----------------------+----------------+-------------------+-----------------+
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| `Snapdragon X5 Modem`_|``PLAT=mdm9607``| 1x ARM Cortex-A7 | AArch32 only |
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| (MDM9x07) | | | |
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+-----------------------+----------------+-------------------+-----------------+
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The TF-A port for MSM8916 provides a minimal, community-maintained
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EL3 firmware. It is primarily based on information from the public
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`Snapdragon 410E Technical Reference Manual`_ combined with a lot of
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trial and error to actually make it work.
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It provides a minimal, community-maintained EL3 firmware and PSCI implementation,
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based on information from the public `Snapdragon 410E Technical Reference Manual`_
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combined with a lot of trial and error to actually make it work.
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.. note::
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Unlike the :doc:`QTI SC7180/SC7280 <qti>` ports, this port does **not**
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@ -56,24 +67,27 @@ booted using an additional shim loader such as `tfalkstub`_.
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Build
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-----
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It is possible to build for either AArch64 or AArch32. AArch64 is the preferred
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build option.
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It is possible to build for either AArch64 or AArch32. Some platforms use 32-bit
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CPUs that only support AArch32 (see table above). For all others AArch64 is the
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preferred build option.
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AArch64 (BL31)
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^^^^^^^^^^^^^^
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Setup the cross compiler for AArch64 and build BL31 for ``msm8916``::
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Setup the cross compiler for AArch64 and build BL31 for one of the platforms in
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the table above::
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$ make CROSS_COMPILE=aarch64-none-elf- PLAT=msm8916
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$ make CROSS_COMPILE=aarch64-none-elf- PLAT=...
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The BL31 ELF image is generated in ``build/msm8916/release/bl31/bl31.elf``.
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The BL31 ELF image is generated in ``build/$PLAT/release/bl31/bl31.elf``.
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AArch32 (BL32/SP_MIN)
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^^^^^^^^^^^^^^^^^^^^^
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Setup the cross compiler for AArch32 and build BL32 with SP_MIN for ``msm8916``::
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Setup the cross compiler for AArch32 and build BL32 with SP_MIN for one of the
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platforms in the table above::
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$ make CROSS_COMPILE=arm-none-eabi- PLAT=msm8916 ARCH=aarch32 AARCH32_SP=sp_min
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$ make CROSS_COMPILE=arm-none-eabi- PLAT=... ARCH=aarch32 AARCH32_SP=sp_min
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The BL32 ELF image is generated in ``build/msm8916/release/bl32/bl32.elf``.
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The BL32 ELF image is generated in ``build/$PLAT/release/bl32/bl32.elf``.
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Build Options
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-------------
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@ -186,7 +200,10 @@ this (with ``DEBUG=1``, otherwise only the ``NOTICE`` lines are shown)::
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[0] welcome to lk
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...
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.. _Qualcomm Snapdragon 410: https://www.qualcomm.com/products/snapdragon-processors-410
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.. _Snapdragon 210: https://www.qualcomm.com/products/snapdragon-processors-210
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.. _Snapdragon 410: https://www.qualcomm.com/products/snapdragon-processors-410
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.. _Snapdragon 615: https://www.qualcomm.com/products/snapdragon-processors-615
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.. _Snapdragon X5 Modem: https://www.qualcomm.com/products/snapdragon-modems-4g-lte-x5
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.. _DragonBoard 410c: https://www.96boards.org/product/dragonboard410c/
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.. _Snapdragon 410E Technical Reference Manual: https://developer.qualcomm.com/download/sd410/snapdragon-410e-technical-reference-manual.pdf
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.. _U-Boot for DragonBoard 410c: https://u-boot.readthedocs.io/en/latest/board/qualcomm/dragonboard410c.html
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14
plat/qti/mdm9607/platform.mk
Normal file
14
plat/qti/mdm9607/platform.mk
Normal file
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@ -0,0 +1,14 @@
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#
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# Copyright (c) 2022-2023, Stephan Gerhold <stephan@gerhold.net>
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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ARM_ARCH_MAJOR := 7
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ARM_CORTEX_A7 := yes
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BL31_BASE ?= 0x87e00000
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PRELOADED_BL33_BASE ?= 0x82900000
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QTI_UART_NUM ?= 5
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include plat/qti/msm8916/platform.mk
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7
plat/qti/mdm9607/sp_min/sp_min-mdm9607.mk
Normal file
7
plat/qti/mdm9607/sp_min/sp_min-mdm9607.mk
Normal file
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@ -0,0 +1,7 @@
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#
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# Copyright (c) 2022-2023, Stephan Gerhold <stephan@gerhold.net>
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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include plat/qti/msm8916/sp_min/sp_min-msm8916.mk
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13
plat/qti/msm8909/platform.mk
Normal file
13
plat/qti/msm8909/platform.mk
Normal file
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@ -0,0 +1,13 @@
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#
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# Copyright (c) 2022-2023, Stephan Gerhold <stephan@gerhold.net>
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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ARM_ARCH_MAJOR := 7
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ARM_CORTEX_A7 := yes
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BL31_BASE ?= 0x87e80000
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QTI_UART_NUM ?= 1
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include plat/qti/msm8916/platform.mk
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7
plat/qti/msm8909/sp_min/sp_min-msm8909.mk
Normal file
7
plat/qti/msm8909/sp_min/sp_min-msm8909.mk
Normal file
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@ -0,0 +1,7 @@
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#
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# Copyright (c) 2022-2023, Stephan Gerhold <stephan@gerhold.net>
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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include plat/qti/msm8916/sp_min/sp_min-msm8916.mk
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@ -6,10 +6,15 @@
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#include <arch.h>
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#include <asm_macros.S>
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#include <platform_def.h>
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#include <msm8916_mmap.h>
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#if PLATFORM_CORE_COUNT > 1
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#define APCS_TCM_START_ADDR 0x10
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#else
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#define APCS_TCM_START_ADDR 0x34
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#endif
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#define APCS_TCM_REDIRECT_EN_0 BIT_32(0)
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.globl plat_crash_console_init
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@ -79,9 +84,18 @@ endfunc plat_panic_handler
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* -------------------------------------------------
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*/
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func plat_my_core_pos
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/* There is just a single cluster so this is very simple */
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ldcopr r0, MPIDR
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and r0, r0, #MPIDR_CPU_MASK
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.if PLATFORM_CORE_COUNT > 1
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ldcopr r1, MPIDR
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and r0, r1, #MPIDR_CPU_MASK
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.if PLATFORM_CLUSTER_COUNT > 1
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and r1, r1, #MPIDR_CLUSTER_MASK
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orr r0, r0, r1, LSR #(MPIDR_AFFINITY_BITS - \
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PLATFORM_CPU_PER_CLUSTER_SHIFT)
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.endif
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.else
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/* There is just a single core so always 0 */
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mov r0, #0
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.endif
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bx lr
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endfunc plat_my_core_pos
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@ -102,7 +116,7 @@ func plat_get_my_entrypoint
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* Cold boot: Disable TCM redirect to L2 cache as early as
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* possible to avoid crashes when making use of the cache.
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*/
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ldr r1, =APCS_CFG
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ldr r1, =APCS_CFG(0)
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ldr r2, [r1, #APCS_TCM_START_ADDR]
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and r2, r2, #~APCS_TCM_REDIRECT_EN_0
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str r2, [r1, #APCS_TCM_START_ADDR]
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@ -6,10 +6,15 @@
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#include <arch.h>
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#include <asm_macros.S>
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#include <platform_def.h>
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#include <msm8916_mmap.h>
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#if PLATFORM_CORE_COUNT > 1
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#define APCS_TCM_START_ADDR 0x10
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#else
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#define APCS_TCM_START_ADDR 0x34
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#endif
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#define APCS_TCM_REDIRECT_EN_0 BIT_32(0)
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.globl plat_crash_console_init
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@ -78,9 +83,18 @@ endfunc plat_panic_handler
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* -------------------------------------------------
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*/
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func plat_my_core_pos
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/* There is just a single cluster so this is very simple */
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mrs x0, mpidr_el1
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and x0, x0, #MPIDR_CPU_MASK
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.if PLATFORM_CORE_COUNT > 1
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mrs x1, mpidr_el1
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and x0, x1, #MPIDR_CPU_MASK
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.if PLATFORM_CLUSTER_COUNT > 1
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and x1, x1, #MPIDR_CLUSTER_MASK
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orr x0, x0, x1, LSR #(MPIDR_AFFINITY_BITS - \
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PLATFORM_CPU_PER_CLUSTER_SHIFT)
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.endif
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.else
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/* There is just a single core so always 0 */
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mov x0, #0
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.endif
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ret
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endfunc plat_my_core_pos
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@ -100,7 +114,7 @@ func plat_get_my_entrypoint
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* Cold boot: Disable TCM redirect to L2 cache as early as
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* possible to avoid crashes when making use of the cache.
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*/
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mov_imm x1, APCS_CFG
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mov_imm x1, APCS_CFG(0)
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ldr w2, [x1, #APCS_TCM_START_ADDR]
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and w2, w2, #~APCS_TCM_REDIRECT_EN_0
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str w2, [x1, #APCS_TCM_START_ADDR]
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|
|
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@ -22,6 +22,7 @@
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#define APPS_SMMU_BASE (PCNOC_BASE + 0x1e00000)
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#define APPS_SMMU_QCOM (APPS_SMMU_BASE + 0xf0000)
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#define GPU_SMMU_BASE (PCNOC_BASE + 0x1f00000)
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#define BLSP1_BASE (PCNOC_BASE + 0x7880000)
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#define BLSP1_UART_BASE(n) (BLSP1_BASE + 0x2f000 + (((n) - 1) * 0x1000))
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@ -32,11 +33,19 @@
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#define APCS_QGIC2_GICC (APCS_QGIC2_BASE + 0x2000)
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#define APCS_BANKED_ACS (APCS_BASE + 0x08000)
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#define APCS_BANKED_SAW2 (APCS_BASE + 0x09000)
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#define APCS_CFG (APCS_BASE + 0x10000)
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#define APCS_GLB (APCS_BASE + 0x11000)
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#define APCS_L2_SAW2 (APCS_BASE + 0x12000)
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#define APCS_QTMR (APCS_BASE + 0x20000)
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#define APCS_ALIAS_ACS(cpu) (APCS_BASE + 0x88000 + ((cpu) * 0x10000))
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#define APCS_ALIAS_SAW2(cpu) (APCS_BASE + 0x89000 + ((cpu) * 0x10000))
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#define _APCS_CLUSTER(cluster) (APCS_BASE + ((cluster) * 0x100000))
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#define _APCS_CPU(cluster, cpu) (_APCS_CLUSTER(cluster) + ((cpu) * 0x10000))
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#define APCS_CFG(cluster) (_APCS_CLUSTER(cluster) + 0x10000)
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#define APCS_GLB(cluster) (_APCS_CLUSTER(cluster) + 0x11000)
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#define APCS_L2_SAW2(cluster) (_APCS_CLUSTER(cluster) + 0x12000)
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#define APCS_QTMR(cluster) (_APCS_CLUSTER(cluster) + 0x20000)
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#define APCS_ALIAS_ACS(cluster, cpu) (_APCS_CPU(cluster, cpu) + 0x88000)
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#define APCS_ALIAS_SAW2(cluster, cpu) (_APCS_CPU(cluster, cpu) + 0x89000)
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/* Only on platforms with multiple clusters (e.g. MSM8939) */
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#define APCS_CCI_BASE (APCS_BASE + 0x1c0000)
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#define APCS_CCI_SAW2 (APCS_BASE + 0x1d2000)
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#define APCS_CCI_ACS (APCS_BASE + 0x1d4000)
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#endif /* MSM8916_MMAP_H */
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|
|
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|||
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|
@ -25,11 +25,20 @@
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#define CACHE_WRITEBACK_GRANULE U(64)
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#define PLATFORM_STACK_SIZE SZ_4K
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|
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/* CPU topology: single cluster with 4 cores */
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/* CPU topology: one or two clusters with 4 cores each */
|
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#ifdef PLAT_msm8939
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#define PLATFORM_CLUSTER_COUNT U(2)
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#else
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#define PLATFORM_CLUSTER_COUNT U(1)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
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#endif
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#if defined(PLAT_mdm9607)
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#define PLATFORM_CPU_PER_CLUSTER_SHIFT U(0) /* 1 */
|
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#else
|
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#define PLATFORM_CPU_PER_CLUSTER_SHIFT U(2) /* 4 */
|
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#endif
|
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#define PLATFORM_CPUS_PER_CLUSTER (1 << PLATFORM_CPU_PER_CLUSTER_SHIFT)
|
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
|
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PLATFORM_MAX_CPUS_PER_CLUSTER)
|
||||
PLATFORM_CPUS_PER_CLUSTER)
|
||||
|
||||
/* Power management */
|
||||
#define PLATFORM_SYSTEM_COUNT U(1)
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
|
|||
u_register_t arg2, u_register_t arg3)
|
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{
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msm8916_early_platform_setup();
|
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msm8916_configure_early();
|
||||
}
|
||||
|
||||
void bl31_plat_arch_setup(void)
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
#include <assert.h>
|
||||
|
||||
#include <arch.h>
|
||||
#include <drivers/arm/cci.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include "msm8916_config.h"
|
||||
|
|
@ -14,13 +15,23 @@
|
|||
#include <msm8916_mmap.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
static void msm8916_configure_timer(void)
|
||||
static const int cci_map[] = { 3, 4 };
|
||||
|
||||
void msm8916_configure_early(void)
|
||||
{
|
||||
if (PLATFORM_CLUSTER_COUNT > 1) {
|
||||
cci_init(APCS_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
|
||||
cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
|
||||
}
|
||||
}
|
||||
|
||||
static void msm8916_configure_timer(uintptr_t base)
|
||||
{
|
||||
/* Set timer frequency */
|
||||
mmio_write_32(APCS_QTMR + CNTCTLBASE_CNTFRQ, PLAT_SYSCNT_FREQ);
|
||||
mmio_write_32(base + CNTCTLBASE_CNTFRQ, PLAT_SYSCNT_FREQ);
|
||||
|
||||
/* Make all timer frames available to non-secure world */
|
||||
mmio_write_32(APCS_QTMR + CNTNSAR, GENMASK_32(7, 0));
|
||||
mmio_write_32(base + CNTNSAR, GENMASK_32(7, 0));
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -30,16 +41,21 @@ static void msm8916_configure_timer(void)
|
|||
*/
|
||||
#define APCS_GLB_SECURE_STS_NS BIT_32(0)
|
||||
#define APCS_GLB_SECURE_PWR_NS BIT_32(1)
|
||||
#define APCS_BOOT_START_ADDR_SEC (APCS_CFG + 0x04)
|
||||
#if PLATFORM_CORE_COUNT > 1
|
||||
#define APCS_BOOT_START_ADDR_SEC 0x04
|
||||
#define APCS_AA64NAA32_REG 0x0c
|
||||
#else
|
||||
#define APCS_BOOT_START_ADDR_SEC 0x18
|
||||
#endif
|
||||
#define REMAP_EN BIT_32(0)
|
||||
#define APCS_AA64NAA32_REG (APCS_CFG + 0x0c)
|
||||
|
||||
static void msm8916_configure_cpu_pm(void)
|
||||
static void msm8916_configure_apcs_cluster(unsigned int cluster)
|
||||
{
|
||||
uintptr_t cfg = APCS_CFG(cluster);
|
||||
unsigned int cpu;
|
||||
|
||||
/* Disallow non-secure access to boot remapper / TCM registers */
|
||||
mmio_write_32(APCS_CFG, 0);
|
||||
mmio_write_32(cfg, 0);
|
||||
|
||||
/*
|
||||
* Disallow non-secure access to power management registers.
|
||||
|
|
@ -47,27 +63,51 @@ static void msm8916_configure_cpu_pm(void)
|
|||
* to CPU frequency related registers (e.g. APCS_CMD_RCGR). If these
|
||||
* bits are not set, CPU frequency control fails in the non-secure world.
|
||||
*/
|
||||
mmio_write_32(APCS_GLB, APCS_GLB_SECURE_STS_NS | APCS_GLB_SECURE_PWR_NS);
|
||||
mmio_write_32(APCS_GLB(cluster),
|
||||
APCS_GLB_SECURE_STS_NS | APCS_GLB_SECURE_PWR_NS);
|
||||
|
||||
/* Disallow non-secure access to L2 SAW2 */
|
||||
mmio_write_32(APCS_L2_SAW2, 0);
|
||||
if (PLATFORM_CORE_COUNT > 1) {
|
||||
/* Disallow non-secure access to L2 SAW2 */
|
||||
mmio_write_32(APCS_L2_SAW2(cluster), 0);
|
||||
|
||||
/* Disallow non-secure access to CPU ACS and SAW2 */
|
||||
for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) {
|
||||
mmio_write_32(APCS_ALIAS_ACS(cpu), 0);
|
||||
mmio_write_32(APCS_ALIAS_SAW2(cpu), 0);
|
||||
/* Disallow non-secure access to CPU ACS and SAW2 */
|
||||
for (cpu = 0; cpu < PLATFORM_CPUS_PER_CLUSTER; cpu++) {
|
||||
mmio_write_32(APCS_ALIAS_ACS(cluster, cpu), 0);
|
||||
mmio_write_32(APCS_ALIAS_SAW2(cluster, cpu), 0);
|
||||
}
|
||||
} else {
|
||||
/* There is just one core so no aliases exist */
|
||||
mmio_write_32(APCS_BANKED_ACS, 0);
|
||||
mmio_write_32(APCS_BANKED_SAW2, 0);
|
||||
}
|
||||
|
||||
#ifdef __aarch64__
|
||||
/* Make sure all further warm boots end up in BL31 and aarch64 state */
|
||||
CASSERT((BL31_BASE & 0xffff) == 0, assert_bl31_base_64k_aligned);
|
||||
mmio_write_32(APCS_BOOT_START_ADDR_SEC, BL31_BASE | REMAP_EN);
|
||||
mmio_write_32(APCS_AA64NAA32_REG, 1);
|
||||
mmio_write_32(cfg + APCS_BOOT_START_ADDR_SEC, BL31_BASE | REMAP_EN);
|
||||
mmio_write_32(cfg + APCS_AA64NAA32_REG, 1);
|
||||
#else
|
||||
/* Make sure all further warm boots end up in BL32 */
|
||||
CASSERT((BL32_BASE & 0xffff) == 0, assert_bl32_base_64k_aligned);
|
||||
mmio_write_32(APCS_BOOT_START_ADDR_SEC, BL32_BASE | REMAP_EN);
|
||||
mmio_write_32(cfg + APCS_BOOT_START_ADDR_SEC, BL32_BASE | REMAP_EN);
|
||||
#endif
|
||||
|
||||
msm8916_configure_timer(APCS_QTMR(cluster));
|
||||
}
|
||||
|
||||
static void msm8916_configure_apcs(void)
|
||||
{
|
||||
unsigned int cluster;
|
||||
|
||||
for (cluster = 0; cluster < PLATFORM_CLUSTER_COUNT; cluster++) {
|
||||
msm8916_configure_apcs_cluster(cluster);
|
||||
}
|
||||
|
||||
if (PLATFORM_CLUSTER_COUNT > 1) {
|
||||
/* Disallow non-secure access to CCI ACS and SAW2 */
|
||||
mmio_write_32(APCS_CCI_ACS, 0);
|
||||
mmio_write_32(APCS_CCI_SAW2, 0);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -77,30 +117,79 @@ static void msm8916_configure_cpu_pm(void)
|
|||
* by default to avoid special setup on the non-secure side.
|
||||
*/
|
||||
#define CLK_OFF BIT_32(31)
|
||||
#define GCC_APSS_TCU_CBCR (GCC_BASE + 0x12018)
|
||||
#define GCC_GFX_TCU_CBCR (GCC_BASE + 0x12020)
|
||||
#define GCC_SMMU_CFG_CBCR (GCC_BASE + 0x12038)
|
||||
#define GCC_RPM_SMMU_CLOCK_BRANCH_ENA_VOTE (GCC_BASE + 0x3600c)
|
||||
#define GCC_APCS_SMMU_CLOCK_BRANCH_ENA_VOTE (GCC_BASE + 0x4500c)
|
||||
#define APSS_TCU_CLK_ENA BIT_32(1)
|
||||
#define GFX_TCU_CLK_ENA BIT_32(2)
|
||||
#define GFX_TBU_CLK_ENA BIT_32(3)
|
||||
#define SMMU_CFG_CLK_ENA BIT_32(12)
|
||||
#define APPS_SMMU_INTR_SEL_NS (APPS_SMMU_QCOM + 0x2000)
|
||||
#define APPS_SMMU_INTR_SEL_NS_EN_ALL U(0xffffffff)
|
||||
|
||||
#define SMMU_SACR 0x010
|
||||
#define SMMU_SACR_CACHE_LOCK BIT_32(26)
|
||||
#define SMMU_IDR7 0x03c
|
||||
#define SMMU_IDR7_MINOR(val) (((val) >> 0) & 0xf)
|
||||
#define SMMU_IDR7_MAJOR(val) (((val) >> 4) & 0xf)
|
||||
|
||||
static void msm8916_smmu_cache_unlock(uintptr_t smmu_base, uintptr_t clk_cbcr)
|
||||
{
|
||||
uint32_t version;
|
||||
|
||||
/* Wait for clock */
|
||||
while (mmio_read_32(clk_cbcr) & CLK_OFF) {
|
||||
}
|
||||
|
||||
version = mmio_read_32(smmu_base + SMMU_IDR7);
|
||||
VERBOSE("SMMU(0x%lx) r%dp%d\n", smmu_base,
|
||||
SMMU_IDR7_MAJOR(version), SMMU_IDR7_MINOR(version));
|
||||
|
||||
/* For SMMU r2p0+ clear CACHE_LOCK to allow writes to CBn_ACTLR */
|
||||
if (SMMU_IDR7_MAJOR(version) >= 2) {
|
||||
mmio_clrbits_32(smmu_base + SMMU_SACR, SMMU_SACR_CACHE_LOCK);
|
||||
}
|
||||
}
|
||||
|
||||
static void msm8916_configure_smmu(void)
|
||||
{
|
||||
/* Enable SMMU configuration clock to enable register access */
|
||||
mmio_setbits_32(GCC_APCS_SMMU_CLOCK_BRANCH_ENA_VOTE, SMMU_CFG_CLK_ENA);
|
||||
while (mmio_read_32(GCC_SMMU_CFG_CBCR) & CLK_OFF)
|
||||
;
|
||||
uint32_t ena_bits = APSS_TCU_CLK_ENA | SMMU_CFG_CLK_ENA;
|
||||
|
||||
/* Single core (MDM) platforms do not have a GPU */
|
||||
if (PLATFORM_CORE_COUNT > 1) {
|
||||
ena_bits |= GFX_TCU_CLK_ENA | GFX_TBU_CLK_ENA;
|
||||
}
|
||||
|
||||
/* Enable SMMU clocks to enable register access */
|
||||
mmio_write_32(GCC_APCS_SMMU_CLOCK_BRANCH_ENA_VOTE, ena_bits);
|
||||
|
||||
/* Wait for configuration clock */
|
||||
while (mmio_read_32(GCC_SMMU_CFG_CBCR) & CLK_OFF) {
|
||||
}
|
||||
|
||||
/* Route all context bank interrupts to non-secure interrupt */
|
||||
mmio_write_32(APPS_SMMU_INTR_SEL_NS, APPS_SMMU_INTR_SEL_NS_EN_ALL);
|
||||
|
||||
/* Disable configuration clock again */
|
||||
mmio_clrbits_32(GCC_APCS_SMMU_CLOCK_BRANCH_ENA_VOTE, SMMU_CFG_CLK_ENA);
|
||||
/* Clear sACR.CACHE_LOCK bit if needed for MMU-500 r2p0+ */
|
||||
msm8916_smmu_cache_unlock(APPS_SMMU_BASE, GCC_APSS_TCU_CBCR);
|
||||
if (PLATFORM_CORE_COUNT > 1) {
|
||||
msm8916_smmu_cache_unlock(GPU_SMMU_BASE, GCC_GFX_TCU_CBCR);
|
||||
}
|
||||
|
||||
/*
|
||||
* Keep APCS vote for SMMU clocks for rest of booting process, but make
|
||||
* sure other vote registers (such as RPM) do not keep permanent votes.
|
||||
*/
|
||||
VERBOSE("Clearing GCC_RPM_SMMU_CLOCK_BRANCH_ENA_VOTE (was: 0x%x)\n",
|
||||
mmio_read_32(GCC_RPM_SMMU_CLOCK_BRANCH_ENA_VOTE));
|
||||
mmio_write_32(GCC_RPM_SMMU_CLOCK_BRANCH_ENA_VOTE, 0);
|
||||
}
|
||||
|
||||
void msm8916_configure(void)
|
||||
{
|
||||
msm8916_gicv2_configure();
|
||||
msm8916_configure_timer();
|
||||
msm8916_configure_cpu_pm();
|
||||
msm8916_configure_apcs();
|
||||
msm8916_configure_smmu();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -8,5 +8,6 @@
|
|||
#define MSM8916_CONFIG_H
|
||||
|
||||
void msm8916_configure(void);
|
||||
void msm8916_configure_early(void);
|
||||
|
||||
#endif /* MSM8916_CONFIG_H */
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
/*
|
||||
* Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
|
||||
* Copyright (c) 2021-2022, Stephan Gerhold <stephan@gerhold.net>
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <common/debug.h>
|
||||
#include <drivers/delay_timer.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include <msm8916_mmap.h>
|
||||
#include "msm8916_pm.h"
|
||||
|
||||
#define CPU_PWR_CTL 0x4
|
||||
|
|
@ -26,12 +26,39 @@
|
|||
#define APC_PWR_GATE_CTL_GHDS_EN BIT_32(0)
|
||||
#define APC_PWR_GATE_CTL_GHDS_CNT(cnt) ((cnt) << 24)
|
||||
|
||||
#define PWR_CTL_OVERRIDE 0xc
|
||||
#define L2_PWR_CTL 0x14
|
||||
#define L2_PWR_STATUS 0x18
|
||||
#define CORE_CBCR 0x58
|
||||
|
||||
#define PWR_CTL_OVERRIDE_PRESETDBG BIT_32(22)
|
||||
|
||||
#define L2_PWR_CTL_L2_ARRAY_HS BIT_32(0)
|
||||
#define L2_PWR_CTL_SCU_ARRAY_HS BIT_32(1)
|
||||
#define L2_PWR_CTL_L2_RST_DIS BIT_32(2)
|
||||
#define L2_PWR_CTL_L2_HS_CLAMP BIT_32(8)
|
||||
#define L2_PWR_CTL_L2_HS_EN BIT_32(9)
|
||||
#define L2_PWR_CTL_L2_HS_RST BIT_32(10)
|
||||
#define L2_PWR_CTL_L2_SLEEP_STATE BIT_32(11)
|
||||
#define L2_PWR_CTL_SYS_RESET BIT_32(12)
|
||||
#define L2_PWR_CTL_L2_RET_SLP BIT_32(13)
|
||||
#define L2_PWR_CTL_SCU_ARRAY_HS_CLAMP BIT_32(14)
|
||||
#define L2_PWR_CTL_L2_ARRAY_HS_CLAMP BIT_32(15)
|
||||
#define L2_PWR_CTL_L2_HS_CNT(cnt) ((cnt) << 16)
|
||||
#define L2_PWR_CTL_PMIC_APC_ON BIT_32(28)
|
||||
|
||||
#define L2_PWR_STATUS_L2_HS_STS BIT_32(9)
|
||||
|
||||
#define CORE_CBCR_CLK_ENABLE BIT_32(0)
|
||||
#define CORE_CBCR_HW_CTL BIT_32(1)
|
||||
|
||||
/* Boot a secondary CPU core for the first time. */
|
||||
void msm8916_cpu_boot(unsigned int core)
|
||||
void msm8916_cpu_boot(uintptr_t acs)
|
||||
{
|
||||
uintptr_t acs = APCS_ALIAS_ACS(core);
|
||||
uint32_t pwr_ctl;
|
||||
|
||||
VERBOSE("PSCI: Powering on CPU @ 0x%08lx\n", acs);
|
||||
|
||||
pwr_ctl = CPU_PWR_CTL_CLAMP | CPU_PWR_CTL_CORE_MEM_CLAMP |
|
||||
CPU_PWR_CTL_CORE_RST | CPU_PWR_CTL_COREPOR_RST;
|
||||
mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
|
||||
|
|
@ -64,3 +91,60 @@ void msm8916_cpu_boot(unsigned int core)
|
|||
mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
|
||||
dsb();
|
||||
}
|
||||
|
||||
/* Power on cluster L2 cache for the first time. */
|
||||
void msm8916_l2_boot(uintptr_t base)
|
||||
{
|
||||
uint32_t pwr_ctl, cbcr, ovr;
|
||||
|
||||
/* Skip if cluster L2 is already powered on */
|
||||
if (mmio_read_32(base + L2_PWR_STATUS) & L2_PWR_STATUS_L2_HS_STS) {
|
||||
VERBOSE("PSCI: L2 cache @ 0x%08lx is already powered on\n", base);
|
||||
return;
|
||||
}
|
||||
|
||||
VERBOSE("PSCI: Powering on L2 cache @ 0x%08lx\n", base);
|
||||
|
||||
pwr_ctl = L2_PWR_CTL_L2_HS_CLAMP | L2_PWR_CTL_L2_HS_EN |
|
||||
L2_PWR_CTL_L2_HS_RST | L2_PWR_CTL_SYS_RESET |
|
||||
L2_PWR_CTL_SCU_ARRAY_HS_CLAMP | L2_PWR_CTL_L2_ARRAY_HS_CLAMP |
|
||||
L2_PWR_CTL_L2_HS_CNT(16);
|
||||
mmio_write_32(base + L2_PWR_CTL, pwr_ctl);
|
||||
|
||||
ovr = PWR_CTL_OVERRIDE_PRESETDBG;
|
||||
mmio_write_32(base + PWR_CTL_OVERRIDE, ovr);
|
||||
dsb();
|
||||
udelay(2);
|
||||
|
||||
pwr_ctl &= ~(L2_PWR_CTL_SCU_ARRAY_HS_CLAMP |
|
||||
L2_PWR_CTL_L2_ARRAY_HS_CLAMP);
|
||||
mmio_write_32(base + L2_PWR_CTL, pwr_ctl);
|
||||
|
||||
pwr_ctl |= (L2_PWR_CTL_L2_ARRAY_HS | L2_PWR_CTL_SCU_ARRAY_HS);
|
||||
mmio_write_32(base + L2_PWR_CTL, pwr_ctl);
|
||||
dsb();
|
||||
udelay(2);
|
||||
|
||||
cbcr = CORE_CBCR_CLK_ENABLE;
|
||||
mmio_write_32(base + CORE_CBCR, cbcr);
|
||||
|
||||
pwr_ctl &= ~L2_PWR_CTL_L2_HS_CLAMP;
|
||||
mmio_write_32(base + L2_PWR_CTL, pwr_ctl);
|
||||
dsb();
|
||||
udelay(2);
|
||||
|
||||
ovr &= ~PWR_CTL_OVERRIDE_PRESETDBG;
|
||||
mmio_write_32(base + PWR_CTL_OVERRIDE, ovr);
|
||||
|
||||
pwr_ctl &= ~(L2_PWR_CTL_L2_HS_RST | L2_PWR_CTL_SYS_RESET);
|
||||
mmio_write_32(base + L2_PWR_CTL, pwr_ctl);
|
||||
dsb();
|
||||
udelay(54);
|
||||
|
||||
pwr_ctl |= L2_PWR_CTL_PMIC_APC_ON;
|
||||
mmio_write_32(base + L2_PWR_CTL, pwr_ctl);
|
||||
|
||||
cbcr |= CORE_CBCR_HW_CTL;
|
||||
mmio_write_32(base + CORE_CBCR, cbcr);
|
||||
dsb();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,9 +4,12 @@
|
|||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#include <arch.h>
|
||||
#include <arch_helpers.h>
|
||||
#include <common/debug.h>
|
||||
#include <drivers/arm/cci.h>
|
||||
#include <drivers/arm/gicv2.h>
|
||||
#include <drivers/delay_timer.h>
|
||||
#include <lib/mmio.h>
|
||||
|
|
@ -16,18 +19,51 @@
|
|||
#include <msm8916_mmap.h>
|
||||
#include "msm8916_pm.h"
|
||||
|
||||
/*
|
||||
* On platforms with two clusters the index of the APCS memory region is swapped
|
||||
* compared to the MPIDR cluster affinity level: APCS cluster 0 manages CPUs
|
||||
* with cluster affinity level 1, while APCS cluster 1 manages CPUs with level 0.
|
||||
*
|
||||
* On platforms with a single cluster there is only one APCS memory region.
|
||||
*/
|
||||
#if PLATFORM_CLUSTER_COUNT == 2
|
||||
#define MPIDR_APCS_CLUSTER(mpidr) !MPIDR_AFFLVL1_VAL(mpidr)
|
||||
#else
|
||||
#define MPIDR_APCS_CLUSTER(mpidr) 0
|
||||
#endif
|
||||
|
||||
#define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1])
|
||||
|
||||
static int msm8916_pwr_domain_on(u_register_t mpidr)
|
||||
{
|
||||
unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
|
||||
|
||||
VERBOSE("PSCI: Booting CPU %d\n", core);
|
||||
msm8916_cpu_boot(core);
|
||||
/* Should be never called on single-core platforms */
|
||||
if (PLATFORM_CORE_COUNT == 1) {
|
||||
assert(false);
|
||||
return PSCI_E_ALREADY_ON;
|
||||
}
|
||||
|
||||
/* Power on L2 cache and secondary CPU core for the first time */
|
||||
if (PLATFORM_CLUSTER_COUNT > 1) {
|
||||
msm8916_l2_boot(APCS_GLB(MPIDR_APCS_CLUSTER(mpidr)));
|
||||
}
|
||||
msm8916_cpu_boot(APCS_ALIAS_ACS(MPIDR_APCS_CLUSTER(mpidr),
|
||||
MPIDR_AFFLVL0_VAL(mpidr)));
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
static void msm8916_pwr_domain_on_finish(const psci_power_state_t *target_state)
|
||||
{
|
||||
/* Should be never called on single-core platforms */
|
||||
if (PLATFORM_CORE_COUNT == 1) {
|
||||
assert(false);
|
||||
return;
|
||||
}
|
||||
|
||||
if (PLATFORM_CLUSTER_COUNT > 1 &&
|
||||
CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
|
||||
cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
|
||||
}
|
||||
|
||||
gicv2_pcpu_distif_init();
|
||||
gicv2_cpuif_enable();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
|
||||
* Copyright (c) 2021-2022, Stephan Gerhold <stephan@gerhold.net>
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -7,6 +7,7 @@
|
|||
#ifndef MSM8916_PM_H
|
||||
#define MSM8916_PM_H
|
||||
|
||||
void msm8916_cpu_boot(unsigned int core);
|
||||
void msm8916_cpu_boot(uintptr_t acs);
|
||||
void msm8916_l2_boot(uintptr_t base);
|
||||
|
||||
#endif /* MSM8916_PM_H */
|
||||
|
|
|
|||
|
|
@ -47,7 +47,14 @@ struct uartdm_gpios {
|
|||
};
|
||||
|
||||
static const struct uartdm_gpios uartdm_gpio_map[] = {
|
||||
#if defined(PLAT_msm8909)
|
||||
{4, 5, 0x2}, {20, 21, 0x3},
|
||||
#elif defined(PLAT_msm8916) || defined(PLAT_msm8939)
|
||||
{0, 1, 0x2}, {4, 5, 0x2},
|
||||
#elif defined(PLAT_mdm9607)
|
||||
{12, 13, 0x2}, {4, 5, 0x2}, {0, 1, 0x1},
|
||||
{16, 17, 0x2}, {8, 9, 0x2}, {20, 21, 0x2},
|
||||
#endif
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -69,13 +76,13 @@ static void msm8916_enable_blsp_uart(void)
|
|||
|
||||
/* Enable AHB clock */
|
||||
mmio_setbits_32(GCC_APCS_CLOCK_BRANCH_ENA_VOTE, BLSP1_AHB_CLK_ENA);
|
||||
while (mmio_read_32(GCC_BLSP1_AHB_CBCR) & CLK_OFF)
|
||||
;
|
||||
while (mmio_read_32(GCC_BLSP1_AHB_CBCR) & CLK_OFF) {
|
||||
}
|
||||
|
||||
/* Enable BLSP UART clock */
|
||||
mmio_setbits_32(GCC_BLSP1_UART_APPS_CBCR(QTI_UART_NUM), CLK_ENABLE);
|
||||
while (mmio_read_32(GCC_BLSP1_UART_APPS_CBCR(QTI_UART_NUM)) & CLK_OFF)
|
||||
;
|
||||
while (mmio_read_32(GCC_BLSP1_UART_APPS_CBCR(QTI_UART_NUM)) & CLK_OFF) {
|
||||
}
|
||||
}
|
||||
|
||||
void msm8916_early_platform_setup(void)
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2022, Stephan Gerhold <stephan@gerhold.net>
|
||||
* Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
|
|
@ -9,24 +10,27 @@
|
|||
|
||||
#include <platform_def.h>
|
||||
|
||||
static const unsigned char plat_power_domain_tree_desc[PLAT_MAX_PWR_LVL + 1] = {
|
||||
static const unsigned char plat_power_domain_tree_desc[] = {
|
||||
PLATFORM_SYSTEM_COUNT,
|
||||
PLATFORM_CLUSTER_COUNT,
|
||||
PLATFORM_MAX_CPUS_PER_CLUSTER,
|
||||
PLATFORM_CPUS_PER_CLUSTER,
|
||||
#if PLATFORM_CLUSTER_COUNT > 1
|
||||
PLATFORM_CPUS_PER_CLUSTER,
|
||||
#endif
|
||||
};
|
||||
|
||||
int plat_core_pos_by_mpidr(u_register_t mpidr)
|
||||
{
|
||||
unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr);
|
||||
unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
|
||||
|
||||
if (MPIDR_AFFLVL3_VAL(mpidr) > 0 ||
|
||||
MPIDR_AFFLVL2_VAL(mpidr) > 0 ||
|
||||
MPIDR_AFFLVL1_VAL(mpidr) > 0 ||
|
||||
core >= PLATFORM_MAX_CPUS_PER_CLUSTER) {
|
||||
cluster >= PLATFORM_CLUSTER_COUNT ||
|
||||
core >= PLATFORM_CPUS_PER_CLUSTER) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
return core;
|
||||
return core | (cluster << PLATFORM_CPU_PER_CLUSTER_SHIFT);
|
||||
}
|
||||
|
||||
const unsigned char *plat_get_power_domain_tree_desc(void)
|
||||
|
|
|
|||
|
|
@ -17,7 +17,9 @@ PLAT_BL_COMMON_SOURCES := ${GICV2_SOURCES} \
|
|||
plat/qti/msm8916/${ARCH}/msm8916_helpers.S \
|
||||
plat/qti/msm8916/${ARCH}/uartdm_console.S
|
||||
|
||||
MSM8916_PM_SOURCES := lib/cpus/${ARCH}/cortex_a53.S \
|
||||
MSM8916_CPU := $(if ${ARM_CORTEX_A7},cortex_a7,cortex_a53)
|
||||
MSM8916_PM_SOURCES := drivers/arm/cci/cci.c \
|
||||
lib/cpus/${ARCH}/${MSM8916_CPU}.S \
|
||||
plat/common/plat_psci_common.c \
|
||||
plat/qti/msm8916/msm8916_config.c \
|
||||
plat/qti/msm8916/msm8916_cpu_boot.c \
|
||||
|
|
@ -48,11 +50,14 @@ WARMBOOT_ENABLE_DCACHE_EARLY := 1
|
|||
ENABLE_SPE_FOR_NS := 0
|
||||
ENABLE_SVE_FOR_NS := 0
|
||||
|
||||
# Disable workarounds unnecessary for Cortex-A53
|
||||
# Disable workarounds unnecessary for Cortex-A7/A53
|
||||
WORKAROUND_CVE_2017_5715 := 0
|
||||
WORKAROUND_CVE_2022_23960 := 0
|
||||
|
||||
# MSM8916 uses ARM Cortex-A53 r0p0 so likely all the errata apply
|
||||
ifeq (${MSM8916_CPU},cortex_a53)
|
||||
# The Cortex-A53 revision varies depending on the SoC revision.
|
||||
# msm8916 uses r0p0, msm8939 uses r0p1 or r0p4. Enable all errata
|
||||
# and rely on the runtime detection to apply them only if needed.
|
||||
ERRATA_A53_819472 := 1
|
||||
ERRATA_A53_824069 := 1
|
||||
ERRATA_A53_826319 := 1
|
||||
|
|
@ -60,8 +65,9 @@ ERRATA_A53_827319 := 1
|
|||
ERRATA_A53_835769 := 1
|
||||
ERRATA_A53_836870 := 1
|
||||
ERRATA_A53_843419 := 1
|
||||
ERRATA_A53_855873 := 0 # Workaround works only for >= r0p3
|
||||
ERRATA_A53_855873 := 1
|
||||
ERRATA_A53_1530924 := 1
|
||||
endif
|
||||
|
||||
# Build config flags
|
||||
# ------------------
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
|
|||
u_register_t arg2, u_register_t arg3)
|
||||
{
|
||||
msm8916_early_platform_setup();
|
||||
msm8916_configure_early();
|
||||
}
|
||||
|
||||
void sp_min_plat_arch_setup(void)
|
||||
|
|
|
|||
11
plat/qti/msm8939/platform.mk
Normal file
11
plat/qti/msm8939/platform.mk
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
#
|
||||
# Copyright (c) 2022-2023, Stephan Gerhold <stephan@gerhold.net>
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
# Cache cannot be enabled early on MSM8939 because the CCI-400 must be
|
||||
# enabled before the CPUs in both clusters become cache-coherent.
|
||||
override WARMBOOT_ENABLE_DCACHE_EARLY := 0
|
||||
|
||||
include plat/qti/msm8916/platform.mk
|
||||
7
plat/qti/msm8939/sp_min/sp_min-msm8939.mk
Normal file
7
plat/qti/msm8939/sp_min/sp_min-msm8939.mk
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
#
|
||||
# Copyright (c) 2022-2023, Stephan Gerhold <stephan@gerhold.net>
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
include plat/qti/msm8916/sp_min/sp_min-msm8916.mk
|
||||
7
plat/qti/msm8939/tsp/tsp-msm8939.mk
Normal file
7
plat/qti/msm8939/tsp/tsp-msm8939.mk
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
#
|
||||
# Copyright (c) 2023, Stephan Gerhold <stephan@gerhold.net>
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
include plat/qti/msm8916/tsp/tsp-msm8916.mk
|
||||
Loading…
Add table
Reference in a new issue