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fix(intel): revert back to use L4 clock

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Using mpu_peri as the clock source will caused the system
timer vary. System timer shall get from a static clock
source.

L4 and L3 clock are both the same at the moment.
There shall be a hardware update to differentiate the clock pll.
To keep this as dormant function for now.

Change-Id: I4d253e2f24a74cbec59bfcbf0e8547abbe3643a8
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
This commit is contained in:
Sieu Mun Tang 2023-12-22 11:12:17 +08:00
parent 11f99e8df5
commit d0e400b3c6
3 changed files with 12 additions and 2 deletions
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11
plat/intel/soc/agilex/soc/agilex_clock_manager.c
View file

@ -398,12 +398,21 @@ uint32_t get_mpu_clk(void)
return mpu_clk; return mpu_clk;
} }
uint32_t get_l4_clk(void)
{
uint32_t l4_clk;
l4_clk = get_clk_freq(CLKMGR_MAINPLL_NOCCLK, CLKMGR_MAINPLL_PLLC1,
CLKMGR_PERPLL_PLLC1);
return l4_clk;
}
/* Get cpu freq clock */ /* Get cpu freq clock */
uint32_t get_cpu_clk(void) uint32_t get_cpu_clk(void)
{ {
uint32_t cpu_clk; uint32_t cpu_clk;
cpu_clk = get_mpu_clk()/PLAT_HZ_CONVERT_TO_MHZ; cpu_clk = get_l4_clk()/PLAT_HZ_CONVERT_TO_MHZ;
return cpu_clk; return cpu_clk;
} }

2
plat/intel/soc/n5x/soc/n5x_clock_manager.c
View file

@ -150,7 +150,7 @@ uint32_t get_cpu_clk(void)
{ {
uint32_t cpu_clk = 0; uint32_t cpu_clk = 0;
cpu_clk = get_mpu_clk()/PLAT_HZ_CONVERT_TO_MHZ; cpu_clk = get_l4_clk()/PLAT_HZ_CONVERT_TO_MHZ;
return cpu_clk; return cpu_clk;
} }

1
plat/intel/soc/stratix10/include/s10_clock_manager.h
View file

@ -95,6 +95,7 @@ uint32_t get_wdt_clk(void);
uint32_t get_uart_clk(void); uint32_t get_uart_clk(void);
uint32_t get_mmc_clk(void); uint32_t get_mmc_clk(void);
uint32_t get_l3_clk(uint32_t ref_clk); uint32_t get_l3_clk(uint32_t ref_clk);
uint32_t get_cpu_clk(void);
uint32_t get_ref_clk(uint32_t pllglob); uint32_t get_ref_clk(uint32_t pllglob);
uint32_t get_mpu_periph_clk(void); uint32_t get_mpu_periph_clk(void);