From 7f69a40697c3cc64e3fc553f6b50c72b97238dc9 Mon Sep 17 00:00:00 2001 From: Bipin Ravi Date: Tue, 27 Feb 2024 15:13:17 -0600 Subject: [PATCH] fix(cpus): workaround for Cortex-X3 erratum 2372204 Cortex-X3 erratum 2372204 is a Cat B erratum that applies to revisions r0p0 and r1p0. It is fixed in r1p1. The workaround is to set bit[40] of CPUACTLR2_EL1 to disable folding of demand requests into older prefetches with L2 miss requests outstanding. SDEN can be found here: https://developer.arm.com/documentation/SDEN2055130/latest Change-Id: Iad28f8625c84186fbd8049406d139d4f15c6e069 Signed-off-by: Bipin Ravi --- docs/design/cpu-specific-build-macros.rst | 4 ++++ lib/cpus/aarch64/cortex_x3.S | 7 +++++++ lib/cpus/cpu-ops.mk | 4 ++++ services/std_svc/errata_abi/errata_abi_main.c | 13 +++++++------ 4 files changed, 22 insertions(+), 6 deletions(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index abd9f8771..ccb45a8fd 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -787,6 +787,10 @@ For Cortex-X3, the following errata build flags are defined : Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it is fixed in r1p1. +- ``ERRATA_X3_2372204``: This applies errata 2372204 workaround to + Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 + of the CPU, it is fixed in r1p1. + - ``ERRATA_X3_2615812``: This applies errata 2615812 workaround to Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the CPU, it is still open. diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S index e5a05fca4..49e9ad1d3 100644 --- a/lib/cpus/aarch64/cortex_x3.S +++ b/lib/cpus/aarch64/cortex_x3.S @@ -51,6 +51,13 @@ workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB check_erratum_ls cortex_x3, ERRATUM(2313909), CPU_REV(1, 0) +workaround_reset_start cortex_x3, ERRATUM(2372204), ERRATA_X3_2372204 + /* Set bit 40 in CPUACTLR2_EL1 */ + sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(40) +workaround_reset_end cortex_x3, ERRATUM(2372204) + +check_erratum_ls cortex_x3, ERRATUM(2372204), CPU_REV(1, 0) + workaround_reset_start cortex_x3, ERRATUM(2615812), ERRATA_X3_2615812 /* Disable retention control for WFI and WFE. */ mrs x0, CORTEX_X3_CPUPWRCTLR_EL1 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index dcbeba191..0b4ed6b37 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -790,6 +790,10 @@ CPU_FLAG_LIST += ERRATA_X3_2302506 # to revisions r0p0 and r1p0 of the Cortex-X3 cpu, it is fixed in r1p1. CPU_FLAG_LIST += ERRATA_X3_2313909 +# Flag to apply erratum 2372204 workaround during reset. This erratum applies +# to revisions r0p0 and r1p0 of the Cortex-X3 cpu, it is fixed in r1p1. +CPU_FLAG_LIST += ERRATA_X3_2372204 + # Flag to apply erratum 2615812 workaround on powerdown. This erratum applies # to revisions r0p0, r1p0, r1p1 of the Cortex-X3 cpu, it is still open. CPU_FLAG_LIST += ERRATA_X3_2615812 diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c index 811adcb0a..fe1068dc8 100644 --- a/services/std_svc/errata_abi/errata_abi_main.c +++ b/services/std_svc/errata_abi/errata_abi_main.c @@ -451,12 +451,13 @@ struct em_cpu_list cpu_list[] = { [1] = {2266875, 0x00, 0x10, ERRATA_X3_2266875}, [2] = {2302506, 0x00, 0x11, ERRATA_X3_2302506}, [3] = {2313909, 0x00, 0x10, ERRATA_X3_2313909}, - [4] = {2615812, 0x00, 0x11, ERRATA_X3_2615812}, - [5] = {2641945, 0x00, 0x10, ERRATA_X3_2641945}, - [6] = {2742421, 0x00, 0x11, ERRATA_X3_2742421}, - [7] = {2743088, 0x00, 0x11, ERRATA_X3_2743088}, - [8] = {2779509, 0x00, 0x11, ERRATA_X3_2779509}, - [9 ... ERRATA_LIST_END] = UNDEF_ERRATA, + [4] = {2372204, 0x00, 0x10, ERRATA_X3_2372204}, + [5] = {2615812, 0x00, 0x11, ERRATA_X3_2615812}, + [6] = {2641945, 0x00, 0x10, ERRATA_X3_2641945}, + [7] = {2742421, 0x00, 0x11, ERRATA_X3_2742421}, + [8] = {2743088, 0x00, 0x11, ERRATA_X3_2743088}, + [9] = {2779509, 0x00, 0x11, ERRATA_X3_2779509}, + [10 ... ERRATA_LIST_END] = UNDEF_ERRATA, } }, #endif /* CORTEX_X3_H_INC */