Merge pull request #1650 from chandnich/sgiclark-ares-support

Sgiclark ares support

include/plat/arm/css/common/css_def.h

@@ -26,6 +26,11 @@
 #define SSC_REG_BASE			0x2a420000
 #define SSC_GPRETN			(SSC_REG_BASE + 0x030)
 
+/* System ID Registers Unit */
+#define SID_REG_BASE			0x2a4a0000
+#define SID_SYSTEM_ID_OFFSET		0x40
+#define SID_SYSTEM_CFG_OFFSET		0x70
+
 /* The slave_bootsecure controls access to GPU, DMC and CS. */
 #define CSS_NIC400_SLAVE_BOOTSECURE	8
 
@@ -123,6 +128,8 @@
 #define SSC_VERSION_DESIGNER_ID_MASK		0xff
 #define SSC_VERSION_PART_NUM_MASK		0xfff
 
+#define SID_SYSTEM_ID_PART_NUM_MASK		0xfff
+
 /* SSC debug configuration registers */
 #define SSC_DBGCFG_SET		0x14
 #define SSC_DBGCFG_CLR		0x18

plat/arm/board/sgiclarka/fdts/sgiclarka.dts

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+/ {
+	/* compatible string */
+	compatible = "arm,sgi-clark";
+
+	/*
+	 * Place holder for system-id node with default values. The
+	 * value of platform-id and config-id will be set to the
+	 * correct values during the BL2 stage of boot.
+	 */
+	system-id {
+		platform-id = <0x0>;
+		config-id = <0x0>;
+	};
+};

plat/arm/board/sgiclarka/fdts/sgiclarka_tb_fw_config.dts

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+/ {
+	/* Platform Config */
+	compatible = "arm,tb_fw";
+	hw_config_addr = <0x0 0xFEF00000>;
+	hw_config_max_size = <0x0100000>;
+	/*
+	 * The following two entries are placeholders for Mbed TLS
+	 * heap information. The default values don't matter since
+	 * they will be overwritten by BL1.
+	 * In case of having shared Mbed TLS heap between BL1 and BL2,
+	 * BL1 will populate these two properties with the respective
+	 * info about the shared heap. This info will be available for
+	 * BL2 in order to locate and re-use the heap.
+	 */
+	mbedtls_heap_addr = <0x0 0x0>;
+	mbedtls_heap_size = <0x0>;
+};

plat/arm/board/sgiclarka/include/platform_def.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <sgi_base_platform_def.h>
+
+#define PLAT_ARM_CLUSTER_COUNT		2
+#define CSS_SGI_MAX_CPUS_PER_CLUSTER	4
+#define CSS_SGI_MAX_PE_PER_CPU		1
+
+#define PLAT_CSS_MHU_BASE		0x45400000
+
+#endif /* PLATFORM_DEF_H */

plat/arm/board/sgiclarka/platform.mk

@@ -0,0 +1,38 @@
+#
+# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include plat/arm/css/sgi/sgi-common.mk
+
+SGICLARKA_BASE		=	plat/arm/board/sgiclarka
+
+PLAT_INCLUDES		+=	-I${SGICLARKA_BASE}/include/
+
+SGI_CPU_SOURCES		:=	lib/cpus/aarch64/cortex_ares.S
+
+BL1_SOURCES		+=	${SGI_CPU_SOURCES}
+
+BL2_SOURCES		+=	lib/utils/mem_region.c			\
+				plat/arm/common/arm_nor_psci_mem_protect.c
+
+BL31_SOURCES		+=	${SGI_CPU_SOURCES}			\
+				drivers/cfi/v2m/v2m_flash.c		\
+				lib/utils/mem_region.c			\
+				plat/arm/common/arm_nor_psci_mem_protect.c
+
+# Add the FDT_SOURCES and options for Dynamic Config
+FDT_SOURCES		+=	${SGICLARKA_BASE}/fdts/${PLAT}_tb_fw_config.dts
+TB_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
+
+# Add the TB_FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config))
+
+FDT_SOURCES		+=	${SGICLARKA_BASE}/fdts/${PLAT}.dts
+HW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}.dtb
+
+# Add the HW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config))
+
+override CTX_INCLUDE_AARCH32_REGS	:= 0

plat/arm/css/sgi/aarch64/sgi_helper.S

@@ -8,6 +8,7 @@
 #include <asm_macros.S>
 #include <platform_def.h>
 #include <cortex_a75.h>
+#include <cortex_ares.h>
 #include <cpu_macros.S>
 
 	.globl	plat_arm_calc_core_pos
@@ -58,6 +59,7 @@ endfunc plat_arm_calc_core_pos
 	 */
 func plat_reset_handler
 	jump_if_cpu_midr CORTEX_A75_MIDR, A75
+	jump_if_cpu_midr CORTEX_ARES_MIDR, ARES
 	ret
 
 	/* -----------------------------------------------------
@@ -70,4 +72,11 @@ A75:
 	msr	CORTEX_A75_CPUPWRCTLR_EL1, x0
 	isb
 	ret
+
+ARES:
+	mrs	x0, CORTEX_ARES_CPUPWRCTLR_EL1
+	bic	x0, x0, #CORTEX_ARES_CORE_PWRDN_EN_MASK
+	msr	CORTEX_ARES_CPUPWRCTLR_EL1, x0
+	isb
+	ret
 endfunc plat_reset_handler

plat/arm/css/sgi/include/sgi_variant.h

@@ -4,10 +4,21 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __SGI_VARIANT_H__
-#define __SGI_VARIANT_H__
+#ifndef SGI_VARIANT_H
+#define SGI_VARIANT_H
 
 /* SSC_VERSION values for SGI575 */
 #define SGI575_SSC_VER_PART_NUM		0x0783
 
-#endif /* __SGI_VARIANT_H__ */
+/* SID Version values for SGI-Clark */
+#define SGI_CLARK_SID_VER_PART_NUM		0x0786
+
+/* Structure containing SGI platform variant information */
+typedef struct sgi_platform_info {
+	unsigned int platform_id;	/* Part Number of the platform */
+	unsigned int config_id;		/* Config Id of the platform */
+} sgi_platform_info_t;
+
+extern sgi_platform_info_t sgi_plat_info;
+
+#endif /* SGI_VARIANT_H */

plat/arm/css/sgi/sgi_bl31_setup.c

@@ -4,13 +4,18 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <assert.h>
 #include <bl_common.h>
 #include <debug.h>
+#include <libfdt.h>
 #include <plat_arm.h>
 #include <sgi_ras.h>
+#include <sgi_variant.h>
 #include "../../css/drivers/scmi/scmi.h"
 #include "../../css/drivers/mhu/css_mhu_doorbell.h"
 
+sgi_platform_info_t sgi_plat_info;
+
 static scmi_channel_plat_info_t sgi575_scmi_plat_info = {
 		.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
 		.db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF,
@@ -19,14 +24,72 @@ static scmi_channel_plat_info_t sgi575_scmi_plat_info = {
 		.ring_doorbell = &mhu_ring_doorbell,
 };
 
+static scmi_channel_plat_info_t sgi_clark_scmi_plat_info = {
+		.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
+		.db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0),
+		.db_preserve_mask = 0xfffffffe,
+		.db_modify_mask = 0x1,
+		.ring_doorbell = &mhuv2_ring_doorbell,
+};
+
 scmi_channel_plat_info_t *plat_css_get_scmi_info()
 {
-	return &sgi575_scmi_plat_info;
+	if (sgi_plat_info.platform_id == SGI_CLARK_SID_VER_PART_NUM)
+		return &sgi_clark_scmi_plat_info;
+	else if (sgi_plat_info.platform_id == SGI575_SSC_VER_PART_NUM)
+		return &sgi575_scmi_plat_info;
+	else
+		panic();
+};
+
+/*******************************************************************************
+ * This function sets the sgi_platform_id and sgi_config_id
+ ******************************************************************************/
+int sgi_identify_platform(unsigned long hw_config)
+{
+	void *fdt;
+	int nodeoffset;
+	const unsigned int *property;
+
+	fdt = (void *)hw_config;
+
+	/* Check the validity of the fdt */
+	assert(fdt_check_header(fdt) == 0);
+
+	nodeoffset = fdt_subnode_offset(fdt, 0, "system-id");
+	if (nodeoffset < 0) {
+		ERROR("Failed to get system-id node offset\n");
+		return -1;
+	}
+
+	property = fdt_getprop(fdt, nodeoffset, "platform-id", NULL);
+	if (property == NULL) {
+		ERROR("Failed to get platform-id property\n");
+		return -1;
+	}
+
+	sgi_plat_info.platform_id = fdt32_to_cpu(*property);
+
+	property = fdt_getprop(fdt, nodeoffset, "config-id", NULL);
+	if (property == NULL) {
+		ERROR("Failed to get config-id property\n");
+		return -1;
+	}
+
+	sgi_plat_info.config_id = fdt32_to_cpu(*property);
+
+	return 0;
 }
 
 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 				u_register_t arg2, u_register_t arg3)
 {
+	int ret;
+
+	ret = sgi_identify_platform(arg2);
+	if (ret == -1)
+		panic();
+
 	arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
 }
 

plat/arm/css/sgi/sgi_image_load.c

@@ -50,6 +50,10 @@ static int plat_sgi_append_config_node(void)
 		platid = mmio_read_32(SSC_VERSION) & SSC_VERSION_PART_NUM_MASK;
 		platcfg = (mmio_read_32(SSC_VERSION) >> SSC_VERSION_CONFIG_SHIFT)
 				& SSC_VERSION_CONFIG_MASK;
+	} else if (strcmp(platform_name, "arm,sgi-clark") == 0) {
+		platid = mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
+				& SID_SYSTEM_ID_PART_NUM_MASK;
+		platcfg = mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
 	} else {
 		WARN("Invalid platform\n");
 		return -1;