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Merge "refactor(xilinx): rename gic macros to make common" into integration

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Mark Dykes 2023-03-28 17:10:29 +02:00 • committed by TrustedFirmware Code Review
commit cfe6a82ee8
7 changed files with 19 additions and 15 deletions
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5
plat/xilinx/versal/include/plat_macros.S
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -102,8 +103,8 @@ exit_print_gic_regs:
* ---------------------------------------------
*/
.macro plat_crash_print_regs
mov_imm x17, PLAT_VERSAL_GICD_BASE
mov_imm x16, PLAT_VERSAL_GICR_BASE
mov_imm x17, PLAT_GICD_BASE_VALUE
mov_imm x16, PLAT_GICR_BASE_VALUE
versal_print_gic_regs
.endm

5
plat/xilinx/versal/include/platform_def.h
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -81,8 +82,8 @@
#define CACHE_WRITEBACK_SHIFT 6
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
#define PLAT_VERSAL_GICD_BASE U(0xF9000000)
#define PLAT_VERSAL_GICR_BASE U(0xF9080000)
#define PLAT_GICD_BASE_VALUE U(0xF9000000)
#define PLAT_GICR_BASE_VALUE U(0xF9080000)
/*
* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3

3
plat/xilinx/versal/pm_service/pm_client.c
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
* Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -121,7 +122,7 @@ static void pm_client_set_wakeup_sources(uint32_t node_id)
uint32_t reg_num;
uint32_t device_id;
uint8_t pm_wakeup_nodes_set[XPM_NODEIDX_DEV_MAX] = { 0U };
uintptr_t isenabler1 = PLAT_VERSAL_GICD_BASE + GICD_ISENABLER + 4;
uintptr_t isenabler1 = PLAT_GICD_BASE_VALUE + GICD_ISENABLER + 4;
for (reg_num = 0U; reg_num < NUM_GICD_ISENABLER; reg_num++) {
uint32_t base_irq = reg_num << ISENABLER_SHIFT;

5
plat/xilinx/versal/versal_gicv3.c
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -60,8 +61,8 @@ static uint32_t versal_gicv3_mpidr_hash(u_register_t mpidr)
}
static const gicv3_driver_data_t versal_gic_data __unused = {
.gicd_base = PLAT_VERSAL_GICD_BASE,
.gicr_base = PLAT_VERSAL_GICR_BASE,
.gicd_base = PLAT_GICD_BASE_VALUE,
.gicr_base = PLAT_GICR_BASE_VALUE,
.interrupt_props = versal_interrupt_props,
.interrupt_props_num = ARRAY_SIZE(versal_interrupt_props),
.rdistif_num = PLATFORM_CORE_COUNT,

6
plat/xilinx/versal_net/include/plat_macros.S
View file

@ -1,7 +1,7 @@
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
* Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
* Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -109,8 +109,8 @@ exit_print_gic_regs:
* Uncomment it when versions are stable
*/
/*
mov_imm x17, PLAT_VERSAL_NET_GICD_BASE
mov_imm x16, PLAT_VERSAL_NET_GICR_BASE
mov_imm x17, PLAT_GICD_BASE_VALUE
mov_imm x16, PLAT_GICR_BASE_VALUE
versal_net_print_gic_regs
*/
.endm

6
plat/xilinx/versal_net/include/platform_def.h
View file

@ -1,7 +1,7 @@
/*
* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
* Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
* Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -95,8 +95,8 @@
#define CACHE_WRITEBACK_SHIFT U(6)
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
#define PLAT_VERSAL_NET_GICD_BASE U(0xE2000000)
#define PLAT_VERSAL_NET_GICR_BASE U(0xE2060000)
#define PLAT_GICD_BASE_VALUE U(0xE2000000)
#define PLAT_GICR_BASE_VALUE U(0xE2060000)
/*
* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3

4
plat/xilinx/versal_net/versal_net_gicv3.c
View file

@ -63,8 +63,8 @@ static uint32_t versal_net_gicv3_mpidr_hash(u_register_t mpidr)
}
static const gicv3_driver_data_t versal_net_gic_data __unused = {
.gicd_base = PLAT_VERSAL_NET_GICD_BASE,
.gicr_base = PLAT_VERSAL_NET_GICR_BASE,
.gicd_base = PLAT_GICD_BASE_VALUE,
.gicr_base = PLAT_GICR_BASE_VALUE,
.interrupt_props = versal_net_interrupt_props,
.interrupt_props_num = ARRAY_SIZE(versal_net_interrupt_props),
.rdistif_num = PLATFORM_CORE_COUNT,