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chore: rename Makalu ELP to Cortex-X3

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The Cortex-X3 cpu port was developed before its public release when it
was known as Makalu ELP. Now that it's released we can use the official
product name.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Iebb90cf2f77330ed848a3d61c5f6928942189c5a
This commit is contained in:
Boyan Karatotev 2022-10-25 11:29:04 +01:00
parent 36d18c542e
commit cf58b2d41c
4 changed files with 41 additions and 41 deletions
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2
docs/plat/arm/tc/index.rst
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@ -18,7 +18,7 @@ Currently, the main difference between TC0 (TARGET_PLATFORM=0), TC1
is the CPUs supported as below: is the CPUs supported as below:
- TC0 has support for Cortex A510, Cortex A710 and Cortex X2. - TC0 has support for Cortex A510, Cortex A710 and Cortex X2.
- TC1 has support for Cortex A510, Cortex Makalu and Cortex Makalu ELP. - TC1 has support for Cortex A510, Cortex Makalu and Cortex X3.
- TC2 has support for Hayes and Hunter Arm CPUs. - TC2 has support for Hayes and Hunter Arm CPUs.

4
docs/security_advisories/security-advisory-tfv-9.rst
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@ -71,12 +71,12 @@ revisions of Cortex-A73 and Cortex-A75 that implements FEAT_CSV2).
+----------------------+ +----------------------+
| Cortex-X2 | | Cortex-X2 |
+----------------------+ +----------------------+
| Cortex-X3 |
+----------------------+
| Cortex-A710 | | Cortex-A710 |
+----------------------+ +----------------------+
| Cortex-Makalu | | Cortex-Makalu |
+----------------------+ +----------------------+
| Cortex-Makalu-ELP |
+----------------------+
| Cortex-Hunter | | Cortex-Hunter |
+----------------------+ +----------------------+
| Neoverse-N1 | | Neoverse-N1 |

18
include/lib/cpus/aarch64/cortex_makalu_elp_arm.h → include/lib/cpus/aarch64/cortex_x3.h
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@ -4,23 +4,23 @@
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#ifndef CORTEX_MAKALU_ELP_ARM_H #ifndef CORTEX_X3_H
#define CORTEX_MAKALU_ELP_ARM_H #define CORTEX_X3_H
#define CORTEX_MAKALU_ELP_ARM_MIDR U(0x410FD4E0) #define CORTEX_X3_MIDR U(0x410FD4E0)
/* Cortex Makalu ELP loop count for CVE-2022-23960 mitigation */ /* Cortex-X3 loop count for CVE-2022-23960 mitigation */
#define CORTEX_MAKALU_ELP_ARM_BHB_LOOP_COUNT U(132) #define CORTEX_X3_BHB_LOOP_COUNT U(132)
/******************************************************************************* /*******************************************************************************
* CPU Extended Control register specific definitions * CPU Extended Control register specific definitions
******************************************************************************/ ******************************************************************************/
#define CORTEX_MAKALU_ELP_ARM_CPUECTLR_EL1 S3_0_C15_C1_4 #define CORTEX_X3_CPUECTLR_EL1 S3_0_C15_C1_4
/******************************************************************************* /*******************************************************************************
* CPU Power Control register specific definitions * CPU Power Control register specific definitions
******************************************************************************/ ******************************************************************************/
#define CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_X3_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) #define CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
#endif /* CORTEX_MAKALU_ELP_ARM_H */ #endif /* CORTEX_X3_H */

54
lib/cpus/aarch64/cortex_x3.S
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@ -7,40 +7,40 @@
#include <arch.h> #include <arch.h>
#include <asm_macros.S> #include <asm_macros.S>
#include <common/bl_common.h> #include <common/bl_common.h>
#include <cortex_makalu_elp_arm.h> #include <cortex_x3.h>
#include <cpu_macros.S> #include <cpu_macros.S>
#include <plat_macros.S> #include <plat_macros.S>
#include "wa_cve_2022_23960_bhb_vector.S" #include "wa_cve_2022_23960_bhb_vector.S"
/* Hardware handled coherency */ /* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0 #if HW_ASSISTED_COHERENCY == 0
#error "Cortex Makalu ELP must be compiled with HW_ASSISTED_COHERENCY enabled" #error "Cortex-X3 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif #endif
/* 64-bit only core */ /* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1 #if CTX_INCLUDE_AARCH32_REGS == 1
#error "Cortex Makalu ELP supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif #endif
#if WORKAROUND_CVE_2022_23960 #if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table CORTEX_MAKALU_ELP_ARM_BHB_LOOP_COUNT, cortex_makalu_elp_arm wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3
#endif /* WORKAROUND_CVE_2022_23960 */ #endif /* WORKAROUND_CVE_2022_23960 */
/* ---------------------------------------------------- /* ----------------------------------------------------
* HW will do the cache maintenance while powering down * HW will do the cache maintenance while powering down
* ---------------------------------------------------- * ----------------------------------------------------
*/ */
func cortex_makalu_elp_arm_core_pwr_dwn func cortex_x3_core_pwr_dwn
/* --------------------------------------------------- /* ---------------------------------------------------
* Enable CPU power down bit in power control register * Enable CPU power down bit in power control register
* --------------------------------------------------- * ---------------------------------------------------
*/ */
mrs x0, CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1 mrs x0, CORTEX_X3_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT orr x0, x0, #CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1, x0 msr CORTEX_X3_CPUPWRCTLR_EL1, x0
isb isb
ret ret
endfunc cortex_makalu_elp_arm_core_pwr_dwn endfunc cortex_x3_core_pwr_dwn
func check_errata_cve_2022_23960 func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960 #if WORKAROUND_CVE_2022_23960
@ -51,28 +51,28 @@ func check_errata_cve_2022_23960
ret ret
endfunc check_errata_cve_2022_23960 endfunc check_errata_cve_2022_23960
func cortex_makalu_elp_arm_reset_func func cortex_x3_reset_func
/* Disable speculative loads */ /* Disable speculative loads */
msr SSBS, xzr msr SSBS, xzr
#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 #if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
/* /*
* The Cortex Makalu ELP generic vectors are overridden to apply * The Cortex-X3 generic vectors are overridden to apply
* errata mitigation on exception entry from lower ELs. * errata mitigation on exception entry from lower ELs.
*/ */
adr x0, wa_cve_vbar_cortex_makalu_elp_arm adr x0, wa_cve_vbar_cortex_x3
msr vbar_el3, x0 msr vbar_el3, x0
#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ #endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
isb isb
ret ret
endfunc cortex_makalu_elp_arm_reset_func endfunc cortex_x3_reset_func
#if REPORT_ERRATA #if REPORT_ERRATA
/* /*
* Errata printing function for Cortex Makalu ELP. Must follow AAPCS. * Errata printing function for Cortex-X3. Must follow AAPCS.
*/ */
func cortex_makalu_elp_arm_errata_report func cortex_x3_errata_report
stp x8, x30, [sp, #-16]! stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var bl cpu_get_rev_var
@ -82,15 +82,15 @@ func cortex_makalu_elp_arm_errata_report
* Report all errata. The revision-variant information is passed to * Report all errata. The revision-variant information is passed to
* checking functions of each errata. * checking functions of each errata.
*/ */
report_errata WORKAROUND_CVE_2022_23960, cortex_makalu_elp_arm, cve_2022_23960 report_errata WORKAROUND_CVE_2022_23960, cortex_x3, cve_2022_23960
ldp x8, x30, [sp], #16 ldp x8, x30, [sp], #16
ret ret
endfunc cortex_makalu_elp_arm_errata_report endfunc cortex_x3_errata_report
#endif #endif
/* --------------------------------------------- /* ---------------------------------------------
* This function provides Cortex Makalu ELP- * This function provides Cortex-X3-
* specific register information for crash * specific register information for crash
* reporting. It needs to return with x6 * reporting. It needs to return with x6
* pointing to a list of register names in ascii * pointing to a list of register names in ascii
@ -98,16 +98,16 @@ endfunc cortex_makalu_elp_arm_errata_report
* reported. * reported.
* --------------------------------------------- * ---------------------------------------------
*/ */
.section .rodata.cortex_makalu_elp_arm_regs, "aS" .section .rodata.cortex_x3_regs, "aS"
cortex_makalu_elp_arm_regs: /* The ascii list of register names to be reported */ cortex_x3_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", "" .asciz "cpuectlr_el1", ""
func cortex_makalu_elp_arm_cpu_reg_dump func cortex_x3_cpu_reg_dump
adr x6, cortex_makalu_elp_arm_regs adr x6, cortex_x3_regs
mrs x8, CORTEX_MAKALU_ELP_ARM_CPUECTLR_EL1 mrs x8, CORTEX_X3_CPUECTLR_EL1
ret ret
endfunc cortex_makalu_elp_arm_cpu_reg_dump endfunc cortex_x3_cpu_reg_dump
declare_cpu_ops cortex_makalu_elp_arm, CORTEX_MAKALU_ELP_ARM_MIDR, \ declare_cpu_ops cortex_x3, CORTEX_X3_MIDR, \
cortex_makalu_elp_arm_reset_func, \ cortex_x3_reset_func, \
cortex_makalu_elp_arm_core_pwr_dwn cortex_x3_core_pwr_dwn