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chore: rename Makalu ELP to Cortex-X3
The Cortex-X3 cpu port was developed before its public release when it was known as Makalu ELP. Now that it's released we can use the official product name. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: Iebb90cf2f77330ed848a3d61c5f6928942189c5a
This commit is contained in:
Boyan Karatotev
parent
36d18c542e
commit
cf58b2d41c
4 changed files with 41 additions and 41 deletions
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@ -18,7 +18,7 @@ Currently, the main difference between TC0 (TARGET_PLATFORM=0), TC1
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is the CPUs supported as below:
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- TC0 has support for Cortex A510, Cortex A710 and Cortex X2.
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- TC1 has support for Cortex A510, Cortex Makalu and Cortex Makalu ELP.
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- TC1 has support for Cortex A510, Cortex Makalu and Cortex X3.
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- TC2 has support for Hayes and Hunter Arm CPUs.
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@ -71,12 +71,12 @@ revisions of Cortex-A73 and Cortex-A75 that implements FEAT_CSV2).
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+----------------------+
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| Cortex-X2 |
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+----------------------+
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| Cortex-X3 |
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+----------------------+
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| Cortex-A710 |
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+----------------------+
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| Cortex-Makalu |
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+----------------------+
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| Cortex-Makalu-ELP |
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+----------------------+
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| Cortex-Hunter |
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+----------------------+
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| Neoverse-N1 |
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@ -4,23 +4,23 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_MAKALU_ELP_ARM_H
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#define CORTEX_MAKALU_ELP_ARM_H
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#ifndef CORTEX_X3_H
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#define CORTEX_X3_H
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#define CORTEX_MAKALU_ELP_ARM_MIDR U(0x410FD4E0)
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#define CORTEX_X3_MIDR U(0x410FD4E0)
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/* Cortex Makalu ELP loop count for CVE-2022-23960 mitigation */
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#define CORTEX_MAKALU_ELP_ARM_BHB_LOOP_COUNT U(132)
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/* Cortex-X3 loop count for CVE-2022-23960 mitigation */
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#define CORTEX_X3_BHB_LOOP_COUNT U(132)
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_MAKALU_ELP_ARM_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_X3_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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#define CORTEX_X3_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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#endif /* CORTEX_MAKALU_ELP_ARM_H */
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#endif /* CORTEX_X3_H */
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@ -7,40 +7,40 @@
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_makalu_elp_arm.h>
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#include <cortex_x3.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex Makalu ELP must be compiled with HW_ASSISTED_COHERENCY enabled"
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#error "Cortex-X3 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex Makalu ELP supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_MAKALU_ELP_ARM_BHB_LOOP_COUNT, cortex_makalu_elp_arm
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wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3
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#endif /* WORKAROUND_CVE_2022_23960 */
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_makalu_elp_arm_core_pwr_dwn
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func cortex_x3_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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mrs x0, CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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msr CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1, x0
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mrs x0, CORTEX_X3_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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msr CORTEX_X3_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_makalu_elp_arm_core_pwr_dwn
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endfunc cortex_x3_core_pwr_dwn
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func check_errata_cve_2022_23960
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#if WORKAROUND_CVE_2022_23960
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@ -51,28 +51,28 @@ func check_errata_cve_2022_23960
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ret
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endfunc check_errata_cve_2022_23960
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func cortex_makalu_elp_arm_reset_func
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func cortex_x3_reset_func
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/* Disable speculative loads */
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msr SSBS, xzr
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#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
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/*
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* The Cortex Makalu ELP generic vectors are overridden to apply
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* The Cortex-X3 generic vectors are overridden to apply
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* errata mitigation on exception entry from lower ELs.
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*/
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adr x0, wa_cve_vbar_cortex_makalu_elp_arm
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adr x0, wa_cve_vbar_cortex_x3
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msr vbar_el3, x0
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#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
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isb
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ret
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endfunc cortex_makalu_elp_arm_reset_func
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endfunc cortex_x3_reset_func
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex Makalu ELP. Must follow AAPCS.
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*/
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func cortex_makalu_elp_arm_errata_report
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/*
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* Errata printing function for Cortex-X3. Must follow AAPCS.
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*/
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func cortex_x3_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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@ -82,15 +82,15 @@ func cortex_makalu_elp_arm_errata_report
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata WORKAROUND_CVE_2022_23960, cortex_makalu_elp_arm, cve_2022_23960
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report_errata WORKAROUND_CVE_2022_23960, cortex_x3, cve_2022_23960
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_makalu_elp_arm_errata_report
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endfunc cortex_x3_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides Cortex Makalu ELP-
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* This function provides Cortex-X3-
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* specific register information for crash
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* reporting. It needs to return with x6
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* pointing to a list of register names in ascii
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@ -98,16 +98,16 @@ endfunc cortex_makalu_elp_arm_errata_report
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_makalu_elp_arm_regs, "aS"
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cortex_makalu_elp_arm_regs: /* The ascii list of register names to be reported */
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.section .rodata.cortex_x3_regs, "aS"
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cortex_x3_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_makalu_elp_arm_cpu_reg_dump
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adr x6, cortex_makalu_elp_arm_regs
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mrs x8, CORTEX_MAKALU_ELP_ARM_CPUECTLR_EL1
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func cortex_x3_cpu_reg_dump
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adr x6, cortex_x3_regs
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mrs x8, CORTEX_X3_CPUECTLR_EL1
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ret
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endfunc cortex_makalu_elp_arm_cpu_reg_dump
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endfunc cortex_x3_cpu_reg_dump
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declare_cpu_ops cortex_makalu_elp_arm, CORTEX_MAKALU_ELP_ARM_MIDR, \
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cortex_makalu_elp_arm_reset_func, \
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cortex_makalu_elp_arm_core_pwr_dwn
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declare_cpu_ops cortex_x3, CORTEX_X3_MIDR, \
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cortex_x3_reset_func, \
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cortex_x3_core_pwr_dwn
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