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feat(plat/qemu): add sdei support for QEMU

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Add sdei support for QEMU, this is to let jailhouse Hypervisor
use SDEI to do hypervisor management, after physical IRQ
has been disabled routing.

Note: To enable SDEI in QEMU, it needs to set "SDEI_SUPPORT=1
EL3_EXCEPTION_HANDLING=1" when compiling.

Signed-off-by: Dongjiu Geng <gengdongjiu1@gmail.com>
Change-Id: Ia7f9c5a0db36da03e5c6e6fb1270281f19924d77
This commit is contained in:
Dongjiu Geng 2023-04-04 19:24:11 +08:00
parent d557aaec77
commit cef76a7c5d
3 changed files with 60 additions and 3 deletions
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30
plat/qemu/common/qemu_sdei.c Normal file
View file

@ -0,0 +1,30 @@
/*
* Copyright (c) 2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/* SDEI configuration for ARM platforms */
#include <bl31/ehf.h>
#include <common/debug.h>
#include <lib/utils_def.h>
#include <services/sdei.h>
#include <platform_def.h>
/* Private event mappings */
static sdei_ev_map_t qemu_sdei_private[] = {
SDEI_DEFINE_EVENT_0(PLAT_SDEI_SGI_PRIVATE),
};
/* Shared event mappings */
static sdei_ev_map_t qemu_sdei_shared[] = {
};
void plat_sdei_setup(void)
{
INFO("SDEI platform setup\n");
}
/* Export Arm SDEI events */
REGISTER_SDEI_MAP(qemu_sdei_private, qemu_sdei_shared);

25
plat/qemu/qemu/include/platform_def.h
View file

@ -244,8 +244,7 @@
* interrupts.
*****************************************************************************/
#define PLATFORM_G1S_PROPS(grp) \
INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \
grp, GIC_INTR_CFG_EDGE), \
DESC_G1S_IRQ_SEC_SGI_0(grp) \
INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \
grp, GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \
@ -261,7 +260,19 @@
INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \
grp, GIC_INTR_CFG_EDGE)
#define PLATFORM_G0_PROPS(grp)
#if SDEI_SUPPORT
#define DESC_G0_IRQ_SEC_SGI(grp) \
INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \
GIC_INTR_CFG_EDGE)
#define DESC_G1S_IRQ_SEC_SGI_0(grp)
#else
#define DESC_G0_IRQ_SEC_SGI(grp)
#define DESC_G1S_IRQ_SEC_SGI_0(grp) \
INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \
GIC_INTR_CFG_EDGE),
#endif
#define PLATFORM_G0_PROPS(grp) DESC_G0_IRQ_SEC_SGI(grp)
/*
* DT related constants
@ -269,6 +280,14 @@
#define PLAT_QEMU_DT_BASE NS_DRAM0_BASE
#define PLAT_QEMU_DT_MAX_SIZE 0x100000
/*
* Platforms macros to support SDEI
*/
#define PLAT_PRI_BITS U(3)
#define PLAT_SDEI_CRITICAL_PRI 0x60
#define PLAT_SDEI_NORMAL_PRI 0x70
#define PLAT_SDEI_SGI_PRIVATE QEMU_IRQ_SEC_SGI_0
/*
* System counter
*/

8
plat/qemu/qemu/platform.mk
View file

@ -230,6 +230,10 @@ BL31_SOURCES += ${QEMU_CPU_LIBS} \
${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \
${QEMU_GIC_SOURCES}
ifeq (${SDEI_SUPPORT}, 1)
BL31_SOURCES += plat/qemu/common/qemu_sdei.c
endif
# Pointer Authentication sources
ifeq (${ENABLE_PAUTH}, 1)
PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c \
@ -323,3 +327,7 @@ qemu_fw.rom: qemu_fw.bios
ifneq (${BL33},)
all: qemu_fw.bios qemu_fw.rom
endif
ifeq (${EL3_EXCEPTION_HANDLING},1)
BL31_SOURCES += plat/common/aarch64/plat_ehf.c
endif