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Merge "refactor(cm): minor update on conditions used in prepare_el3_exit" into integration
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commit
ceedd1dc02
1 changed files with 24 additions and 20 deletions
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@ -959,8 +959,8 @@ void cm_prepare_el3_exit(uint32_t security_state)
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scr_el3 = read_ctx_reg(get_el3state_ctx(ctx),
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CTX_SCR_EL3);
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if (((scr_el3 & SCR_HCE_BIT) != 0U)
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|| (el2_implemented != EL_IMPL_NONE)) {
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if (el2_implemented != EL_IMPL_NONE) {
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/*
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* If context is not being used for EL2, initialize
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* HCRX_EL2 with its init value here.
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@ -986,28 +986,32 @@ void cm_prepare_el3_exit(uint32_t security_state)
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write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL);
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write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL);
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}
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}
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if ((scr_el3 & SCR_HCE_BIT) != 0U) {
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/* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
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sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx),
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CTX_SCTLR_EL1);
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sctlr_elx &= SCTLR_EE_BIT;
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sctlr_elx |= SCTLR_EL2_RES1;
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/* Condition to ensure EL2 is being used. */
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if ((scr_el3 & SCR_HCE_BIT) != 0U) {
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/* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
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sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx),
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CTX_SCTLR_EL1);
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sctlr_elx &= SCTLR_EE_BIT;
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sctlr_elx |= SCTLR_EL2_RES1;
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#if ERRATA_A75_764081
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/*
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* If workaround of errata 764081 for Cortex-A75 is used
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* then set SCTLR_EL2.IESB to enable Implicit Error
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* Synchronization Barrier.
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*/
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sctlr_elx |= SCTLR_IESB_BIT;
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#endif
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write_sctlr_el2(sctlr_elx);
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} else if (el2_implemented != EL_IMPL_NONE) {
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init_nonsecure_el2_unused(ctx);
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/*
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* If workaround of errata 764081 for Cortex-A75
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* is used then set SCTLR_EL2.IESB to enable
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* Implicit Error Synchronization Barrier.
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*/
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sctlr_elx |= SCTLR_IESB_BIT;
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#endif /* ERRATA_A75_764081 */
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write_sctlr_el2(sctlr_elx);
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} else {
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/*
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* (scr_el3 & SCR_HCE_BIT==0)
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* EL2 implemented but unused.
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*/
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init_nonsecure_el2_unused(ctx);
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}
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}
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}
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cm_el1_sysregs_context_restore(security_state);
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cm_set_next_eret_context(security_state);
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}
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