refactor(xilinx): move plat_get_syscnt_freq2 to common file

The code in the AMD-Xilinx platform for Versal and Versal NET is being
refactored to move the plat_get_syscnt_freq2() function to a common
file. This common function is utilized for obtaining the CPU clock
frequency from the platform.

Change-Id: I7a4c3fa43a2941d51cacd259c57b24e545aea848
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
This commit is contained in:
Prasad Kummari 2023-12-20 11:01:24 +05:30 committed by Kummari Prasad
parent 1f02024b19
commit cc3374ac63
3 changed files with 19 additions and 36 deletions

View file

@ -4,11 +4,30 @@
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#include <common/debug.h> #include <common/debug.h>
#include <lib/mmio.h>
#include <plat/common/platform.h> #include <plat/common/platform.h>
#include <platform_def.h> #include <platform_def.h>
#include <plat_private.h> #include <plat_private.h>
uint32_t plat_get_syscnt_freq2(void)
{
uint32_t counter_freq = 0;
uint32_t ret = 0;
counter_freq = mmio_read_32(IOU_SCNTRS_BASE +
IOU_SCNTRS_BASE_FREQ_OFFSET);
if (counter_freq != 0U) {
ret = counter_freq;
} else {
INFO("Indicates counter frequency %dHz setting to %dHz\n",
counter_freq, cpu_clock);
ret = cpu_clock;
}
return ret;
}
void set_cnt_freq(void) void set_cnt_freq(void)
{ {
uint64_t counter_freq; uint64_t counter_freq;

View file

@ -54,25 +54,6 @@ void versal_config_setup(void)
generic_delay_timer_init(); generic_delay_timer_init();
} }
uint32_t plat_get_syscnt_freq2(void)
{
uint32_t counter_freq = 0;
uint32_t ret = 0;
counter_freq = mmio_read_32(IOU_SCNTRS_BASE
+ IOU_SCNTRS_BASE_FREQ_OFFSET);
if (counter_freq != 0U) {
ret = counter_freq;
} else {
INFO("Indicates counter frequency %dHz setting to %dHz\n",
counter_freq, cpu_clock);
ret = cpu_clock;
}
return ret;
}
void board_detection(void) void board_detection(void)
{ {
uint32_t plat_info[2]; uint32_t plat_info[2];

View file

@ -149,20 +149,3 @@ void syscnt_freq_config_setup(void)
IOU_SCNTRS_CONTROL_EN); IOU_SCNTRS_CONTROL_EN);
} }
uint32_t plat_get_syscnt_freq2(void)
{
uint32_t counter_freq = 0;
uint32_t ret = 0;
counter_freq = mmio_read_32(IOU_SCNTRS_BASE +
IOU_SCNTRS_BASE_FREQ_OFFSET);
if (counter_freq != 0U) {
ret = counter_freq;
} else {
INFO("Indicates counter frequency %dHz setting to %dHz\n",
counter_freq, cpu_clock);
ret = cpu_clock;
}
return ret;
}