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feat(plat/arm/sgi): add CPU specific handler for Neoverse V1

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The 'CORE_PWRDN_EN' bit of 'CPUPWRCTLR_EL1' register requires an
explicit write to clear it for hotplug and idle to function correctly.
So add Neoverse V1 CPU specific handler in platform reset handler to
clear the CORE_PWRDN_EN bit.

Signed-off-by: shriram.k <shriram.k@arm.com>
Change-Id: I56084c42a56c401503a751cb518238c83cfca8ac
This commit is contained in:
shriram.k 2021-08-11 17:39:30 +05:30 • committed by Shriram K
parent 5447302fee
commit cbee43ebd6
1 changed files with 9 additions and 0 deletions
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9
plat/arm/css/sgi/aarch64/sgi_helper.S
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@ -9,6 +9,7 @@
#include <platform_def.h> #include <platform_def.h>
#include <cortex_a75.h> #include <cortex_a75.h>
#include <neoverse_n1.h> #include <neoverse_n1.h>
#include <neoverse_v1.h>
#include <cpu_macros.S> #include <cpu_macros.S>
.globl plat_arm_calc_core_pos .globl plat_arm_calc_core_pos
@ -66,6 +67,7 @@ endfunc plat_arm_calc_core_pos
func plat_reset_handler func plat_reset_handler
jump_if_cpu_midr CORTEX_A75_MIDR, A75 jump_if_cpu_midr CORTEX_A75_MIDR, A75
jump_if_cpu_midr NEOVERSE_N1_MIDR, N1 jump_if_cpu_midr NEOVERSE_N1_MIDR, N1
jump_if_cpu_midr NEOVERSE_V1_MIDR, V1
ret ret
/* ----------------------------------------------------- /* -----------------------------------------------------
@ -85,4 +87,11 @@ N1:
msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0
isb isb
ret ret
V1:
mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1
bic x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr NEOVERSE_V1_CPUPWRCTLR_EL1, x0
isb
ret
endfunc plat_reset_handler endfunc plat_reset_handler