Remove platform dependency in CCI-400 driver

* Create cci_init() function in CCI-400 driver to allow platform
  to provide arguments needed by the driver (i.e. base address
  and cluster indices for the ACE slave interfaces).

* Rename cci_(en|dis)able_coherency to
  cci_(en|dis)able_cluster_coherency to make it clear that
  the driver only enables/disables the coherency of CPU
  clusters and not other devices connected to the CCI-400.

* Update FVP port to use new cci_init() function and remove
  unnecessary CCI defintions from platform_def.h. Also rename
  fvp_cci_setup() to fvp_cci_enable() to more clearly
  differentiate between CCI initialization and enabling.

THIS CHANGE REQUIRES PLATFORM PORTS THAT USE THE CCI-400 DRIVER
TO BE UPDATED

Fixes ARM-software/tf-issues#168

Change-Id: I1946a51409b91217b92285b6375082619f607fec

drivers/arm/cci400/cci400.c

@@ -28,34 +28,80 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include <arch.h>
+#include <assert.h>
 #include <cci400.h>
 #include <mmio.h>
-#include <platform_def.h>
+
+#define MAX_CLUSTERS		2
+
+static unsigned long cci_base_addr;
+static unsigned int cci_cluster_ix_to_iface[MAX_CLUSTERS];
+
+
+void cci_init(unsigned long cci_base,
+		int slave_iface3_cluster_ix,
+		int slave_iface4_cluster_ix)
+{
+	/*
+	 * Check the passed arguments are valid. The cluster indices must be
+	 * less than MAX_CLUSTERS, not the same as each other and at least one
+	 * of them must be refer to a valid cluster index.
+	 */
+	assert(cci_base);
+	assert(slave_iface3_cluster_ix < MAX_CLUSTERS);
+	assert(slave_iface4_cluster_ix < MAX_CLUSTERS);
+	assert(slave_iface3_cluster_ix != slave_iface4_cluster_ix);
+	assert((slave_iface3_cluster_ix >= 0) ||
+		(slave_iface3_cluster_ix >= 0));
+
+	cci_base_addr = cci_base;
+	if (slave_iface3_cluster_ix >= 0)
+		cci_cluster_ix_to_iface[slave_iface3_cluster_ix] =
+			SLAVE_IFACE3_OFFSET;
+	if (slave_iface4_cluster_ix >= 0)
+		cci_cluster_ix_to_iface[slave_iface4_cluster_ix] =
+			SLAVE_IFACE4_OFFSET;
+}
 
 static inline unsigned long get_slave_iface_base(unsigned long mpidr)
 {
-	return CCI400_BASE + SLAVE_IFACE_OFFSET(CCI400_SL_IFACE_INDEX(mpidr));
+	/*
+	 * We assume the TF topology code allocates affinity instances
+	 * consecutively from zero.
+	 * It is a programming error if this is called without initializing
+	 * the slave interface to use for this cluster.
+	 */
+	unsigned int cluster_id =
+		(mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
+
+	assert(cluster_id < MAX_CLUSTERS);
+	assert(cci_cluster_ix_to_iface[cluster_id] != 0);
+
+	return cci_base_addr + cci_cluster_ix_to_iface[cluster_id];
 }
 
-void cci_enable_coherency(unsigned long mpidr)
+void cci_enable_cluster_coherency(unsigned long mpidr)
 {
+	assert(cci_base_addr);
 	/* Enable Snoops and DVM messages */
 	mmio_write_32(get_slave_iface_base(mpidr) + SNOOP_CTRL_REG,
 		      DVM_EN_BIT | SNOOP_EN_BIT);
 
 	/* Wait for the dust to settle down */
-	while (mmio_read_32(CCI400_BASE + STATUS_REG) & CHANGE_PENDING_BIT)
+	while (mmio_read_32(cci_base_addr + STATUS_REG) & CHANGE_PENDING_BIT)
 		;
 }
 
-void cci_disable_coherency(unsigned long mpidr)
+void cci_disable_cluster_coherency(unsigned long mpidr)
 {
+	assert(cci_base_addr);
 	/* Disable Snoops and DVM messages */
 	mmio_write_32(get_slave_iface_base(mpidr) + SNOOP_CTRL_REG,
 		      ~(DVM_EN_BIT | SNOOP_EN_BIT));
 
 	/* Wait for the dust to settle down */
-	while (mmio_read_32(CCI400_BASE + STATUS_REG) & CHANGE_PENDING_BIT)
+	while (mmio_read_32(cci_base_addr + STATUS_REG) & CHANGE_PENDING_BIT)
 		;
 }
 

include/drivers/arm/cci400.h

@@ -37,7 +37,8 @@
 #define SLAVE_IFACE2_OFFSET		0x3000
 #define SLAVE_IFACE1_OFFSET		0x2000
 #define SLAVE_IFACE0_OFFSET		0x1000
-#define SLAVE_IFACE_OFFSET(index)	SLAVE_IFACE0_OFFSET + (0x1000 * index)
+#define SLAVE_IFACE_OFFSET(index)	SLAVE_IFACE0_OFFSET +	\
+					(0x1000 * (index))
 
 /* Control and ID register offsets */
 #define CTRL_OVERRIDE_REG		0x0
@@ -68,8 +69,22 @@
 #ifndef __ASSEMBLY__
 
 /* Function declarations */
-void cci_enable_coherency(unsigned long mpidr);
+
-void cci_disable_coherency(unsigned long mpidr);
+/*
+ * The CCI-400 driver must be initialized with the base address of the
+ * CCI-400 device in the platform memory map, and the cluster indices for
+ * the CCI-400 slave interfaces 3 and 4 respectively. These are the fully
+ * coherent ACE slave interfaces of CCI-400.
+ * The cluster indices must either be 0 or 1, corresponding to the level 1
+ * affinity instance of the mpidr representing the cluster. A negative cluster
+ * index indicates that no cluster is present on that slave interface.
+ */
+void cci_init(unsigned long cci_base,
+		int slave_iface3_cluster_ix,
+		int slave_iface4_cluster_ix);
+
+void cci_enable_cluster_coherency(unsigned long mpidr);
+void cci_disable_cluster_coherency(unsigned long mpidr);
 
 #endif /* __ASSEMBLY__ */
 #endif /* __CCI_400_H__ */

plat/fvp/aarch64/fvp_common.c

@@ -31,7 +31,6 @@
 #include <arch.h>
 #include <arch_helpers.h>
 #include <arm_gic.h>
-#include <assert.h>
 #include <bl_common.h>
 #include <cci400.h>
 #include <debug.h>
@@ -243,15 +242,26 @@ uint64_t plat_get_syscnt_freq(void)
 	return counter_base_frequency;
 }
 
-void fvp_cci_setup(void)
+void fvp_cci_init(void)
 {
 	/*
-	 * Enable CCI-400 for this cluster. No need
+	 * Initialize CCI-400 driver
+	 */
+	if (plat_config.flags & CONFIG_HAS_CCI)
+		cci_init(CCI400_BASE,
+			CCI400_SL_IFACE3_CLUSTER_IX,
+			CCI400_SL_IFACE4_CLUSTER_IX);
+}
+
+void fvp_cci_enable(void)
+{
+	/*
+	 * Enable CCI-400 coherency for this cluster. No need
 	 * for locks as no other cpu is active at the
 	 * moment
 	 */
 	if (plat_config.flags & CONFIG_HAS_CCI)
-		cci_enable_coherency(read_mpidr());
+		cci_enable_cluster_coherency(read_mpidr());
 }
 
 void fvp_gic_init(void)

plat/fvp/bl1_fvp_setup.c

@@ -110,7 +110,8 @@ void bl1_platform_setup(void)
  ******************************************************************************/
 void bl1_plat_arch_setup(void)
 {
-	fvp_cci_setup();
+	fvp_cci_init();
+	fvp_cci_enable();
 
 	fvp_configure_mmu_el3(bl1_tzram_layout.total_base,
 			      bl1_tzram_layout.total_size,

plat/fvp/bl31_fvp_setup.c

@@ -230,9 +230,9 @@ void bl31_platform_setup(void)
  ******************************************************************************/
 void bl31_plat_arch_setup(void)
 {
+	fvp_cci_init();
 #if RESET_TO_BL31
-	fvp_cci_setup();
+	fvp_cci_enable();
-
 #endif
 	fvp_configure_mmu_el3(BL31_RO_BASE,
 			      (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),

plat/fvp/fvp_def.h

@@ -184,11 +184,8 @@
  * CCI-400 related constants
  ******************************************************************************/
 #define CCI400_BASE			0x2c090000
-#define CCI400_SL_IFACE_CLUSTER0	3
+#define CCI400_SL_IFACE3_CLUSTER_IX	0
-#define CCI400_SL_IFACE_CLUSTER1	4
+#define CCI400_SL_IFACE4_CLUSTER_IX	1
-#define CCI400_SL_IFACE_INDEX(mpidr)	(mpidr & MPIDR_CLUSTER_MASK ? \
-					 CCI400_SL_IFACE_CLUSTER1 :   \
-					 CCI400_SL_IFACE_CLUSTER0)
 
 /*******************************************************************************
  * GIC-400 & interrupt handling related constants

plat/fvp/fvp_pm.c

@@ -140,7 +140,7 @@ int fvp_affinst_off(unsigned long mpidr,
 			 * turned off
 			 */
 			if (get_plat_config()->flags & CONFIG_HAS_CCI)
-				cci_disable_coherency(mpidr);
+				cci_disable_cluster_coherency(mpidr);
 
 			/*
 			 * Program the power controller to turn the
@@ -215,7 +215,7 @@ int fvp_affinst_suspend(unsigned long mpidr,
 			 * turned off
 			 */
 			if (get_plat_config()->flags & CONFIG_HAS_CCI)
-				cci_disable_coherency(mpidr);
+				cci_disable_cluster_coherency(mpidr);
 
 			/*
 			 * Program the power controller to turn the
@@ -302,7 +302,7 @@ int fvp_affinst_on_finish(unsigned long mpidr,
 			 */
 			fvp_pwrc_write_pponr(mpidr);
 
-			fvp_cci_setup();
+			fvp_cci_enable();
 		}
 		break;
 

plat/fvp/fvp_private.h

@@ -77,7 +77,8 @@ void fvp_configure_mmu_el3(unsigned long total_base,
 			   unsigned long);
 int fvp_config_setup(void);
 
-void fvp_cci_setup(void);
+void fvp_cci_init(void);
+void fvp_cci_enable(void);
 
 void fvp_gic_init(void);
 

plat/fvp/include/plat_macros.S

@@ -30,7 +30,7 @@
 #include <cci400.h>
 #include <gic_v2.h>
 #include <plat_config.h>
-#include "platform_def.h"
+#include "../fvp_def.h"
 
 .section .rodata.gic_reg_name, "aS"
 gic_regs:

plat/fvp/include/platform_def.h

@@ -156,17 +156,6 @@
  ******************************************************************************/
 #define IRQ_SEC_PHY_TIMER		29
 
-/*******************************************************************************
- * CCI-400 related constants
- ******************************************************************************/
-#define CCI400_BASE			0x2c090000
-#define CCI400_SL_IFACE_CLUSTER0	3
-#define CCI400_SL_IFACE_CLUSTER1	4
-#define CCI400_SL_IFACE_INDEX(mpidr)	(mpidr & MPIDR_CLUSTER_MASK ? \
-					 CCI400_SL_IFACE_CLUSTER1 :   \
-					 CCI400_SL_IFACE_CLUSTER0)
-
-
 /*******************************************************************************
  * Declarations and constants to access the mailboxes safely. Each mailbox is
  * aligned on the biggest cache line size in the platform. This is known only