From ca93b018dc7aeebb84641b73edab6ca85b7a5908 Mon Sep 17 00:00:00 2001 From: Bo-Chen Chen Date: Thu, 1 Sep 2022 15:16:23 +0800 Subject: [PATCH] refator(mediatek): move common definitions of pmic wrap to common folder Some definitions can be shared among mt8192, mt8195, and mt8186, so move them to pmic_wrap_init_common.h. Signed-off-by: Bo-Chen Chen Change-Id: I992b61a47a84039fe8c246e2ff75721c57ee41a5 --- .../drivers/pmic_wrap/pmic_wrap_init_common.h | 61 +++++++++++++++++++ .../mt8186/drivers/pmic/pmic_wrap_init.h | 37 +---------- plat/mediatek/mt8186/platform.mk | 1 + .../mt8192/drivers/pmic/pmic_wrap_init.h | 50 +-------------- plat/mediatek/mt8192/platform.mk | 1 + .../mt8195/drivers/pmic/pmic_wrap_init.h | 50 +-------------- plat/mediatek/mt8195/platform.mk | 1 + 7 files changed, 70 insertions(+), 131 deletions(-) create mode 100644 plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h diff --git a/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h new file mode 100644 index 000000000..4ba1f5c7b --- /dev/null +++ b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PMIC_WRAP_INIT_COMMON_H +#define PMIC_WRAP_INIT_COMMON_H + +#include + +#include "platform_def.h" + +/* external API */ +int32_t pwrap_read(uint32_t adr, uint32_t *rdata); +int32_t pwrap_write(uint32_t adr, uint32_t wdata); + +#define GET_WACS_FSM(x) ((x >> 1) & 0x7) + +/* macro for SWINF_FSM */ +#define SWINF_FSM_IDLE (0x00) +#define SWINF_FSM_REQ (0x02) +#define SWINF_FSM_WFDLE (0x04) +#define SWINF_FSM_WFVLDCLR (0x06) +#define SWINF_INIT_DONE (0x01) + +/* timeout setting */ +#define PWRAP_READ_US (1000) +#define PWRAP_WAIT_IDLE_US (1000) + +/* error information flag */ +enum pwrap_errno { + E_PWR_INVALID_ARG = 1, + E_PWR_INVALID_RW = 2, + E_PWR_INVALID_ADDR = 3, + E_PWR_INVALID_WDAT = 4, + E_PWR_INVALID_OP_MANUAL = 5, + E_PWR_NOT_IDLE_STATE = 6, + E_PWR_NOT_INIT_DONE = 7, + E_PWR_NOT_INIT_DONE_READ = 8, + E_PWR_WAIT_IDLE_TIMEOUT = 9, + E_PWR_WAIT_IDLE_TIMEOUT_READ = 10, + E_PWR_INIT_SIDLY_FAIL = 11, + E_PWR_RESET_TIMEOUT = 12, + E_PWR_TIMEOUT = 13, + E_PWR_INIT_RESET_SPI = 20, + E_PWR_INIT_SIDLY = 21, + E_PWR_INIT_REG_CLOCK = 22, + E_PWR_INIT_ENABLE_PMIC = 23, + E_PWR_INIT_DIO = 24, + E_PWR_INIT_CIPHER = 25, + E_PWR_INIT_WRITE_TEST = 26, + E_PWR_INIT_ENABLE_CRC = 27, + E_PWR_INIT_ENABLE_DEWRAP = 28, + E_PWR_INIT_ENABLE_EVENT = 29, + E_PWR_READ_TEST_FAIL = 30, + E_PWR_WRITE_TEST_FAIL = 31, + E_PWR_SWITCH_DIO = 32, +}; + +#endif /* PMIC_WRAP_INIT_COMMON_H */ diff --git a/plat/mediatek/mt8186/drivers/pmic/pmic_wrap_init.h b/plat/mediatek/mt8186/drivers/pmic/pmic_wrap_init.h index e837456fb..e8cbf7ee6 100644 --- a/plat/mediatek/mt8186/drivers/pmic/pmic_wrap_init.h +++ b/plat/mediatek/mt8186/drivers/pmic/pmic_wrap_init.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, MediaTek Inc. All rights reserved. + * Copyright (c) 2021-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,10 +10,7 @@ #include #include "platform_def.h" - -/* external API */ -int32_t pwrap_read(uint32_t adr, uint32_t *rdata); -int32_t pwrap_write(uint32_t adr, uint32_t wdata); +#include static struct mt8186_pmic_wrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE; @@ -61,34 +58,4 @@ enum { WACS_SYNC_BUSY = 0x00 }; -/* error information flag */ -enum { - E_PWR_INVALID_ARG = 1, - E_PWR_INVALID_RW = 2, - E_PWR_INVALID_ADDR = 3, - E_PWR_INVALID_WDAT = 4, - E_PWR_INVALID_OP_MANUAL = 5, - E_PWR_NOT_IDLE_STATE = 6, - E_PWR_NOT_INIT_DONE = 7, - E_PWR_NOT_INIT_DONE_READ = 8, - E_PWR_WAIT_IDLE_TIMEOUT = 9, - E_PWR_WAIT_IDLE_TIMEOUT_READ = 10, - E_PWR_INIT_SIDLY_FAIL = 11, - E_PWR_RESET_TIMEOUT = 12, - E_PWR_TIMEOUT = 13, - E_PWR_INIT_RESET_SPI = 20, - E_PWR_INIT_SIDLY = 21, - E_PWR_INIT_REG_CLOCK = 22, - E_PWR_INIT_ENABLE_PMIC = 23, - E_PWR_INIT_DIO = 24, - E_PWR_INIT_CIPHER = 25, - E_PWR_INIT_WRITE_TEST = 26, - E_PWR_INIT_ENABLE_CRC = 27, - E_PWR_INIT_ENABLE_DEWRAP = 28, - E_PWR_INIT_ENABLE_EVENT = 29, - E_PWR_READ_TEST_FAIL = 30, - E_PWR_WRITE_TEST_FAIL = 31, - E_PWR_SWITCH_DIO = 32 -}; - #endif /* PMIC_WRAP_INIT_H */ diff --git a/plat/mediatek/mt8186/platform.mk b/plat/mediatek/mt8186/platform.mk index 0b3646af3..8717d7d3e 100644 --- a/plat/mediatek/mt8186/platform.mk +++ b/plat/mediatek/mt8186/platform.mk @@ -12,6 +12,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ -I${MTK_PLAT}/drivers/gic600/ \ -I${MTK_PLAT}/drivers/gpio/ \ -I${MTK_PLAT}/drivers/lpm/ \ + -I${MTK_PLAT}/drivers/pmic_wrap/ \ -I${MTK_PLAT}/drivers/timer/ \ -I${MTK_PLAT}/drivers/uart/ \ -I${MTK_PLAT}/include/ \ diff --git a/plat/mediatek/mt8192/drivers/pmic/pmic_wrap_init.h b/plat/mediatek/mt8192/drivers/pmic/pmic_wrap_init.h index ae892ed5a..b9ab586d5 100644 --- a/plat/mediatek/mt8192/drivers/pmic/pmic_wrap_init.h +++ b/plat/mediatek/mt8192/drivers/pmic/pmic_wrap_init.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,10 +10,7 @@ #include #include "platform_def.h" - -/* external API */ -int32_t pwrap_read(uint32_t adr, uint32_t *rdata); -int32_t pwrap_write(uint32_t adr, uint32_t wdata); +#include static struct mt8192_pmic_wrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE; @@ -30,47 +27,4 @@ struct mt8192_pmic_wrap_regs { uint32_t wacs2_sta; }; -#define GET_WACS_FSM(x) ((x >> 1) & 0x7) - -/* macro for SWINF_FSM */ -#define SWINF_FSM_IDLE (0x00) -#define SWINF_FSM_REQ (0x02) -#define SWINF_FSM_WFDLE (0x04) -#define SWINF_FSM_WFVLDCLR (0x06) -#define SWINF_INIT_DONE (0x01) - -/* timeout setting */ -#define PWRAP_READ_US 1000 -#define PWRAP_WAIT_IDLE_US 1000 - -/* error information flag */ -enum pwrap_errno { - E_PWR_INVALID_ARG = 1, - E_PWR_INVALID_RW = 2, - E_PWR_INVALID_ADDR = 3, - E_PWR_INVALID_WDAT = 4, - E_PWR_INVALID_OP_MANUAL = 5, - E_PWR_NOT_IDLE_STATE = 6, - E_PWR_NOT_INIT_DONE = 7, - E_PWR_NOT_INIT_DONE_READ = 8, - E_PWR_WAIT_IDLE_TIMEOUT = 9, - E_PWR_WAIT_IDLE_TIMEOUT_READ = 10, - E_PWR_INIT_SIDLY_FAIL = 11, - E_PWR_RESET_TIMEOUT = 12, - E_PWR_TIMEOUT = 13, - E_PWR_INIT_RESET_SPI = 20, - E_PWR_INIT_SIDLY = 21, - E_PWR_INIT_REG_CLOCK = 22, - E_PWR_INIT_ENABLE_PMIC = 23, - E_PWR_INIT_DIO = 24, - E_PWR_INIT_CIPHER = 25, - E_PWR_INIT_WRITE_TEST = 26, - E_PWR_INIT_ENABLE_CRC = 27, - E_PWR_INIT_ENABLE_DEWRAP = 28, - E_PWR_INIT_ENABLE_EVENT = 29, - E_PWR_READ_TEST_FAIL = 30, - E_PWR_WRITE_TEST_FAIL = 31, - E_PWR_SWITCH_DIO = 32 -}; - #endif /* PMIC_WRAP_INIT_H */ diff --git a/plat/mediatek/mt8192/platform.mk b/plat/mediatek/mt8192/platform.mk index e26d464c3..ccc9a718e 100644 --- a/plat/mediatek/mt8192/platform.mk +++ b/plat/mediatek/mt8192/platform.mk @@ -12,6 +12,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ -I${MTK_PLAT}/drivers/gic600/ \ -I${MTK_PLAT}/drivers/gpio/ \ -I${MTK_PLAT}/drivers/lpm/ \ + -I${MTK_PLAT}/drivers/pmic_wrap/ \ -I${MTK_PLAT}/drivers/rtc/ \ -I${MTK_PLAT}/drivers/timer/ \ -I${MTK_PLAT}/drivers/uart/ \ diff --git a/plat/mediatek/mt8195/drivers/pmic/pmic_wrap_init.h b/plat/mediatek/mt8195/drivers/pmic/pmic_wrap_init.h index 39e78f5f3..9e6e74cb6 100644 --- a/plat/mediatek/mt8195/drivers/pmic/pmic_wrap_init.h +++ b/plat/mediatek/mt8195/drivers/pmic/pmic_wrap_init.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,10 +10,7 @@ #include #include "platform_def.h" - -/* external API */ -int32_t pwrap_read(uint32_t adr, uint32_t *rdata); -int32_t pwrap_write(uint32_t adr, uint32_t wdata); +#include static struct mt8195_pmic_wrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE; @@ -30,47 +27,4 @@ struct mt8195_pmic_wrap_regs { uint32_t wacs2_sta; }; -#define GET_WACS_FSM(x) ((x >> 1) & 0x7) - -/* macro for SWINF_FSM */ -#define SWINF_FSM_IDLE (0x00) -#define SWINF_FSM_REQ (0x02) -#define SWINF_FSM_WFDLE (0x04) -#define SWINF_FSM_WFVLDCLR (0x06) -#define SWINF_INIT_DONE (0x01) - -/* timeout setting */ -#define PWRAP_READ_US 1000 -#define PWRAP_WAIT_IDLE_US 1000 - -/* error information flag */ -enum pwrap_errno { - E_PWR_INVALID_ARG = 1, - E_PWR_INVALID_RW = 2, - E_PWR_INVALID_ADDR = 3, - E_PWR_INVALID_WDAT = 4, - E_PWR_INVALID_OP_MANUAL = 5, - E_PWR_NOT_IDLE_STATE = 6, - E_PWR_NOT_INIT_DONE = 7, - E_PWR_NOT_INIT_DONE_READ = 8, - E_PWR_WAIT_IDLE_TIMEOUT = 9, - E_PWR_WAIT_IDLE_TIMEOUT_READ = 10, - E_PWR_INIT_SIDLY_FAIL = 11, - E_PWR_RESET_TIMEOUT = 12, - E_PWR_TIMEOUT = 13, - E_PWR_INIT_RESET_SPI = 20, - E_PWR_INIT_SIDLY = 21, - E_PWR_INIT_REG_CLOCK = 22, - E_PWR_INIT_ENABLE_PMIC = 23, - E_PWR_INIT_DIO = 24, - E_PWR_INIT_CIPHER = 25, - E_PWR_INIT_WRITE_TEST = 26, - E_PWR_INIT_ENABLE_CRC = 27, - E_PWR_INIT_ENABLE_DEWRAP = 28, - E_PWR_INIT_ENABLE_EVENT = 29, - E_PWR_READ_TEST_FAIL = 30, - E_PWR_WRITE_TEST_FAIL = 31, - E_PWR_SWITCH_DIO = 32 -}; - #endif /* PMIC_WRAP_INIT_H */ diff --git a/plat/mediatek/mt8195/platform.mk b/plat/mediatek/mt8195/platform.mk index 05fde45b7..3d0e64495 100644 --- a/plat/mediatek/mt8195/platform.mk +++ b/plat/mediatek/mt8195/platform.mk @@ -13,6 +13,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ -I${MTK_PLAT}/drivers/gic600/ \ -I${MTK_PLAT}/drivers/gpio/ \ -I${MTK_PLAT}/drivers/lpm/ \ + -I${MTK_PLAT}/drivers/pmic_wrap/ \ -I${MTK_PLAT}/drivers/rtc/ \ -I${MTK_PLAT}/drivers/timer/ \ -I${MTK_PLAT}/drivers/uart/ \