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ARMv7: support non-LPAE mapping (not xlat_v2)
Support 32bit descriptor MMU table. This is required by ARMv7 architectures that do not support the Large Page Address Extensions. nonlpae_tables.c source file is dumped from the OP-TEE project: core_mmu_armv7.c and related header files. Change-Id: If912d66c374290c49c5a1211ce4c5c27b2d7dc60 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Usama Arif <usama.arif@arm.com>
This commit is contained in:
Etienne Carriere
Usama Arif
parent
6393c787b5
commit
c9fe6fed4b
2 changed files with 555 additions and 1 deletions
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@ -73,7 +73,11 @@
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#define PAGE_SIZE_MASK (PAGE_SIZE - U(1))
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#define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == U(0))
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#define XLAT_ENTRY_SIZE_SHIFT U(3) /* Each MMU table entry is 8 bytes (1 << 3) */
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#if (ARM_ARCH_MAJOR == 7) && !ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING
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#define XLAT_ENTRY_SIZE_SHIFT U(2) /* Each MMU table entry is 4 bytes */
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#else
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#define XLAT_ENTRY_SIZE_SHIFT U(3) /* Each MMU table entry is 8 bytes */
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#endif
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#define XLAT_ENTRY_SIZE (U(1) << XLAT_ENTRY_SIZE_SHIFT)
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#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one complete table */
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550
lib/xlat_tables/aarch32/nonlpae_tables.c
Normal file
550
lib/xlat_tables/aarch32/nonlpae_tables.c
Normal file
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@ -0,0 +1,550 @@
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/*
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* Copyright (c) 2016-2017, Linaro Limited. All rights reserved.
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* Copyright (c) 2014-2017, Arm Limited. All rights reserved.
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* Copyright (c) 2014, STMicroelectronics International N.V.
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stdio.h>
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#include <string.h>
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#include <platform_def.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/cassert.h>
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#include <lib/utils.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include "../xlat_tables_private.h"
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#ifdef ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING
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#error "ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING flag is set. \
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This module is to be used when LPAE is not supported"
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#endif
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CASSERT(PLAT_VIRT_ADDR_SPACE_SIZE == (1ULL << 32), invalid_vaddr_space_size);
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CASSERT(PLAT_PHY_ADDR_SPACE_SIZE == (1ULL << 32), invalid_paddr_space_size);
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#define MMU32B_UNSET_DESC ~0ul
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#define MMU32B_INVALID_DESC 0ul
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#define MT_UNKNOWN ~0U
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/*
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* MMU related values
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*/
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/* Sharable */
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#define MMU32B_TTB_S (1 << 1)
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/* Not Outer Sharable */
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#define MMU32B_TTB_NOS (1 << 5)
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/* Normal memory, Inner Non-cacheable */
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#define MMU32B_TTB_IRGN_NC 0
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/* Normal memory, Inner Write-Back Write-Allocate Cacheable */
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#define MMU32B_TTB_IRGN_WBWA (1 << 6)
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/* Normal memory, Inner Write-Through Cacheable */
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#define MMU32B_TTB_IRGN_WT 1
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/* Normal memory, Inner Write-Back no Write-Allocate Cacheable */
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#define MMU32B_TTB_IRGN_WB (1 | (1 << 6))
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/* Normal memory, Outer Write-Back Write-Allocate Cacheable */
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#define MMU32B_TTB_RNG_WBWA (1 << 3)
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#define MMU32B_DEFAULT_ATTRS \
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(MMU32B_TTB_S | MMU32B_TTB_NOS | \
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MMU32B_TTB_IRGN_WBWA | MMU32B_TTB_RNG_WBWA)
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/* armv7 memory mapping attributes: section mapping */
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#define SECTION_SECURE (0 << 19)
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#define SECTION_NOTSECURE (1 << 19)
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#define SECTION_SHARED (1 << 16)
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#define SECTION_NOTGLOBAL (1 << 17)
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#define SECTION_ACCESS_FLAG (1 << 10)
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#define SECTION_UNPRIV (1 << 11)
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#define SECTION_RO (1 << 15)
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#define SECTION_TEX(tex) ((((tex) >> 2) << 12) | \
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((((tex) >> 1) & 0x1) << 3) | \
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(((tex) & 0x1) << 2))
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#define SECTION_DEVICE SECTION_TEX(MMU32B_ATTR_DEVICE_INDEX)
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#define SECTION_NORMAL SECTION_TEX(MMU32B_ATTR_DEVICE_INDEX)
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#define SECTION_NORMAL_CACHED \
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SECTION_TEX(MMU32B_ATTR_IWBWA_OWBWA_INDEX)
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#define SECTION_XN (1 << 4)
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#define SECTION_PXN (1 << 0)
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#define SECTION_SECTION (2 << 0)
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#define SECTION_PT_NOTSECURE (1 << 3)
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#define SECTION_PT_PT (1 << 0)
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#define SMALL_PAGE_SMALL_PAGE (1 << 1)
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#define SMALL_PAGE_SHARED (1 << 10)
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#define SMALL_PAGE_NOTGLOBAL (1 << 11)
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#define SMALL_PAGE_TEX(tex) ((((tex) >> 2) << 6) | \
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((((tex) >> 1) & 0x1) << 3) | \
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(((tex) & 0x1) << 2))
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#define SMALL_PAGE_DEVICE \
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SMALL_PAGE_TEX(MMU32B_ATTR_DEVICE_INDEX)
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#define SMALL_PAGE_NORMAL \
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SMALL_PAGE_TEX(MMU32B_ATTR_DEVICE_INDEX)
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#define SMALL_PAGE_NORMAL_CACHED \
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SMALL_PAGE_TEX(MMU32B_ATTR_IWBWA_OWBWA_INDEX)
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#define SMALL_PAGE_ACCESS_FLAG (1 << 4)
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#define SMALL_PAGE_UNPRIV (1 << 5)
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#define SMALL_PAGE_RO (1 << 9)
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#define SMALL_PAGE_XN (1 << 0)
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/* The TEX, C and B bits concatenated */
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#define MMU32B_ATTR_DEVICE_INDEX 0x0
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#define MMU32B_ATTR_IWBWA_OWBWA_INDEX 0x1
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#define MMU32B_PRRR_IDX(idx, tr, nos) (((tr) << (2 * (idx))) | \
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((uint32_t)(nos) << ((idx) + 24)))
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#define MMU32B_NMRR_IDX(idx, ir, or) (((ir) << (2 * (idx))) | \
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((uint32_t)(or) << (2 * (idx) + 16)))
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#define MMU32B_PRRR_DS0 (1 << 16)
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#define MMU32B_PRRR_DS1 (1 << 17)
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#define MMU32B_PRRR_NS0 (1 << 18)
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#define MMU32B_PRRR_NS1 (1 << 19)
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#define DACR_DOMAIN(num, perm) ((perm) << ((num) * 2))
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#define DACR_DOMAIN_PERM_NO_ACCESS 0x0
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#define DACR_DOMAIN_PERM_CLIENT 0x1
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#define DACR_DOMAIN_PERM_MANAGER 0x3
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#define NUM_1MB_IN_4GB (1 << 12)
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#define NUM_4K_IN_1MB (1 << 8)
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#define ONE_MB_SHIFT 20
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/* mmu 32b integration */
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#define MMU32B_L1_TABLE_SIZE (NUM_1MB_IN_4GB * 4)
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#define MMU32B_L2_TABLE_SIZE (NUM_4K_IN_1MB * 4)
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#define MMU32B_L1_TABLE_ALIGN (1 << 14)
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#define MMU32B_L2_TABLE_ALIGN (1 << 10)
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static unsigned int next_xlat;
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static unsigned long long xlat_max_pa;
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static uintptr_t xlat_max_va;
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static uint32_t mmu_l1_base[NUM_1MB_IN_4GB]
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__aligned(MMU32B_L1_TABLE_ALIGN) __attribute__((section("xlat_table")));
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static uint32_t mmu_l2_base[MAX_XLAT_TABLES][NUM_4K_IN_1MB]
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__aligned(MMU32B_L2_TABLE_ALIGN) __attribute__((section("xlat_table")));
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/*
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* Array of all memory regions stored in order of ascending base address.
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* The list is terminated by the first entry with size == 0.
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*/
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static mmap_region_t mmap[MAX_MMAP_REGIONS + 1];
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void print_mmap(void)
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{
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#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
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mmap_region_t *mm = mmap;
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printf("init xlat - l1:%p l2:%p (%d)\n",
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(void *)mmu_l1_base, (void *)mmu_l2_base, MAX_XLAT_TABLES);
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printf("mmap:\n");
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while (mm->size) {
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printf(" VA:%p PA:0x%llx size:0x%zx attr:0x%x\n",
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(void *)mm->base_va, mm->base_pa,
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mm->size, mm->attr);
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++mm;
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};
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printf("\n");
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#endif
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}
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void mmap_add(const mmap_region_t *mm)
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{
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const mmap_region_t *mm_cursor = mm;
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while ((mm_cursor->size != 0U) || (mm_cursor->attr != 0U)) {
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mmap_add_region(mm_cursor->base_pa, mm_cursor->base_va,
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mm_cursor->size, mm_cursor->attr);
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mm_cursor++;
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}
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}
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void mmap_add_region(unsigned long long base_pa, uintptr_t base_va,
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size_t size, unsigned int attr)
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{
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mmap_region_t *mm = mmap;
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const mmap_region_t *mm_last = mm + ARRAY_SIZE(mmap) - 1U;
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unsigned long long end_pa = base_pa + size - 1U;
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uintptr_t end_va = base_va + size - 1U;
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assert(IS_PAGE_ALIGNED(base_pa));
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assert(IS_PAGE_ALIGNED(base_va));
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assert(IS_PAGE_ALIGNED(size));
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if (size == 0U)
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return;
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assert(base_pa < end_pa); /* Check for overflows */
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assert(base_va < end_va);
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assert((base_va + (uintptr_t)size - (uintptr_t)1) <=
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(PLAT_VIRT_ADDR_SPACE_SIZE - 1U));
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assert((base_pa + (unsigned long long)size - 1ULL) <=
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(PLAT_PHY_ADDR_SPACE_SIZE - 1U));
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#if ENABLE_ASSERTIONS
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/* Check for PAs and VAs overlaps with all other regions */
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for (mm = mmap; mm->size; ++mm) {
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uintptr_t mm_end_va = mm->base_va + mm->size - 1U;
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/*
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* Check if one of the regions is completely inside the other
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* one.
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*/
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bool fully_overlapped_va =
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((base_va >= mm->base_va) && (end_va <= mm_end_va)) ||
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((mm->base_va >= base_va) && (mm_end_va <= end_va));
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/*
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* Full VA overlaps are only allowed if both regions are
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* identity mapped (zero offset) or have the same VA to PA
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* offset. Also, make sure that it's not the exact same area.
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*/
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if (fully_overlapped_va) {
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assert((mm->base_va - mm->base_pa) ==
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(base_va - base_pa));
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assert((base_va != mm->base_va) || (size != mm->size));
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} else {
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/*
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* If the regions do not have fully overlapping VAs,
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* then they must have fully separated VAs and PAs.
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* Partial overlaps are not allowed
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*/
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unsigned long long mm_end_pa =
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mm->base_pa + mm->size - 1;
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bool separated_pa = (end_pa < mm->base_pa) ||
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(base_pa > mm_end_pa);
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bool separated_va = (end_va < mm->base_va) ||
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(base_va > mm_end_va);
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assert(separated_va && separated_pa);
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}
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}
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mm = mmap; /* Restore pointer to the start of the array */
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#endif /* ENABLE_ASSERTIONS */
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/* Find correct place in mmap to insert new region */
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while ((mm->base_va < base_va) && (mm->size != 0U))
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++mm;
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/*
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* If a section is contained inside another one with the same base
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* address, it must be placed after the one it is contained in:
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*
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* 1st |-----------------------|
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* 2nd |------------|
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* 3rd |------|
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*
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* This is required for mmap_region_attr() to get the attributes of the
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* small region correctly.
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*/
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while ((mm->base_va == base_va) && (mm->size > size))
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++mm;
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/* Make room for new region by moving other regions up by one place */
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(void)memmove(mm + 1, mm, (uintptr_t)mm_last - (uintptr_t)mm);
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/* Check we haven't lost the empty sentinal from the end of the array */
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assert(mm_last->size == 0U);
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mm->base_pa = base_pa;
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mm->base_va = base_va;
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mm->size = size;
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mm->attr = attr;
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if (end_pa > xlat_max_pa)
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xlat_max_pa = end_pa;
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if (end_va > xlat_max_va)
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xlat_max_va = end_va;
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}
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/* map all memory as shared/global/domain0/no-usr access */
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static unsigned long mmap_desc(unsigned attr, unsigned long addr_pa,
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unsigned int level)
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{
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unsigned long desc;
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switch (level) {
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case 1:
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assert(!(addr_pa & (MMU32B_L1_TABLE_ALIGN - 1)));
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desc = SECTION_SECTION | SECTION_SHARED;
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desc |= attr & MT_NS ? SECTION_NOTSECURE : 0;
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desc |= SECTION_ACCESS_FLAG;
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desc |= attr & MT_RW ? 0 : SECTION_RO;
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desc |= attr & MT_MEMORY ?
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SECTION_NORMAL_CACHED : SECTION_DEVICE;
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if ((attr & MT_RW) || !(attr & MT_MEMORY))
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desc |= SECTION_XN;
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break;
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case 2:
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assert(!(addr_pa & (MMU32B_L2_TABLE_ALIGN - 1)));
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desc = SMALL_PAGE_SMALL_PAGE | SMALL_PAGE_SHARED;
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desc |= SMALL_PAGE_ACCESS_FLAG;
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desc |= attr & MT_RW ? 0 : SMALL_PAGE_RO;
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desc |= attr & MT_MEMORY ?
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SMALL_PAGE_NORMAL_CACHED : SMALL_PAGE_DEVICE;
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if ((attr & MT_RW) || !(attr & MT_MEMORY))
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desc |= SMALL_PAGE_XN;
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break;
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default:
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panic();
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}
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#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
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/* dump only the non-lpae level 2 tables */
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if (level == 2) {
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printf(attr & MT_MEMORY ? "MEM" : "dev");
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printf(attr & MT_RW ? "-rw" : "-RO");
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printf(attr & MT_NS ? "-NS" : "-S");
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}
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#endif
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return desc | addr_pa;
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}
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static unsigned int mmap_region_attr(const mmap_region_t *mm, uintptr_t base_va,
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size_t size, unsigned int *attr)
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{
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/* Don't assume that the area is contained in the first region */
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unsigned int ret = MT_UNKNOWN;
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/*
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* Get attributes from last (innermost) region that contains the
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* requested area. Don't stop as soon as one region doesn't contain it
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* because there may be other internal regions that contain this area:
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*
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* |-----------------------------1-----------------------------|
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* |----2----| |-------3-------| |----5----|
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* |--4--|
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*
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* |---| <- Area we want the attributes of.
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*
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* In this example, the area is contained in regions 1, 3 and 4 but not
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* in region 2. The loop shouldn't stop at region 2 as inner regions
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* have priority over outer regions, it should stop at region 5.
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*/
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for ( ; ; ++mm) {
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if (mm->size == 0U)
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return ret; /* Reached end of list */
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if (mm->base_va > (base_va + size - 1U))
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return ret; /* Next region is after area so end */
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if ((mm->base_va + mm->size - 1U) < base_va)
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continue; /* Next region has already been overtaken */
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if ((ret == 0U) && (mm->attr == *attr))
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continue; /* Region doesn't override attribs so skip */
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if ((mm->base_va > base_va) ||
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((mm->base_va + mm->size - 1U) < (base_va + size - 1U)))
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return MT_UNKNOWN; /* Region doesn't fully cover area */
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*attr = mm->attr;
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ret = 0U;
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}
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return ret;
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}
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static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm,
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unsigned long base_va,
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unsigned long *table,
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unsigned int level)
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{
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unsigned int level_size_shift = (level == 1) ?
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ONE_MB_SHIFT : FOUR_KB_SHIFT;
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unsigned int level_size = 1 << level_size_shift;
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unsigned long level_index_mask = (level == 1) ?
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(NUM_1MB_IN_4GB - 1) << ONE_MB_SHIFT :
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(NUM_4K_IN_1MB - 1) << FOUR_KB_SHIFT;
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assert(level == 1 || level == 2);
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VERBOSE("init xlat table at %p (level%1d)\n", (void *)table, level);
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do {
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unsigned long desc = MMU32B_UNSET_DESC;
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if (mm->base_va + mm->size <= base_va) {
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/* Area now after the region so skip it */
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++mm;
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continue;
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}
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#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
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/* dump only non-lpae level 2 tables content */
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if (level == 2)
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printf(" 0x%lx %x " + 6 - 2 * level,
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base_va, level_size);
|
||||
#endif
|
||||
if (mm->base_va >= base_va + level_size) {
|
||||
/* Next region is after area so nothing to map yet */
|
||||
desc = MMU32B_INVALID_DESC;
|
||||
} else if (mm->base_va <= base_va && mm->base_va + mm->size >=
|
||||
base_va + level_size) {
|
||||
/* Next region covers all of area */
|
||||
unsigned int attr = mm->attr;
|
||||
unsigned int r = mmap_region_attr(mm, base_va,
|
||||
level_size, &attr);
|
||||
|
||||
if (r == 0U) {
|
||||
desc = mmap_desc(attr,
|
||||
base_va - mm->base_va + mm->base_pa,
|
||||
level);
|
||||
}
|
||||
}
|
||||
|
||||
if (desc == MMU32B_UNSET_DESC) {
|
||||
unsigned long xlat_table;
|
||||
|
||||
/*
|
||||
* Area not covered by a region so need finer table
|
||||
* Reuse next level table if any (assert attrib matching).
|
||||
* Otherwise allocate a xlat table.
|
||||
*/
|
||||
if (*table) {
|
||||
assert((*table & 3) == SECTION_PT_PT);
|
||||
assert(!(*table & SECTION_PT_NOTSECURE) ==
|
||||
!(mm->attr & MT_NS));
|
||||
|
||||
xlat_table = (*table) &
|
||||
~(MMU32B_L1_TABLE_ALIGN - 1);
|
||||
desc = *table;
|
||||
} else {
|
||||
xlat_table = (unsigned long)mmu_l2_base +
|
||||
next_xlat * MMU32B_L2_TABLE_SIZE;
|
||||
assert(++next_xlat <= MAX_XLAT_TABLES);
|
||||
memset((char *)xlat_table, 0,
|
||||
MMU32B_L2_TABLE_SIZE);
|
||||
|
||||
desc = xlat_table | SECTION_PT_PT;
|
||||
desc |= mm->attr & MT_NS ?
|
||||
SECTION_PT_NOTSECURE : 0;
|
||||
}
|
||||
/* Recurse to fill in new table */
|
||||
mm = init_xlation_table_inner(mm, base_va,
|
||||
(unsigned long *)xlat_table,
|
||||
level + 1);
|
||||
}
|
||||
#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
|
||||
/* dump only non-lpae level 2 tables content */
|
||||
if (level == 2)
|
||||
printf("\n");
|
||||
#endif
|
||||
*table++ = desc;
|
||||
base_va += level_size;
|
||||
} while (mm->size && (base_va & level_index_mask));
|
||||
|
||||
return mm;
|
||||
}
|
||||
|
||||
void init_xlat_tables(void)
|
||||
{
|
||||
print_mmap();
|
||||
|
||||
assert(!((unsigned int)mmu_l1_base & (MMU32B_L1_TABLE_ALIGN - 1)));
|
||||
assert(!((unsigned int)mmu_l2_base & (MMU32B_L2_TABLE_ALIGN - 1)));
|
||||
|
||||
memset(mmu_l1_base, 0, MMU32B_L1_TABLE_SIZE);
|
||||
|
||||
init_xlation_table_inner(mmap, 0, (unsigned long *)mmu_l1_base, 1);
|
||||
|
||||
VERBOSE("init xlat - max_va=%p, max_pa=%llx\n",
|
||||
(void *)xlat_max_va, xlat_max_pa);
|
||||
assert(xlat_max_va <= PLAT_VIRT_ADDR_SPACE_SIZE - 1);
|
||||
assert(xlat_max_pa <= PLAT_VIRT_ADDR_SPACE_SIZE - 1);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function for enabling the MMU in Secure PL1, assuming that the
|
||||
* page-tables have already been created.
|
||||
******************************************************************************/
|
||||
void enable_mmu_svc_mon(unsigned int flags)
|
||||
{
|
||||
unsigned int prrr;
|
||||
unsigned int nmrr;
|
||||
unsigned int sctlr;
|
||||
|
||||
assert(IS_IN_SECURE());
|
||||
assert((read_sctlr() & SCTLR_M_BIT) == 0);
|
||||
|
||||
/* Enable Access flag (simplified access permissions) and TEX remap */
|
||||
write_sctlr(read_sctlr() | SCTLR_AFE_BIT | SCTLR_TRE_BIT);
|
||||
|
||||
prrr = MMU32B_PRRR_IDX(MMU32B_ATTR_DEVICE_INDEX, 1, 0) \
|
||||
| MMU32B_PRRR_IDX(MMU32B_ATTR_IWBWA_OWBWA_INDEX, 2, 1);
|
||||
nmrr = MMU32B_NMRR_IDX(MMU32B_ATTR_DEVICE_INDEX, 0, 0) \
|
||||
| MMU32B_NMRR_IDX(MMU32B_ATTR_IWBWA_OWBWA_INDEX, 1, 1);
|
||||
|
||||
prrr |= MMU32B_PRRR_NS1 | MMU32B_PRRR_DS1;
|
||||
|
||||
write_prrr(prrr);
|
||||
write_nmrr(nmrr);
|
||||
|
||||
/* Program Domain access control register: domain 0 only */
|
||||
write_dacr(DACR_DOMAIN(0, DACR_DOMAIN_PERM_CLIENT));
|
||||
|
||||
/* Invalidate TLBs at the current exception level */
|
||||
tlbiall();
|
||||
|
||||
/* set MMU base xlat table entry (use only TTBR0) */
|
||||
write_ttbr0((uint32_t)mmu_l1_base | MMU32B_DEFAULT_ATTRS);
|
||||
write_ttbr1(0);
|
||||
|
||||
/*
|
||||
* Ensure all translation table writes have drained
|
||||
* into memory, the TLB invalidation is complete,
|
||||
* and translation register writes are committed
|
||||
* before enabling the MMU
|
||||
*/
|
||||
dsb();
|
||||
isb();
|
||||
|
||||
sctlr = read_sctlr();
|
||||
sctlr |= SCTLR_M_BIT;
|
||||
#if ARMV7_SUPPORTS_VIRTUALIZATION
|
||||
sctlr |= SCTLR_WXN_BIT;
|
||||
#endif
|
||||
|
||||
if (flags & DISABLE_DCACHE)
|
||||
sctlr &= ~SCTLR_C_BIT;
|
||||
else
|
||||
sctlr |= SCTLR_C_BIT;
|
||||
|
||||
write_sctlr(sctlr);
|
||||
|
||||
/* Ensure the MMU enable takes effect immediately */
|
||||
isb();
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue