From ddf2ca03979ea9fad305b1bc59beb6e27f0e1c02 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 13 Feb 2021 19:09:29 +0100 Subject: [PATCH 01/12] feat(plat/rcar3): add optional support for gzip-compressed BL33 The BL33 size on this platform is limited to 1 MiB, add optional support for decompressing and starting gzip-compressed BL33, which may help with this size limitation. This functionality is disabled by default, set RCAR_GEN3_BL33_GZIP=1 during build to enable it. The BL33 at 0x50000000 should then be gzip compressed, however if the BL33 does not have a valid gzip header, it is copied to the correct location and started as-is, this is a fallback for legacy systems and systems which update to gzip-compressed BL33. Signed-off-by: Marek Vasut Change-Id: Id93f1c7e6f17db1ffb952ea086562993473f6efa --- plat/renesas/common/include/platform_def.h | 3 +- plat/renesas/rcar/bl2_plat_setup.c | 34 ++++++++++++++++++++-- plat/renesas/rcar/platform.mk | 12 ++++++++ 3 files changed, 46 insertions(+), 3 deletions(-) diff --git a/plat/renesas/common/include/platform_def.h b/plat/renesas/common/include/platform_def.h index 73787140b..72c768891 100644 --- a/plat/renesas/common/include/platform_def.h +++ b/plat/renesas/common/include/platform_def.h @@ -151,7 +151,8 @@ * BL33 ******************************************************************************/ #define BL33_BASE DRAM1_NS_BASE - +#define BL33_COMP_SIZE U(0x200000) +#define BL33_COMP_BASE (BL33_BASE - BL33_COMP_SIZE) /******************************************************************************* * Platform specific page table and MMU setup constants diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c index add2a4f9b..1b4a7b292 100644 --- a/plat/renesas/rcar/bl2_plat_setup.c +++ b/plat/renesas/rcar/bl2_plat_setup.c @@ -15,12 +15,16 @@ #include #include #include +#include #include #include #include #include #include #include +#if RCAR_GEN3_BL33_GZIP == 1 +#include +#endif #include "avs_driver.h" #include "boot_init_dram.h" @@ -357,16 +361,29 @@ static uint32_t is_ddr_backup_mode(void) #endif } +#if RCAR_GEN3_BL33_GZIP == 1 +void bl2_plat_preload_setup(void) +{ + image_decompress_init(BL33_COMP_BASE, BL33_COMP_SIZE, gunzip); +} +#endif + int bl2_plat_handle_pre_image_load(unsigned int image_id) { u_register_t *boot_kind = (void *) BOOT_KIND_BASE; bl_mem_params_node_t *bl_mem_params; + bl_mem_params = get_bl_mem_params_node(image_id); + +#if RCAR_GEN3_BL33_GZIP == 1 + if (image_id == BL33_IMAGE_ID) { + image_decompress_prepare(&bl_mem_params->image_info); + } +#endif + if (image_id != BL31_IMAGE_ID) return 0; - bl_mem_params = get_bl_mem_params_node(image_id); - if (is_ddr_backup_mode() == RCAR_COLD_BOOT) goto cold_boot; @@ -433,6 +450,19 @@ int bl2_plat_handle_post_image_load(unsigned int image_id) sizeof(entry_point_info_t)); break; case BL33_IMAGE_ID: +#if RCAR_GEN3_BL33_GZIP == 1 + if ((mmio_read_32(BL33_COMP_BASE) & 0xffff) == 0x8b1f) { + /* decompress gzip-compressed image */ + ret = image_decompress(&bl_mem_params->image_info); + if (ret != 0) { + return ret; + } + } else { + /* plain image, copy it in place */ + memcpy((void *)BL33_BASE, (void *)BL33_COMP_BASE, + bl_mem_params->image_info.image_size); + } +#endif memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, sizeof(entry_point_info_t)); break; diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk index 7a7a56c79..11de5594f 100644 --- a/plat/renesas/rcar/platform.mk +++ b/plat/renesas/rcar/platform.mk @@ -280,6 +280,11 @@ RCAR_SYSTEM_RESET_KEEPON_DDR := 0 endif $(eval $(call add_define,RCAR_SYSTEM_RESET_KEEPON_DDR)) +ifndef RCAR_GEN3_BL33_GZIP +RCAR_GEN3_BL33_GZIP := 0 +endif +$(eval $(call add_define,RCAR_GEN3_BL33_GZIP)) + # RCAR_SYSTEM_RESET_KEEPON_DDR requires power control of PMIC etc. # When executing SYSTEM_SUSPEND other than Salvator-X, Salvator-XS and Ebisu, # processing equivalent to that implemented in PMIC_ROHM_BD9571 is necessary. @@ -315,6 +320,13 @@ PLAT_INCLUDES += -Idrivers/renesas/common/ddr \ BL2_SOURCES += plat/renesas/rcar/bl2_plat_setup.c \ drivers/renesas/rcar/board/board.c +ifeq (${RCAR_GEN3_BL33_GZIP},1) +include lib/zlib/zlib.mk + +BL2_SOURCES += common/image_decompress.c \ + $(ZLIB_SOURCES) +endif + ifeq (${RCAR_GEN3_ULCB},1) BL31_SOURCES += drivers/renesas/rcar/cpld/ulcb_cpld.c endif From e624e98dc34c0d5b08ddd238bfa5bba0e6bd8b19 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 16 Apr 2021 21:25:27 +0200 Subject: [PATCH 02/12] refactor(plat/rcar3): factor out DT memory node generation Move the code that adds single new memory@ node into the DT fragment passed to system software into separate function. Adjust the failure message to be more specific and print the address range of node which failed to be added. No functional change. Signed-off-by: Marek Vasut Change-Id: Ie42cd7756b045271f070bca93c524fff6238f5a2 --- plat/renesas/rcar/bl2_plat_setup.c | 68 ++++++++++++++++++------------ 1 file changed, 40 insertions(+), 28 deletions(-) diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c index 1b4a7b292..ecb030ad3 100644 --- a/plat/renesas/rcar/bl2_plat_setup.c +++ b/plat/renesas/rcar/bl2_plat_setup.c @@ -565,12 +565,48 @@ static void bl2_populate_compatible_string(void *dt) } } -static void bl2_advertise_dram_entries(uint64_t dram_config[8]) +static void bl2_add_dram_entry(uint64_t start, uint64_t size) { char nodename[32] = { 0 }; - uint64_t start, size; uint64_t fdtsize; - int ret, node, chan; + int ret, node; + + fdtsize = cpu_to_fdt64(size); + + snprintf(nodename, sizeof(nodename), "memory@"); + unsigned_num_print(start, 16, nodename + strlen(nodename)); + node = ret = fdt_add_subnode(fdt, 0, nodename); + if (ret < 0) { + goto err; + } + + ret = fdt_setprop_string(fdt, node, "device_type", "memory"); + if (ret < 0) { + goto err; + } + + ret = fdt_setprop_u64(fdt, node, "reg", start); + if (ret < 0) { + goto err; + } + + ret = fdt_appendprop(fdt, node, "reg", &fdtsize, + sizeof(fdtsize)); + if (ret < 0) { + goto err; + } + + return; +err: + NOTICE("BL2: Cannot add memory node [%llx - %llx] to FDT (ret=%i)\n", + start, start + size - 1, ret); + panic(); +} + +static void bl2_advertise_dram_entries(uint64_t dram_config[8]) +{ + uint64_t start, size; + int chan; for (chan = 0; chan < 4; chan++) { start = dram_config[2 * chan]; @@ -605,32 +641,8 @@ static void bl2_advertise_dram_entries(uint64_t dram_config[8]) size -= 0x8000000; } - fdtsize = cpu_to_fdt64(size); - - snprintf(nodename, sizeof(nodename), "memory@"); - unsigned_num_print(start, 16, nodename + strlen(nodename)); - node = ret = fdt_add_subnode(fdt, 0, nodename); - if (ret < 0) - goto err; - - ret = fdt_setprop_string(fdt, node, "device_type", "memory"); - if (ret < 0) - goto err; - - ret = fdt_setprop_u64(fdt, node, "reg", start); - if (ret < 0) - goto err; - - ret = fdt_appendprop(fdt, node, "reg", &fdtsize, - sizeof(fdtsize)); - if (ret < 0) - goto err; + bl2_add_dram_entry(start, size); } - - return; -err: - NOTICE("BL2: Cannot add memory node to FDT (ret=%i)\n", ret); - panic(); } static void bl2_advertise_dram_size(uint32_t product) From 21924f2466b9b5e1243c142932e6f498da5633e9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 16 Apr 2021 21:39:36 +0200 Subject: [PATCH 03/12] fix(plat/rcar3): generate two memory nodes for larger than 2 GiB channel 0 The DRAM channel 0 memory area in 32bit space is limited to 2 GiB window. Furthermore, the first 128 MiB of this memory window are reserved and not accessible by the system software, hence the 32bit area memory node is limited to range 0x4800_0000..0xbfff_ffff. In case there are more than 2 GiB of DRAM populated in channel 0, it is necessary to generate two memory nodes, once covering the 2 GiB - 128 MiB area in the 32bit space, and another covering the rest of the memory in 64bit space. This patch implements handling of such a case. Signed-off-by: Marek Vasut Change-Id: I3495241fb938e355352e817afaca8f01d04c81d2 --- plat/renesas/rcar/bl2_plat_setup.c | 36 ++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c index ecb030ad3..b479859b0 100644 --- a/plat/renesas/rcar/bl2_plat_setup.c +++ b/plat/renesas/rcar/bl2_plat_setup.c @@ -605,7 +605,7 @@ err: static void bl2_advertise_dram_entries(uint64_t dram_config[8]) { - uint64_t start, size; + uint64_t start, size, size32; int chan; for (chan = 0; chan < 4; chan++) { @@ -634,11 +634,39 @@ static void bl2_advertise_dram_entries(uint64_t dram_config[8]) /* * Channel 0 is mapped in 32bit space and the first - * 128 MiB are reserved + * 128 MiB are reserved and the maximum size is 2GiB. */ if (chan == 0) { - start = 0x48000000; - size -= 0x8000000; + /* Limit the 32bit entry to 2 GiB - 128 MiB */ + size32 = size - 0x8000000U; + if (size32 >= 0x78000000U) { + size32 = 0x78000000U; + } + + /* Emit 32bit entry, up to 2 GiB - 128 MiB long. */ + bl2_add_dram_entry(0x48000000, size32); + + /* + * If channel 0 is less than 2 GiB long, the + * entire memory fits into the 32bit space entry, + * so move on to the next channel. + */ + if (size <= 0x80000000U) { + continue; + } + + /* + * If channel 0 is more than 2 GiB long, emit + * another entry which covers the rest of the + * memory in channel 0, in the 64bit space. + * + * Start of this new entry is at 2 GiB offset + * from the beginning of the 64bit channel 0 + * address, size is 2 GiB shorter than total + * size of the channel. + */ + start += 0x80000000U; + size -= 0x80000000U; } bl2_add_dram_entry(start, size); From 36d5645aec947ab00b925b21141e59e58e1efd8c Mon Sep 17 00:00:00 2001 From: Toshiyuki Ogasahara Date: Mon, 30 Nov 2020 20:36:09 +0900 Subject: [PATCH 04/12] fix(drivers/rcar3): emmc: remove CPG_CPGWPR redefinition emmc_registers.h contains redefinition of CPG_CPGWPR from bl2_cpg_register.h Signed-off-by: Toshiyuki Ogasahara Signed-off-by: Yoshifumi Hosoya Change-Id: Ie13590100df08f32193653e50191e66ed42d2b28 --- drivers/renesas/common/emmc/emmc_init.c | 3 ++- drivers/renesas/common/emmc/emmc_registers.h | 4 +--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/renesas/common/emmc/emmc_init.c b/drivers/renesas/common/emmc/emmc_init.c index 354aa3c82..9c2ec4752 100644 --- a/drivers/renesas/common/emmc/emmc_init.c +++ b/drivers/renesas/common/emmc/emmc_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,6 +14,7 @@ #include "emmc_registers.h" #include "emmc_def.h" #include "rcar_private.h" +#include "cpg_registers.h" st_mmc_base mmc_drv_obj; diff --git a/drivers/renesas/common/emmc/emmc_registers.h b/drivers/renesas/common/emmc/emmc_registers.h index 7fae5e406..370cc1cd1 100644 --- a/drivers/renesas/common/emmc/emmc_registers.h +++ b/drivers/renesas/common/emmc/emmc_registers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -60,8 +60,6 @@ #define CPG_SD2CKCR (CPG_BASE + 0x0268U) /* SDHI3 clock frequency control register */ #define CPG_SD3CKCR (CPG_BASE + 0x026CU) -/* CPG Write Protect Register */ -#define CPG_CPGWPR (CPG_BASE + 0x0900U) #if USE_MMC_CH == MMC_CH0 #define CPG_SDxCKCR (CPG_SD2CKCR) /* SDHI2/MMC0 */ From 0dae56bb2f0aa1f89ec98ebe3931fb19751a5c72 Mon Sep 17 00:00:00 2001 From: Toshiyuki Ogasahara Date: Mon, 30 Nov 2020 20:39:21 +0900 Subject: [PATCH 05/12] fix(drivers/rcar3): fix CPG registers redefinition This commit deletes the value of the redefined CPG register. Signed-off-by: Toshiyuki Ogasahara Signed-off-by: Yoshifumi Hosoya Change-Id: I05cf4a449ae28adb2ddd59593971a7d0cbcb21de --- drivers/renesas/common/common.c | 5 +++-- drivers/renesas/common/emmc/emmc_init.c | 6 +++--- drivers/renesas/common/emmc/emmc_registers.h | 11 ----------- drivers/renesas/common/pwrc/pwrc.c | 7 ++++--- plat/renesas/common/include/rcar_def.h | 3 +-- plat/renesas/common/include/registers/cpg_registers.h | 8 +++++++- plat/renesas/common/rcar_common.c | 7 +++---- 7 files changed, 21 insertions(+), 26 deletions(-) diff --git a/drivers/renesas/common/common.c b/drivers/renesas/common/common.c index 9b7c1eb16..a0aa4808d 100644 --- a/drivers/renesas/common/common.c +++ b/drivers/renesas/common/common.c @@ -1,11 +1,12 @@ /* - * Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include +#include "cpg_registers.h" #include "rcar_private.h" #if IMAGE_BL31 @@ -16,7 +17,7 @@ void cpg_write(uintptr_t regadr, uint32_t regval) { uint32_t value = regval; - mmio_write_32((uintptr_t) RCAR_CPGWPR, ~value); + mmio_write_32(CPG_CPGWPR, ~value); mmio_write_32(regadr, value); } diff --git a/drivers/renesas/common/emmc/emmc_init.c b/drivers/renesas/common/emmc/emmc_init.c index 9c2ec4752..c0ec600f5 100644 --- a/drivers/renesas/common/emmc/emmc_init.c +++ b/drivers/renesas/common/emmc/emmc_init.c @@ -88,11 +88,11 @@ static EMMC_ERROR_CODE emmc_dev_finalize(void) SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */ SETR_32(SD_CLK_CTRL, 0x00000000U); /* MMC clock stop */ - dataL = mmio_read_32(CPG_SMSTPCR3); + dataL = mmio_read_32(SMSTPCR3); if ((dataL & CPG_MSTP_MMC) == 0U) { dataL |= (CPG_MSTP_MMC); mmio_write_32(CPG_CPGWPR, (~dataL)); - mmio_write_32(CPG_SMSTPCR3, dataL); + mmio_write_32(SMSTPCR3, dataL); } return result; @@ -101,7 +101,7 @@ static EMMC_ERROR_CODE emmc_dev_finalize(void) static EMMC_ERROR_CODE emmc_dev_init(void) { /* Enable clock supply to eMMC. */ - mstpcr_write(CPG_SMSTPCR3, CPG_MSTPSR3, CPG_MSTP_MMC); + mstpcr_write(SMSTPCR3, CPG_MSTPSR3, CPG_MSTP_MMC); /* Set SD clock */ mmio_write_32(CPG_CPGWPR, ~((uint32_t) (BIT9 | BIT0))); /* SD phy 200MHz */ diff --git a/drivers/renesas/common/emmc/emmc_registers.h b/drivers/renesas/common/emmc/emmc_registers.h index 370cc1cd1..67d285d0a 100644 --- a/drivers/renesas/common/emmc/emmc_registers.h +++ b/drivers/renesas/common/emmc/emmc_registers.h @@ -50,17 +50,6 @@ #define BIT30 (0x40000000U) #define BIT31 (0x80000000U) -/* Clock Pulse Generator (CPG) registers */ -#define CPG_BASE (0xE6150000U) -/* Module stop status register 3 */ -#define CPG_MSTPSR3 (CPG_BASE + 0x0048U) -/* System module stop control register 3 */ -#define CPG_SMSTPCR3 (CPG_BASE + 0x013CU) -/* SDHI2 clock frequency control register */ -#define CPG_SD2CKCR (CPG_BASE + 0x0268U) -/* SDHI3 clock frequency control register */ -#define CPG_SD3CKCR (CPG_BASE + 0x026CU) - #if USE_MMC_CH == MMC_CH0 #define CPG_SDxCKCR (CPG_SD2CKCR) /* SDHI2/MMC0 */ #else /* USE_MMC_CH == MMC_CH0 */ diff --git a/drivers/renesas/common/pwrc/pwrc.c b/drivers/renesas/common/pwrc/pwrc.c index c0f015f04..3f60fe633 100644 --- a/drivers/renesas/common/pwrc/pwrc.c +++ b/drivers/renesas/common/pwrc/pwrc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,6 +20,7 @@ #include "pwrc.h" #include "rcar_def.h" #include "rcar_private.h" +#include "cpg_registers.h" /* * Someday there will be a generic power controller api. At the moment each @@ -238,7 +239,7 @@ void rcar_pwrc_cpuon(uint64_t mpidr) scu_power_up(mpidr); cpu = mpidr & MPIDR_CPU_MASK; on_data = 1 << cpu; - mmio_write_32(RCAR_CPGWPR, ~on_data); + mmio_write_32(CPG_CPGWPR, ~on_data); mmio_write_32(on_reg, on_data); mmio_write_32(res_reg, res_data & (~(1 << (3 - cpu)))); @@ -260,7 +261,7 @@ void rcar_pwrc_cpuoff(uint64_t mpidr) if (read_mpidr_el1() != mpidr) panic(); - mmio_write_32(RCAR_CPGWPR, ~CPU_PWR_OFF); + mmio_write_32(CPG_CPGWPR, ~CPU_PWR_OFF); mmio_write_32(reg + cpu * 0x0010, CPU_PWR_OFF); rcar_lock_release(); diff --git a/plat/renesas/common/include/rcar_def.h b/plat/renesas/common/include/rcar_def.h index 6c5b29561..93a65f1a4 100644 --- a/plat/renesas/common/include/rcar_def.h +++ b/plat/renesas/common/include/rcar_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -120,7 +120,6 @@ /* Timer control */ #define RCAR_CNTC_BASE U(0xE6080000) /* Reset */ -#define RCAR_CPGWPR U(0xE6150900) /* CPG write protect */ #define RCAR_MODEMR U(0xE6160060) /* Mode pin */ #define RCAR_CA57RESCNT U(0xE6160040) /* Reset control A57 */ #define RCAR_CA53RESCNT U(0xE6160044) /* Reset control A53 */ diff --git a/plat/renesas/common/include/registers/cpg_registers.h b/plat/renesas/common/include/registers/cpg_registers.h index 0d698d9c1..5d2bb9e3a 100644 --- a/plat/renesas/common/include/registers/cpg_registers.h +++ b/plat/renesas/common/include/registers/cpg_registers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,6 +16,8 @@ #define CPG_SRCR2 (CPG_BASE + 0x00B0U) /* CPG module stop status 2 */ #define CPG_MSTPSR2 (CPG_BASE + 0x0040U) +/* CPG module stop status 2 */ +#define CPG_MSTPSR3 (CPG_BASE + 0x0048U) /* CPG write protect */ #define CPG_CPGWPR (CPG_BASE + 0x0900U) /* CPG write protect control */ @@ -24,6 +26,10 @@ #define CPG_SMSTPCR9 (CPG_BASE + 0x0994U) /* CPG module stop status 9 */ #define CPG_MSTPSR9 (CPG_BASE + 0x09A4U) +/* SDHI2 clock frequency control register */ +#define CPG_SD2CKCR (CPG_BASE + 0x0268U) +/* SDHI3 clock frequency control register */ +#define CPG_SD3CKCR (CPG_BASE + 0x026CU) /* CPG (SECURITY) registers */ diff --git a/plat/renesas/common/rcar_common.c b/plat/renesas/common/rcar_common.c index dec7229b3..95e1f6158 100644 --- a/plat/renesas/common/rcar_common.c +++ b/plat/renesas/common/rcar_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2019-2021, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,9 +12,8 @@ #include #include +#include -#define CPG_BASE 0xE6150000 -#define CPG_MSTPSR3 0x0048 #define MSTP318 (1 << 18) #define MSTP319 (1 << 19) #define PMSR 0x5c @@ -31,7 +30,7 @@ static int rcar_pcie_fixup(unsigned int controller) int ret = 0; /* Test if PCIECx is enabled */ - cpg = mmio_read_32(CPG_BASE + CPG_MSTPSR3); + cpg = mmio_read_32(CPG_MSTPSR3); if (cpg & (MSTP318 << !controller)) return ret; From b757d3a1d901bee9b7ad430702575adba04889ba Mon Sep 17 00:00:00 2001 From: Toshiyuki Ogasahara Date: Mon, 30 Nov 2020 20:42:27 +0900 Subject: [PATCH 06/12] fix(drivers/rcar3): i2c_dvfs: fix I2C operation This commit fixes value to write to the ICCR register according to the hardware manual. Signed-off-by: Toshiyuki Ogasahara Signed-off-by: Yoshifumi Hosoya Change-Id: I1f612a482c012a6739e2f31db80224b222df766c --- drivers/renesas/common/iic_dvfs/iic_dvfs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/renesas/common/iic_dvfs/iic_dvfs.c b/drivers/renesas/common/iic_dvfs/iic_dvfs.c index e1c9a5bd4..bf8069728 100644 --- a/drivers/renesas/common/iic_dvfs/iic_dvfs.c +++ b/drivers/renesas/common/iic_dvfs/iic_dvfs.c @@ -517,7 +517,7 @@ RCAR_DVFS_API(send, uint8_t slave, uint8_t reg_addr, uint8_t reg_data) uint32_t err = 0U; mstpcr_write(SCMSTPCR9, CPG_MSTPSR9, CPG_BIT_SMSTPCR9_DVFS); - mmio_write_8(IIC_DVFS_REG_ICCR, 0U); + mmio_write_8(IIC_DVFS_REG_ICCR, 1U); again: switch (state) { case DVFS_START: @@ -557,7 +557,7 @@ RCAR_DVFS_API(receive, uint8_t slave, uint8_t reg, uint8_t *data) uint32_t err = 0U; mstpcr_write(SCMSTPCR9, CPG_MSTPSR9, CPG_BIT_SMSTPCR9_DVFS); - mmio_write_8(IIC_DVFS_REG_ICCR, 0U); + mmio_write_8(IIC_DVFS_REG_ICCR, 1U); again: switch (state) { case DVFS_START: From ec767c1b99675fbb50ef1b2fdb2d38e881e4789d Mon Sep 17 00:00:00 2001 From: Chiaki Fujii Date: Fri, 30 Oct 2020 10:45:18 +0900 Subject: [PATCH 07/12] fix(drivers/rcar3): ddr: update DDR setting for H3, M3, M3N [IPL/DDR] - Update H3, M3, M3N DDR setting rev.0.41. Signed-off-by: Chiaki Fujii Signed-off-by: Yoshifumi Hosoya Change-Id: Idd2fbea621365d84b566748b5b7d7fb2f0d08168 --- drivers/renesas/common/ddr/ddr_b/boot_init_dram.c | 8 +++++++- drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h | 4 ++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c b/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c index aa3bc245b..8d002deca 100644 --- a/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c +++ b/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c @@ -4147,7 +4147,13 @@ int32_t rcar_dram_init(void) } /* THCTR Bit6: PONM=0 , Bit0: THSST=0 */ - data_l = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE; + data_l = mmio_read_32(THS1_THCTR); + if (data_l & 0x00000040U) { + data_l = data_l & 0xFFFFFFBEU; + } else { + data_l = data_l | BIT(1); + } + mmio_write_32(THS1_THCTR, data_l); /* Judge product and cut */ diff --git a/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h index 56363eb99..3cb19752c 100644 --- a/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h +++ b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#define RCAR_DDR_VERSION "rev.0.40" +#define RCAR_DDR_VERSION "rev.0.41" #define DRAM_CH_CNT 0x04 #define SLICE_CNT 0x04 #define CS_CNT 0x02 From 726050b8e2d2ee2234e103e2df55f9c7f262c851 Mon Sep 17 00:00:00 2001 From: Toshiyuki Ogasahara Date: Tue, 8 Dec 2020 16:14:56 +0900 Subject: [PATCH 08/12] feat(drivers/rcar3): ddr: add function to judge a DDR rank This commit adds the function to change the settings used for DDR initialization depending on the board ID and DDR rank. Signed-off-by: Toshiyuki Ogasahara Signed-off-by: Yoshifumi Hosoya Change-Id: I94d550cea620748f5b15499fed1b791a69d61592 --- .../common/ddr/ddr_b/boot_init_dram_config.c | 45 ++++++++++++++++++- 1 file changed, 43 insertions(+), 2 deletions(-) diff --git a/drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c index 45b6b088c..bbb020086 100644 --- a/drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c +++ b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c @@ -12,6 +12,9 @@ #if (RZG_SOC == 1) #define BOARDNUM 4 #else + +#include + #define BOARDNUM 22 #endif /* RZG_SOC == 1 */ #define BOARD_JUDGE_AUTO @@ -1967,6 +1970,44 @@ static uint32_t rzg2_board_judge(void) } #endif /* RZG_SOC == 1 */ +#if (RZG_SOC == 0) && (RCAR_DRAM_LPDDR4_MEMCONF != 0) +static uint32_t ddr_rank_judge(void) +{ + uint32_t brd; + +#if (RCAR_DRAM_MEMRANK == 0) + int32_t ret; + uint32_t type = 0U; + uint32_t rev = 0U; + + brd = 99U; + ret = rcar_get_board_type(&type, &rev); + if ((ret == 0) && (rev != 0xFFU)) { + if (type == (uint32_t)BOARD_SALVATOR_XS) { + if (rev == 0x11U) { + brd = 14U; + } else { + brd = 8U; + } + } else if (type == (uint32_t)BOARD_STARTER_KIT_PRE) { + if (rev == 0x21U) { + brd = 14U; + } else { + brd = 8U; + } + } + } +#elif (RCAR_DRAM_MEMRANK == 1) + brd = 14U; +#elif (RCAR_DRAM_MEMRANK == 2) + brd = 8U; +#else +#error Invalid value was set to RCAR_DRAM_MEMRANK +#endif /* (RCAR_DRAM_MEMRANK == 0) */ + return brd; +} +#endif /* (RCAR_DRAM_LPDDR4_MEMCONF != 0) */ + static uint32_t _board_judge(void) { uint32_t brd; @@ -1985,7 +2026,7 @@ static uint32_t _board_judge(void) #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) brd = 7; #else - brd = 8; + brd = ddr_rank_judge(); #endif } } else if (prr_product == PRR_PRODUCT_M3) { @@ -2039,7 +2080,7 @@ static uint32_t _board_judge(void) #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) brd = 7; #else - brd = 8; + brd = ddr_rank_judge(); #endif } } else if (prr_product == PRR_PRODUCT_M3N) { From 4379a3e9744cf3b0844446335aca40357a889b9a Mon Sep 17 00:00:00 2001 From: Toshiyuki Ogasahara Date: Mon, 30 Nov 2020 14:52:19 +0900 Subject: [PATCH 09/12] feat(plat/rcar3): add new board revision for Salvator-XS/H3ULCB Add new board revision for 8GB 1rank of Salvator-XS/H3ULCB Signed-off-by: Toshiyuki Ogasahara Signed-off-by: Yoshifumi Hosoya Change-Id: I9e0ef7340d92de9c892fc5bd04abe24ad6ee4286 --- drivers/renesas/rcar/board/board.c | 6 +++--- plat/renesas/rcar/platform.mk | 6 ++++++ 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/renesas/rcar/board/board.c b/drivers/renesas/rcar/board/board.c index cd194ff9f..dbbaed659 100644 --- a/drivers/renesas/rcar/board/board.c +++ b/drivers/renesas/rcar/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights * reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -30,9 +30,9 @@ #define BOARD_CODE_SHIFT (0x03) #define BOARD_ID_UNKNOWN (0xFF) -#define SXS_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU } +#define SXS_ID { 0x10U, 0x11U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU } #define SX_ID { 0x10U, 0x11U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU } -#define SKP_ID { 0x10U, 0x10U, 0x20U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU } +#define SKP_ID { 0x10U, 0x10U, 0x20U, 0x21U, 0xFFU, 0xFFU, 0xFFU, 0xFFU } #define SK_ID { 0x10U, 0x30U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU } #define EB4_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU } #define EB_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU } diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk index 11de5594f..670d49931 100644 --- a/plat/renesas/rcar/platform.mk +++ b/plat/renesas/rcar/platform.mk @@ -245,6 +245,12 @@ RCAR_DRAM_LPDDR4_MEMCONF :=1 endif $(eval $(call add_define,RCAR_DRAM_LPDDR4_MEMCONF)) +# Process RCAR_DRAM_MEMRANK flag +ifndef RCAR_DRAM_MEMRANK +RCAR_DRAM_MEMRANK :=0 +endif +$(eval $(call add_define,RCAR_DRAM_MEMRANK)) + # Process RCAR_DRAM_DDR3L_MEMCONF flag ifndef RCAR_DRAM_DDR3L_MEMCONF RCAR_DRAM_DDR3L_MEMCONF :=1 From c5f5bb17abfcf6c0eeb3e6c3d70499de0bd6abc0 Mon Sep 17 00:00:00 2001 From: Toshiyuki Ogasahara Date: Tue, 8 Dec 2020 17:43:24 +0900 Subject: [PATCH 10/12] feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.0 Update the revision number in the revision management file. Signed-off-by: Toshiyuki Ogasahara Signed-off-by: Yoshifumi Hosoya Change-Id: I44b9e5a992e8a44cfeafad6d2c1a97aa59baca4e --- plat/renesas/common/include/rcar_version.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/plat/renesas/common/include/rcar_version.h b/plat/renesas/common/include/rcar_version.h index 67cbd71ab..173111df5 100644 --- a/plat/renesas/common/include/rcar_version.h +++ b/plat/renesas/common/include/rcar_version.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,7 +9,7 @@ #include -#define VERSION_OF_RENESAS "2.0.6" +#define VERSION_OF_RENESAS "3.0.0" #define VERSION_OF_RENESAS_MAXLEN 128 extern const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN]; From f95d551217a287bd909aa3c82f4ade4986ad7244 Mon Sep 17 00:00:00 2001 From: Toshiyuki Ogasahara Date: Tue, 15 Dec 2020 18:22:16 +0900 Subject: [PATCH 11/12] feat(plat/rcar3): add a DRAM size setting for M3N This commit adds a DRAM size setting when building with RCAR_DRAM_LPDDR4_MEMCONF=2 for M3N Ver.1.1 4GB DRAM. Signed-off-by: Toshiyuki Ogasahara Signed-off-by: Yoshifumi Hosoya Change-Id: Ib7fea862ab2e0bcafaf39ec030384f0fddda9b96 --- plat/renesas/rcar/bl2_plat_setup.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c index b479859b0..1d2977a93 100644 --- a/plat/renesas/rcar/bl2_plat_setup.c +++ b/plat/renesas/rcar/bl2_plat_setup.c @@ -718,8 +718,13 @@ static void bl2_advertise_dram_size(uint32_t product) break; case PRR_PRODUCT_M3N: +#if (RCAR_DRAM_LPDDR4_MEMCONF == 2) + /* 4GB(4GBx1) */ + dram_config[1] = 0x100000000ULL; +#elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) /* 2GB(1GBx2) */ dram_config[1] = 0x80000000ULL; +#endif break; case PRR_PRODUCT_V3M: From 12c75c8886a0ee69d7e279a48cbeb8d1602826b3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 10 Jul 2021 17:59:05 +0200 Subject: [PATCH 12/12] feat(plat/rcar3): emit RPC status to DT fragment if RPC unlocked In case the RCAR_RPC_HYPERFLASH_LOCKED is 0, emit DT node /soc/rpc@ee200000 with property status = "okay" into the DT fragment passed to subsequent software, to indicate the RPC is unlocked. Signed-off-by: Marek Vasut Change-Id: Id93c4573ab1c62cf13fa5a803dc5818584a2c13a --- plat/renesas/rcar/bl2_plat_setup.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c index 1d2977a93..41b2d11e7 100644 --- a/plat/renesas/rcar/bl2_plat_setup.c +++ b/plat/renesas/rcar/bl2_plat_setup.c @@ -565,6 +565,33 @@ static void bl2_populate_compatible_string(void *dt) } } +static void bl2_add_rpc_node(void) +{ +#if (RCAR_RPC_HYPERFLASH_LOCKED == 0) + int ret, node; + + node = ret = fdt_add_subnode(fdt, 0, "soc"); + if (ret < 0) { + goto err; + } + + node = ret = fdt_add_subnode(fdt, node, "rpc@ee200000"); + if (ret < 0) { + goto err; + } + + ret = fdt_setprop_string(fdt, node, "status", "okay"); + if (ret < 0) { + goto err; + } + + return; +err: + NOTICE("BL2: Cannot add RPC node to FDT (ret=%i)\n", ret); + panic(); +#endif +} + static void bl2_add_dram_entry(uint64_t start, uint64_t size) { char nodename[32] = { 0 }; @@ -1010,6 +1037,9 @@ lcm_state: /* Add platform compatible string */ bl2_populate_compatible_string(fdt); + /* Enable RPC if unlocked */ + bl2_add_rpc_node(); + /* Print DRAM layout */ bl2_advertise_dram_size(product);