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drivers/marvell/mochi: add missing stream IDs configurations
- Add setup of DMA stream IDs in AP807/AP806 drivers Change-Id: I23ffe86002db4753f812c63c31431a3d04056d07 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com>
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3 changed files with 75 additions and 5 deletions
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@ -15,8 +15,9 @@
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#include <drivers/marvell/mci.h>
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#include <drivers/marvell/mochi/ap_setup.h>
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#include <lib/mmio.h>
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#include <lib/utils_def.h>
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#include <mvebu_def.h>
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#include <a8k_plat_def.h>
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#define SMMU_sACR (MVEBU_SMMU_BASE + 0x10)
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#define SMMU_sACR_PG_64K (1 << 16)
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@ -71,6 +72,23 @@
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#define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_BASE + \
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0x4 * index)
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#define XOR_STREAM_ID_REG(ch) (MVEBU_REGS_BASE + 0x410010 + (ch) * 0x20000)
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#define XOR_STREAM_ID_MASK 0xFFFF
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#define SDIO_STREAM_ID_REG (MVEBU_RFU_BASE + 0x4600)
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#define SDIO_STREAM_ID_MASK 0xFF
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/* Do not use the default Stream ID 0 */
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#define A807_STREAM_ID_BASE (0x1)
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static uintptr_t stream_id_reg[] = {
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XOR_STREAM_ID_REG(0),
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XOR_STREAM_ID_REG(1),
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XOR_STREAM_ID_REG(2),
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XOR_STREAM_ID_REG(3),
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SDIO_STREAM_ID_REG,
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0
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};
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enum axi_attr {
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AXI_SDIO_ATTR = 0,
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AXI_DFX_ATTR,
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@ -162,6 +180,21 @@ static void mci_remap_indirect_access_base(void)
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MCI_REMAP_OFF_SHIFT);
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}
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/* Set a unique stream id for all DMA capable devices */
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static void ap807_stream_id_init(void)
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{
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uint32_t i;
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for (i = 0;
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stream_id_reg[i] != 0 && i < ARRAY_SIZE(stream_id_reg); i++) {
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uint32_t mask = stream_id_reg[i] == SDIO_STREAM_ID_REG ?
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SDIO_STREAM_ID_MASK : XOR_STREAM_ID_MASK;
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mmio_clrsetbits_32(stream_id_reg[i], mask,
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i + A807_STREAM_ID_BASE);
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}
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}
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static void ap807_axi_attr_init(void)
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{
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uint32_t index, data;
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@ -265,6 +298,9 @@ void ap_init(void)
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/* configure CCU windows */
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init_ccu(MVEBU_AP0);
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/* Set the stream IDs for DMA masters */
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ap807_stream_id_init();
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/* configure the SMMU */
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setup_smmu();
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@ -15,7 +15,7 @@
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#include <drivers/marvell/mochi/ap_setup.h>
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#include <lib/mmio.h>
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#include <mvebu_def.h>
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#include <a8k_plat_def.h>
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#define SMMU_sACR (MVEBU_SMMU_BASE + 0x10)
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#define SMMU_sACR_PG_64K (1 << 16)
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@ -67,6 +67,23 @@
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#define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_BASE + \
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0x4 * index)
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#define XOR_STREAM_ID_REG(ch) (MVEBU_REGS_BASE + 0x410010 + (ch) * 0x20000)
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#define XOR_STREAM_ID_MASK 0xFFFF
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#define SDIO_STREAM_ID_REG (MVEBU_RFU_BASE + 0x4600)
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#define SDIO_STREAM_ID_MASK 0xFF
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/* Do not use the default Stream ID 0 */
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#define A806_STREAM_ID_BASE (0x1)
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static uintptr_t stream_id_reg[] = {
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XOR_STREAM_ID_REG(0),
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XOR_STREAM_ID_REG(1),
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XOR_STREAM_ID_REG(2),
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XOR_STREAM_ID_REG(3),
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SDIO_STREAM_ID_REG,
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0
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};
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enum axi_attr {
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AXI_SDIO_ATTR = 0,
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AXI_DFX_ATTR,
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@ -158,6 +175,20 @@ static void mci_remap_indirect_access_base(void)
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MCI_REMAP_OFF_SHIFT);
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}
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/* Set a unique stream id for all DMA capable devices */
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static void ap806_stream_id_init(void)
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{
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int i;
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for (i = 0; stream_id_reg[i] != 0; i++) {
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uint32_t mask = stream_id_reg[i] == SDIO_STREAM_ID_REG ?
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SDIO_STREAM_ID_MASK : XOR_STREAM_ID_MASK;
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mmio_clrsetbits_32(stream_id_reg[i], mask,
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i + A806_STREAM_ID_BASE);
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}
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}
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static void apn806_axi_attr_init(void)
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{
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uint32_t index, data;
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@ -236,6 +267,9 @@ void ap_init(void)
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/* configure DSS */
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dss_setup();
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/* Set the stream IDs for DMA masters */
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ap806_stream_id_init();
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/* configure the SMMU */
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setup_smmu();
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@ -136,7 +136,7 @@ enum axi_attr {
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#define USB3H_1_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x10)
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#define SATA_0_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x14)
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#define SATA_1_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x18)
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#define SDIO_0_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x28)
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#define SDIO_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x28)
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#define CP_DMA_0_STREAM_ID_REG (0x6B0010)
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#define CP_DMA_1_STREAM_ID_REG (0x6D0010)
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@ -144,14 +144,14 @@ enum axi_attr {
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/* We allocate IDs 128-255 for PCIe */
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#define MAX_STREAM_ID (0x80)
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uintptr_t stream_id_reg[] = {
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static uintptr_t stream_id_reg[] = {
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USB3H_0_STREAM_ID_REG,
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USB3H_1_STREAM_ID_REG,
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CP_DMA_0_STREAM_ID_REG,
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CP_DMA_1_STREAM_ID_REG,
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SATA_0_STREAM_ID_REG,
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SATA_1_STREAM_ID_REG,
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SDIO_0_STREAM_ID_REG,
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SDIO_STREAM_ID_REG,
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0
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};
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