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drivers/marvell/mochi: add missing stream IDs configurations

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- Add setup of DMA stream IDs in AP807/AP806 drivers

Change-Id: I23ffe86002db4753f812c63c31431a3d04056d07
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
This commit is contained in:
Konstantin Porotchkin 2020-10-19 11:28:54 +03:00
parent 57660d9d79
commit c82cf21d6e
3 changed files with 75 additions and 5 deletions
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38
drivers/marvell/mochi/ap807_setup.c
View file

@ -15,8 +15,9 @@
#include <drivers/marvell/mci.h> #include <drivers/marvell/mci.h>
#include <drivers/marvell/mochi/ap_setup.h> #include <drivers/marvell/mochi/ap_setup.h>
#include <lib/mmio.h> #include <lib/mmio.h>
#include <lib/utils_def.h>
#include <mvebu_def.h> #include <a8k_plat_def.h>
#define SMMU_sACR (MVEBU_SMMU_BASE + 0x10) #define SMMU_sACR (MVEBU_SMMU_BASE + 0x10)
#define SMMU_sACR_PG_64K (1 << 16) #define SMMU_sACR_PG_64K (1 << 16)
@ -71,6 +72,23 @@
#define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_BASE + \ #define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_BASE + \
0x4 * index) 0x4 * index)
#define XOR_STREAM_ID_REG(ch) (MVEBU_REGS_BASE + 0x410010 + (ch) * 0x20000)
#define XOR_STREAM_ID_MASK 0xFFFF
#define SDIO_STREAM_ID_REG (MVEBU_RFU_BASE + 0x4600)
#define SDIO_STREAM_ID_MASK 0xFF
/* Do not use the default Stream ID 0 */
#define A807_STREAM_ID_BASE (0x1)
static uintptr_t stream_id_reg[] = {
XOR_STREAM_ID_REG(0),
XOR_STREAM_ID_REG(1),
XOR_STREAM_ID_REG(2),
XOR_STREAM_ID_REG(3),
SDIO_STREAM_ID_REG,
0
};
enum axi_attr { enum axi_attr {
AXI_SDIO_ATTR = 0, AXI_SDIO_ATTR = 0,
AXI_DFX_ATTR, AXI_DFX_ATTR,
@ -162,6 +180,21 @@ static void mci_remap_indirect_access_base(void)
MCI_REMAP_OFF_SHIFT); MCI_REMAP_OFF_SHIFT);
} }
/* Set a unique stream id for all DMA capable devices */
static void ap807_stream_id_init(void)
{
uint32_t i;
for (i = 0;
stream_id_reg[i] != 0 && i < ARRAY_SIZE(stream_id_reg); i++) {
uint32_t mask = stream_id_reg[i] == SDIO_STREAM_ID_REG ?
SDIO_STREAM_ID_MASK : XOR_STREAM_ID_MASK;
mmio_clrsetbits_32(stream_id_reg[i], mask,
i + A807_STREAM_ID_BASE);
}
}
static void ap807_axi_attr_init(void) static void ap807_axi_attr_init(void)
{ {
uint32_t index, data; uint32_t index, data;
@ -265,6 +298,9 @@ void ap_init(void)
/* configure CCU windows */ /* configure CCU windows */
init_ccu(MVEBU_AP0); init_ccu(MVEBU_AP0);
/* Set the stream IDs for DMA masters */
ap807_stream_id_init();
/* configure the SMMU */ /* configure the SMMU */
setup_smmu(); setup_smmu();

36
drivers/marvell/mochi/apn806_setup.c
View file

@ -15,7 +15,7 @@
#include <drivers/marvell/mochi/ap_setup.h> #include <drivers/marvell/mochi/ap_setup.h>
#include <lib/mmio.h> #include <lib/mmio.h>
#include <mvebu_def.h> #include <a8k_plat_def.h>
#define SMMU_sACR (MVEBU_SMMU_BASE + 0x10) #define SMMU_sACR (MVEBU_SMMU_BASE + 0x10)
#define SMMU_sACR_PG_64K (1 << 16) #define SMMU_sACR_PG_64K (1 << 16)
@ -67,6 +67,23 @@
#define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_BASE + \ #define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_BASE + \
0x4 * index) 0x4 * index)
#define XOR_STREAM_ID_REG(ch) (MVEBU_REGS_BASE + 0x410010 + (ch) * 0x20000)
#define XOR_STREAM_ID_MASK 0xFFFF
#define SDIO_STREAM_ID_REG (MVEBU_RFU_BASE + 0x4600)
#define SDIO_STREAM_ID_MASK 0xFF
/* Do not use the default Stream ID 0 */
#define A806_STREAM_ID_BASE (0x1)
static uintptr_t stream_id_reg[] = {
XOR_STREAM_ID_REG(0),
XOR_STREAM_ID_REG(1),
XOR_STREAM_ID_REG(2),
XOR_STREAM_ID_REG(3),
SDIO_STREAM_ID_REG,
0
};
enum axi_attr { enum axi_attr {
AXI_SDIO_ATTR = 0, AXI_SDIO_ATTR = 0,
AXI_DFX_ATTR, AXI_DFX_ATTR,
@ -158,6 +175,20 @@ static void mci_remap_indirect_access_base(void)
MCI_REMAP_OFF_SHIFT); MCI_REMAP_OFF_SHIFT);
} }
/* Set a unique stream id for all DMA capable devices */
static void ap806_stream_id_init(void)
{
int i;
for (i = 0; stream_id_reg[i] != 0; i++) {
uint32_t mask = stream_id_reg[i] == SDIO_STREAM_ID_REG ?
SDIO_STREAM_ID_MASK : XOR_STREAM_ID_MASK;
mmio_clrsetbits_32(stream_id_reg[i], mask,
i + A806_STREAM_ID_BASE);
}
}
static void apn806_axi_attr_init(void) static void apn806_axi_attr_init(void)
{ {
uint32_t index, data; uint32_t index, data;
@ -236,6 +267,9 @@ void ap_init(void)
/* configure DSS */ /* configure DSS */
dss_setup(); dss_setup();
/* Set the stream IDs for DMA masters */
ap806_stream_id_init();
/* configure the SMMU */ /* configure the SMMU */
setup_smmu(); setup_smmu();

6
drivers/marvell/mochi/cp110_setup.c
View file

@ -136,7 +136,7 @@ enum axi_attr {
#define USB3H_1_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x10) #define USB3H_1_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x10)
#define SATA_0_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x14) #define SATA_0_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x14)
#define SATA_1_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x18) #define SATA_1_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x18)
#define SDIO_0_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x28) #define SDIO_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x28)
#define CP_DMA_0_STREAM_ID_REG (0x6B0010) #define CP_DMA_0_STREAM_ID_REG (0x6B0010)
#define CP_DMA_1_STREAM_ID_REG (0x6D0010) #define CP_DMA_1_STREAM_ID_REG (0x6D0010)
@ -144,14 +144,14 @@ enum axi_attr {
/* We allocate IDs 128-255 for PCIe */ /* We allocate IDs 128-255 for PCIe */
#define MAX_STREAM_ID (0x80) #define MAX_STREAM_ID (0x80)
uintptr_t stream_id_reg[] = { static uintptr_t stream_id_reg[] = {
USB3H_0_STREAM_ID_REG, USB3H_0_STREAM_ID_REG,
USB3H_1_STREAM_ID_REG, USB3H_1_STREAM_ID_REG,
CP_DMA_0_STREAM_ID_REG, CP_DMA_0_STREAM_ID_REG,
CP_DMA_1_STREAM_ID_REG, CP_DMA_1_STREAM_ID_REG,
SATA_0_STREAM_ID_REG, SATA_0_STREAM_ID_REG,
SATA_1_STREAM_ID_REG, SATA_1_STREAM_ID_REG,
SDIO_0_STREAM_ID_REG, SDIO_STREAM_ID_REG,
0 0
}; };