fix(psci): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement body within the curly braces.

Change-Id: I8b656f59b445e914dd3f47e3dde83735481a3640
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

lib/psci/psci_common.c

@@ -138,9 +138,9 @@ int psci_validate_power_state(unsigned int power_state,
 			      psci_power_state_t *state_info)
 {
 	/* Check SBZ bits in power state are zero */
-	if (psci_check_power_state(power_state) != 0U)
+	if (psci_check_power_state(power_state) != 0U) {
 		return PSCI_E_INVALID_PARAMS;
-
+	}
 	assert(psci_plat_pm_ops->validate_power_state != NULL);
 
 	/* Validate the power_state using platform pm_ops */
@@ -439,8 +439,9 @@ void psci_get_target_local_pwr_states(unsigned int cpu_idx, unsigned int end_pwr
 	}
 
 	/* Set the the higher levels to RUN */
-	for (; lvl <= PLAT_MAX_PWR_LVL; lvl++)
+	for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) {
 		target_state->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN;
+	}
 }
 
 /******************************************************************************
@@ -574,8 +575,9 @@ void psci_do_state_coordination(unsigned int cpu_idx, unsigned int end_pwrlvl,
 		state_info->pwr_domain_state[lvl] = target_state;
 
 		/* Break early if the negotiated target power state is RUN */
-		if (is_local_state_run(state_info->pwr_domain_state[lvl]) != 0)
+		if (is_local_state_run(state_info->pwr_domain_state[lvl]) != 0) {
 			break;
+		}
 
 		parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
 	}
@@ -757,8 +759,9 @@ unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info)
 	int i;
 
 	for (i = (int) PLAT_MAX_PWR_LVL; i >= (int) PSCI_CPU_PWR_LVL; i--) {
-		if (is_local_state_off(state_info->pwr_domain_state[i]) != 0)
+		if (is_local_state_off(state_info->pwr_domain_state[i]) != 0) {
 			return (unsigned int) i;
+		}
 	}
 
 	return PSCI_INVALID_PWR_LVL;
@@ -942,8 +945,9 @@ int psci_validate_entry_point(entry_point_info_t *ep,
 	/* Validate the entrypoint using platform psci_ops */
 	if (psci_plat_pm_ops->validate_ns_entrypoint != NULL) {
 		rc = psci_plat_pm_ops->validate_ns_entrypoint(entrypoint);
-		if (rc != PSCI_E_SUCCESS)
+		if (rc != PSCI_E_SUCCESS) {
 			return PSCI_E_INVALID_ADDRESS;
+		}
 	}
 
 	/*
@@ -1017,9 +1021,9 @@ void psci_warmboot_entrypoint(void)
 	 * of power management handler and perform the generic, architecture
 	 * and platform specific handling.
 	 */
-	if (psci_get_aff_info_state() == AFF_STATE_ON_PENDING)
+	if (psci_get_aff_info_state() == AFF_STATE_ON_PENDING) {
 		psci_cpu_on_finish(cpu_idx, &state_info);
-	else {
+	} else {
 		unsigned int max_off_lvl = psci_find_max_off_lvl(&state_info);
 
 		assert(max_off_lvl != PSCI_INVALID_PWR_LVL);

lib/psci/psci_main.c

@@ -31,13 +31,15 @@ int psci_cpu_on(u_register_t target_cpu,
 	entry_point_info_t ep;
 
 	/* Validate the target CPU */
-	if (!is_valid_mpidr(target_cpu))
+	if (!is_valid_mpidr(target_cpu)) {
 		return PSCI_E_INVALID_PARAMS;
+	}
 
 	/* Validate the entry point and get the entry_point_info */
 	rc = psci_validate_entry_point(&ep, entrypoint, context_id);
-	if (rc != PSCI_E_SUCCESS)
+	if (rc != PSCI_E_SUCCESS) {
 		return rc;
+	}
 
 	/*
 	 * To turn this cpu on, specify which power
@@ -102,8 +104,9 @@ int psci_cpu_suspend(unsigned int power_state,
 
 	/* Fast path for CPU standby.*/
 	if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) {
-		if  (psci_plat_pm_ops->cpu_standby == NULL)
+		if  (psci_plat_pm_ops->cpu_standby == NULL) {
 			return PSCI_E_INVALID_PARAMS;
+		}
 
 		/*
 		 * Set the state of the CPU power domain to the platform
@@ -171,8 +174,9 @@ int psci_cpu_suspend(unsigned int power_state,
 	 */
 	if (is_power_down_state != 0U) {
 		rc = psci_validate_entry_point(&ep, entrypoint, context_id);
-		if (rc != PSCI_E_SUCCESS)
+		if (rc != PSCI_E_SUCCESS) {
 			return rc;
+		}
 	}
 
 	/*
@@ -199,13 +203,15 @@ int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id)
 	unsigned int cpu_idx = plat_my_core_pos();
 
 	/* Check if the current CPU is the last ON CPU in the system */
-	if (!psci_is_last_on_cpu(cpu_idx))
+	if (!psci_is_last_on_cpu(cpu_idx)) {
 		return PSCI_E_DENIED;
+	}
 
 	/* Validate the entry point and get the entry_point_info */
 	rc = psci_validate_entry_point(&ep, entrypoint, context_id);
-	if (rc != PSCI_E_SUCCESS)
+	if (rc != PSCI_E_SUCCESS) {
 		return rc;
+	}
 
 	/* Query the psci_power_state for system suspend */
 	psci_query_sys_suspend_pwrstate(&state_info);
@@ -214,9 +220,9 @@ int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id)
 	 * Check if platform allows suspend to Highest power level
 	 * (System level)
 	 */
-	if (psci_find_target_suspend_lvl(&state_info) < PLAT_MAX_PWR_LVL)
+	if (psci_find_target_suspend_lvl(&state_info) < PLAT_MAX_PWR_LVL) {
 		return PSCI_E_DENIED;
-
+	}
 	/* Ensure that the psci_power_state makes sense */
 	assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN)
 						== PSCI_E_SUCCESS);
@@ -264,13 +270,14 @@ int psci_affinity_info(u_register_t target_affinity,
 	unsigned int target_idx;
 
 	/* Validate the target affinity */
-	if (!is_valid_mpidr(target_affinity))
+	if (!is_valid_mpidr(target_affinity)) {
 		return PSCI_E_INVALID_PARAMS;
+	}
 
 	/* We dont support level higher than PSCI_CPU_PWR_LVL */
-	if (lowest_affinity_level > PSCI_CPU_PWR_LVL)
+	if (lowest_affinity_level > PSCI_CPU_PWR_LVL) {
 		return PSCI_E_INVALID_PARAMS;
-
+	}
 	/* Calculate the cpu index of the target */
 	target_idx = (unsigned int) plat_core_pos_by_mpidr(target_affinity);
 
@@ -305,20 +312,23 @@ int psci_migrate(u_register_t target_cpu)
 		return PSCI_E_INVALID_PARAMS;
 
 	rc = psci_spd_migrate_info(&resident_cpu_mpidr);
-	if (rc != PSCI_TOS_UP_MIG_CAP)
+	if (rc != PSCI_TOS_UP_MIG_CAP) {
 		return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ?
 			  PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED;
+	}
 
 	/*
 	 * Migrate should only be invoked on the CPU where
 	 * the Secure OS is resident.
 	 */
-	if (resident_cpu_mpidr != read_mpidr_el1())
+	if (resident_cpu_mpidr != read_mpidr_el1()) {
 		return PSCI_E_NOT_PRESENT;
+	}
 
 	/* Check the validity of the specified target cpu */
-	if (!is_valid_mpidr(target_cpu))
+	if (!is_valid_mpidr(target_cpu)) {
 		return PSCI_E_INVALID_PARAMS;
+	}
 
 	assert((psci_spd_pm != NULL) && (psci_spd_pm->svc_migrate != NULL));
 
@@ -380,23 +390,23 @@ int psci_features(unsigned int psci_fid)
 {
 	unsigned int local_caps = psci_caps;
 
-	if (psci_fid == SMCCC_VERSION)
+	if (psci_fid == SMCCC_VERSION) {
 		return PSCI_E_SUCCESS;
-
+	}
 	/* Check if it is a 64 bit function */
-	if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64)
+	if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64) {
 		local_caps &= PSCI_CAP_64BIT_MASK;
-
+	}
 	/* Check for invalid fid */
 	if (!(is_std_svc_call(psci_fid) && is_valid_fast_smc(psci_fid)
-			&& is_psci_fid(psci_fid)))
+			&& is_psci_fid(psci_fid))) {
 		return PSCI_E_NOT_SUPPORTED;
-
+	}
 
 	/* Check if the psci fid is supported or not */
-	if ((local_caps & define_psci_cap(psci_fid)) == 0U)
+	if ((local_caps & define_psci_cap(psci_fid)) == 0U) {
 		return PSCI_E_NOT_SUPPORTED;
-
+	}
 	/* Format the feature flags */
 	if ((psci_fid == PSCI_CPU_SUSPEND_AARCH32) ||
 	    (psci_fid == PSCI_CPU_SUSPEND_AARCH64)) {
@@ -458,12 +468,14 @@ u_register_t psci_smc_handler(uint32_t smc_fid,
 {
 	u_register_t ret;
 
-	if (is_caller_secure(flags))
+	if (is_caller_secure(flags)) {
 		return (u_register_t)SMC_UNK;
+	}
 
 	/* Check the fid against the capabilities */
-	if ((psci_caps & define_psci_cap(smc_fid)) == 0U)
+	if ((psci_caps & define_psci_cap(smc_fid)) == 0U) {
 		return (u_register_t)SMC_UNK;
+	}
 
 	if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) {
 		/* 32-bit PSCI function, clear top parameter bits */

lib/psci/psci_on.c

@@ -100,8 +100,9 @@ int psci_cpu_on_start(u_register_t target_cpu,
 	 * to let it do any bookeeping. If the handler encounters an error, it's
 	 * expected to assert within
 	 */
-	if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_on != NULL))
+	if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_on != NULL)) {
 		psci_spd_pm->svc_on(target_cpu);
+	}
 
 	/*
 	 * Set the Affinity info state of the target cpu to ON_PENDING.
@@ -140,10 +141,10 @@ int psci_cpu_on_start(u_register_t target_cpu,
 	rc = psci_plat_pm_ops->pwr_domain_on(target_cpu);
 	assert((rc == PSCI_E_SUCCESS) || (rc == PSCI_E_INTERN_FAIL));
 
-	if (rc == PSCI_E_SUCCESS)
+	if (rc == PSCI_E_SUCCESS) {
 		/* Store the re-entry information for the non-secure world. */
 		cm_init_context_by_index(target_idx, ep);
-	else {
+	} else {
 		/* Restore the state on error. */
 		psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_OFF);
 		flush_cpu_data_by_index(target_idx,
@@ -182,9 +183,9 @@ void psci_cpu_on_finish(unsigned int cpu_idx, const psci_power_state_t *state_in
 	 * can only be done with the cpu and the cluster guaranteed to
 	 * be coherent.
 	 */
-	if (psci_plat_pm_ops->pwr_domain_on_finish_late != NULL)
+	if (psci_plat_pm_ops->pwr_domain_on_finish_late != NULL) {
 		psci_plat_pm_ops->pwr_domain_on_finish_late(state_info);
-
+	}
 	/*
 	 * All the platform specific actions for turning this cpu
 	 * on have completed. Perform enough arch.initialization
@@ -209,9 +210,9 @@ void psci_cpu_on_finish(unsigned int cpu_idx, const psci_power_state_t *state_in
 	 * Dispatcher to let it do any bookeeping. If the handler encounters an
 	 * error, it's expected to assert within
 	 */
-	if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_on_finish != NULL))
+	if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_on_finish != NULL)) {
 		psci_spd_pm->svc_on_finish(0);
-
+	}
 	PUBLISH_EVENT(psci_cpu_on_finish);
 
 	/* Populate the mpidr field within the cpu node array */

lib/psci/psci_setup.c

@@ -244,35 +244,44 @@ int __init psci_setup(const psci_lib_args_t *lib_args)
 	/* Initialize the psci capability */
 	psci_caps = PSCI_GENERIC_CAP;
 
-	if (psci_plat_pm_ops->pwr_domain_off != NULL)
+	if (psci_plat_pm_ops->pwr_domain_off != NULL) {
 		psci_caps |=  define_psci_cap(PSCI_CPU_OFF);
+	}
 	if ((psci_plat_pm_ops->pwr_domain_on != NULL) &&
-	    (psci_plat_pm_ops->pwr_domain_on_finish != NULL))
+	    (psci_plat_pm_ops->pwr_domain_on_finish != NULL)) {
 		psci_caps |=  define_psci_cap(PSCI_CPU_ON_AARCH64);
+	}
 	if ((psci_plat_pm_ops->pwr_domain_suspend != NULL) &&
 	    (psci_plat_pm_ops->pwr_domain_suspend_finish != NULL)) {
-		if (psci_plat_pm_ops->validate_power_state != NULL)
+		if (psci_plat_pm_ops->validate_power_state != NULL) {
 			psci_caps |=  define_psci_cap(PSCI_CPU_SUSPEND_AARCH64);
-		if (psci_plat_pm_ops->get_sys_suspend_power_state != NULL)
+		}
+		if (psci_plat_pm_ops->get_sys_suspend_power_state != NULL) {
 			psci_caps |=  define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64);
+		}
 #if PSCI_OS_INIT_MODE
 		psci_caps |= define_psci_cap(PSCI_SET_SUSPEND_MODE);
 #endif
 	}
-	if (psci_plat_pm_ops->system_off != NULL)
+	if (psci_plat_pm_ops->system_off != NULL) {
 		psci_caps |=  define_psci_cap(PSCI_SYSTEM_OFF);
-	if (psci_plat_pm_ops->system_reset != NULL)
+	}
+	if (psci_plat_pm_ops->system_reset != NULL) {
 		psci_caps |=  define_psci_cap(PSCI_SYSTEM_RESET);
-	if (psci_plat_pm_ops->get_node_hw_state != NULL)
+	}
+	if (psci_plat_pm_ops->get_node_hw_state != NULL) {
 		psci_caps |= define_psci_cap(PSCI_NODE_HW_STATE_AARCH64);
+	}
 	if ((psci_plat_pm_ops->read_mem_protect != NULL) &&
-			(psci_plat_pm_ops->write_mem_protect != NULL))
+			(psci_plat_pm_ops->write_mem_protect != NULL)) {
 		psci_caps |= define_psci_cap(PSCI_MEM_PROTECT);
-	if (psci_plat_pm_ops->mem_protect_chk != NULL)
+	}
+	if (psci_plat_pm_ops->mem_protect_chk != NULL) {
 		psci_caps |= define_psci_cap(PSCI_MEM_CHK_RANGE_AARCH64);
-	if (psci_plat_pm_ops->system_reset2 != NULL)
+	}
+	if (psci_plat_pm_ops->system_reset2 != NULL) {
 		psci_caps |= define_psci_cap(PSCI_SYSTEM_RESET2_AARCH64);
-
+	}
 #if ENABLE_PSCI_STAT
 	psci_caps |=  define_psci_cap(PSCI_STAT_RESIDENCY_AARCH64);
 	psci_caps |=  define_psci_cap(PSCI_STAT_COUNT_AARCH64);

lib/psci/psci_system_off.c

@@ -65,8 +65,9 @@ u_register_t psci_system_reset2(uint32_t reset_type, u_register_t cookie)
 		/*
 		 * Only WARM_RESET is allowed for architectural type resets.
 		 */
-		if (reset_type != PSCI_RESET2_SYSTEM_WARM_RESET)
+		if (reset_type != PSCI_RESET2_SYSTEM_WARM_RESET) {
 			return (u_register_t) PSCI_E_INVALID_PARAMS;
+		}
 		if ((psci_plat_pm_ops->write_mem_protect != NULL) &&
 		    (psci_plat_pm_ops->write_mem_protect(0) < 0)) {
 			return (u_register_t) PSCI_E_NOT_SUPPORTED;