From c62d9c7d27cfe99e7b0fcb0630ccff7c067b43cf Mon Sep 17 00:00:00 2001
From: Govindraj Raja <govindraj.raja@arm.com>
Date: Thu, 15 Jun 2023 15:32:41 -0500
Subject: [PATCH] refactor(cpus): convert the Cortex-A76AE to use the errata
 framework

Testing:
  - Manual comparison of disassembly with and without conversion.
  - Using the test script in gerrit - 19136
  - Building with errata and stepping through from ArmDS and running tftf.

Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Change-Id: I1936ab6aaef803f653e79f5c6b590a59b34a8ed1
---
 lib/cpus/aarch64/cortex_a76ae.S | 50 +++++++--------------------------
 1 file changed, 10 insertions(+), 40 deletions(-)

diff --git a/lib/cpus/aarch64/cortex_a76ae.S b/lib/cpus/aarch64/cortex_a76ae.S
index 5c19548c8..f98bb44eb 100644
--- a/lib/cpus/aarch64/cortex_a76ae.S
+++ b/lib/cpus/aarch64/cortex_a76ae.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -25,22 +25,10 @@
 	wa_cve_2022_23960_bhb_vector_table CORTEX_A76AE_BHB_LOOP_COUNT, cortex_a76ae
 #endif /* WORKAROUND_CVE_2022_23960 */
 
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
-	mov	x0, #ERRATA_APPLIES
-#else
-	mov	x0, #ERRATA_MISSING
-#endif /* WORKAROUND_CVE_2022_23960 */
-	ret
-endfunc check_errata_cve_2022_23960
+check_erratum_chosen cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 
-	/* --------------------------------------------
-	 * The CPU Ops reset function for Cortex-A76AE.
-	 * Shall clobber: x0-x19
-	 * --------------------------------------------
-	 */
-func cortex_a76ae_reset_func
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
+workaround_reset_start cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
 	/*
 	 * The Cortex-A76ae generic vectors are overridden to apply errata
 	 * mitigation on exception entry from lower ELs.
@@ -48,10 +36,13 @@ func cortex_a76ae_reset_func
 	adr	x0, wa_cve_vbar_cortex_a76ae
 	msr	vbar_el3, x0
 	isb
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a76ae, CVE(2022, 23960)
 
-	ret
-endfunc cortex_a76ae_reset_func
+cpu_reset_func_start cortex_a76ae
+cpu_reset_func_end cortex_a76ae
+
+errata_report_shim cortex_a76ae
 
 	/* ----------------------------------------------------
 	 * HW will do the cache maintenance while powering down
@@ -69,27 +60,6 @@ func cortex_a76ae_core_pwr_dwn
 	ret
 endfunc cortex_a76ae_core_pwr_dwn
 
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex-A76AE. Must follow AAPCS.
- */
-func cortex_a76ae_errata_report
-	stp	x8, x30, [sp, #-16]!
-
-	bl	cpu_get_rev_var
-	mov	x8, x0
-
-	/*
-	 * Report all errata. The revision-variant information is passed to
-	 * checking functions of each errata.
-	 */
-	report_errata WORKAROUND_CVE_2022_23960, cortex_a76ae, cve_2022_23960
-
-	ldp	x8, x30, [sp], #16
-	ret
-endfunc cortex_a76ae_errata_report
-#endif	/* REPORT_ERRATA */
-
 	/* ---------------------------------------------
 	 * This function provides cortex_a76ae specific
 	 * register information for crash reporting.