From 3a580e9e472a5506da82227e809e0bd472dea1b1 Mon Sep 17 00:00:00 2001
From: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Date: Tue, 11 Jun 2024 18:39:58 +0300
Subject: [PATCH 1/2] feat(nxp-drivers): add clock skeleton for s32cc

The S32CC is an umbrella for S32G2, S32G3 and S32R45 SoCs; therefore,
this clock driver will be used for all of these families.

Change-Id: Iede5371b212b67cf494a033c62fbfdcbe9b1a879
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
---
 changelog.yaml                        |  3 ++
 docs/about/maintainers.rst            |  1 +
 drivers/nxp/clk/s32cc/s32cc_clk.mk    | 12 ++++++
 drivers/nxp/clk/s32cc/s32cc_clk_drv.c | 59 +++++++++++++++++++++++++++
 drivers/nxp/drivers.mk                |  4 ++
 5 files changed, 79 insertions(+)
 create mode 100644 drivers/nxp/clk/s32cc/s32cc_clk.mk
 create mode 100644 drivers/nxp/clk/s32cc/s32cc_clk_drv.c

diff --git a/changelog.yaml b/changelog.yaml
index fd2a8ecc2..4d84fb704 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -1146,6 +1146,9 @@ subsections:
           - title: TRDC
             scope: imx-trdc
 
+          - title: Clock
+            scope: nxp-clk
+
       - title: Renesas
         scope: renesas-drivers
 
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 85cc61212..cbed72f34 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -767,6 +767,7 @@ NXP SoC Part S32G274A and its platform port
 :|M|: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
 :|G|: `gprocopciucnxp`_
 :|F|: docs/plat/s32g274a.rst
+:|F|: drivers/nxp/clk/s32cc
 :|F|: drivers/nxp/console/linflex_console.S
 :|F|: include/drivers/nxp/console/linflex.h
 :|F|: plat/nxp/s32
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk.mk b/drivers/nxp/clk/s32cc/s32cc_clk.mk
new file mode 100644
index 000000000..d1f940ac4
--- /dev/null
+++ b/drivers/nxp/clk/s32cc/s32cc_clk.mk
@@ -0,0 +1,12 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+CLK_SOURCES		:= \
+	${PLAT_DRIVERS_PATH}/clk/s32cc/s32cc_clk_drv.c \
+
+ifeq (${BL_COMM_CLK_NEEDED},yes)
+BL2_SOURCES		+= ${CLK_SOURCES}
+endif
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
new file mode 100644
index 000000000..845300028
--- /dev/null
+++ b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <errno.h>
+
+#include <drivers/clk.h>
+
+static int s32cc_clk_enable(unsigned long id)
+{
+	return -ENOTSUP;
+}
+
+static void s32cc_clk_disable(unsigned long id)
+{
+}
+
+static bool s32cc_clk_is_enabled(unsigned long id)
+{
+	return false;
+}
+
+static unsigned long s32cc_clk_get_rate(unsigned long id)
+{
+	return 0;
+}
+
+static int s32cc_clk_set_rate(unsigned long id, unsigned long rate,
+			      unsigned long *orate)
+{
+	return -ENOTSUP;
+}
+
+static int s32cc_clk_get_parent(unsigned long id)
+{
+	return -ENOTSUP;
+}
+
+static int s32cc_clk_set_parent(unsigned long id, unsigned long parent_id)
+{
+	return -ENOTSUP;
+}
+
+void s32cc_clk_register_drv(void)
+{
+	static const struct clk_ops s32cc_clk_ops = {
+		.enable		= s32cc_clk_enable,
+		.disable	= s32cc_clk_disable,
+		.is_enabled	= s32cc_clk_is_enabled,
+		.get_rate	= s32cc_clk_get_rate,
+		.set_rate	= s32cc_clk_set_rate,
+		.get_parent	= s32cc_clk_get_parent,
+		.set_parent	= s32cc_clk_set_parent,
+	};
+
+	clk_register(&s32cc_clk_ops);
+}
+
diff --git a/drivers/nxp/drivers.mk b/drivers/nxp/drivers.mk
index d77e98549..761571d3a 100644
--- a/drivers/nxp/drivers.mk
+++ b/drivers/nxp/drivers.mk
@@ -97,3 +97,7 @@ endif
 ifeq (${IFC_NAND_NEEDED},yes)
 include ${PLAT_DRIVERS_PATH}/ifc/nand/ifc_nand.mk
 endif
+
+ifeq (${CLK_NEEDED},yes)
+include ${PLAT_DRIVERS_PATH}/clk/s32cc/s32cc_clk.mk
+endif

From f1e4ac56b53029e67b2cb626b637a4bfe4904866 Mon Sep 17 00:00:00 2001
From: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Date: Tue, 11 Jun 2024 18:45:33 +0300
Subject: [PATCH 2/2] feat(s32g274a): use s32cc clock driver

To enable early clocks, such as A53, XBAR, and others, the clock driver
compilation should be included as part of the BL2 stage.

Change-Id: I17ba195d8c3cf3f91bd333a00d4a4af2f1f472b7
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
---
 plat/nxp/s32/s32g274ardb2/platform.mk | 1 +
 1 file changed, 1 insertion(+)

diff --git a/plat/nxp/s32/s32g274ardb2/platform.mk b/plat/nxp/s32/s32g274ardb2/platform.mk
index ee1507e5d..316ed2cf3 100644
--- a/plat/nxp/s32/s32g274ardb2/platform.mk
+++ b/plat/nxp/s32/s32g274ardb2/platform.mk
@@ -35,6 +35,7 @@ ERRATA_SPECULATIVE_AT := 1
 
 # Selecting Drivers for SoC
 $(eval $(call SET_NXP_MAKE_FLAG,CONSOLE_NEEDED,BL_COMM))
+$(eval $(call SET_NXP_MAKE_FLAG,CLK_NEEDED,BL_COMM))
 
 include ${PLAT_DRIVERS_PATH}/drivers.mk