diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 463790859..a871c5968 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -580,6 +580,9 @@ For Neoverse V2, the following errata build flags are defined : For Neoverse V3, the following errata build flags are defined : +- ``ERRATA_V3_2970647``: This applies errata 2970647 workaround to Neoverse-V3 + CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. + - ``ERRATA_V3_3701767``: This applies errata 3701767 workaround to Neoverse-V3 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 of the CPU and is still open. @@ -882,6 +885,9 @@ For Cortex-X4, the following errata build flags are defined : - ``ERRATA_X4_2923985``: This applies errata 2923985 workaround to Cortex-X4 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. +- ``ERRATA_X4_2957258``: This applies errata 2957258 workaround to Cortex-X4 + CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. + - ``ERRATA_X4_3076789``: This applies errata 3076789 workaround to Cortex-X4 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. @@ -891,6 +897,9 @@ For Cortex-X4, the following errata build flags are defined : For Cortex-X925, the following errata build flags are defined : +- ``ERRATA_X925_2963999``: This applies errata 2963999 workaround to Cortex-X925 + CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. + - ``ERRATA_X925_3701747``: This applies errata 3701747 workaround to Cortex-X925 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is still open. diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S index fded73fe4..1e81892b1 100644 --- a/lib/cpus/aarch64/cortex_x4.S +++ b/lib/cpus/aarch64/cortex_x4.S @@ -89,6 +89,21 @@ workaround_reset_end cortex_x4, ERRATUM(2923985) check_erratum_ls cortex_x4, ERRATUM(2923985), CPU_REV(0, 1) +workaround_reset_start cortex_x4, ERRATUM(2957258), ERRATA_X4_2957258 + /* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */ + ldr x0, =0x1 + msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */ + ldr x0, =0xd5380000 + msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */ + ldr x0, =0xFFFFFF40 + msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */ + ldr x0, =0x000080010033f + msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */ + isb +workaround_reset_end cortex_x4, ERRATUM(2957258) + +check_erratum_ls cortex_x4, ERRATUM(2957258), CPU_REV(0, 1) + workaround_reset_start cortex_x4, ERRATUM(3076789), ERRATA_X4_3076789 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(14) sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(13) diff --git a/lib/cpus/aarch64/cortex_x925.S b/lib/cpus/aarch64/cortex_x925.S index e2e70dd9a..5974c18d5 100644 --- a/lib/cpus/aarch64/cortex_x925.S +++ b/lib/cpus/aarch64/cortex_x925.S @@ -27,6 +27,21 @@ add_erratum_entry cortex_x925, ERRATUM(3701747), ERRATA_X925_3701747, NO_APPLY_A check_erratum_ls cortex_x925, ERRATUM(3701747), CPU_REV(0, 1) +workaround_reset_start cortex_x925, ERRATUM(2963999), ERRATA_X925_2963999 + /* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */ + ldr x0, =0x0 + msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */ + ldr x0, =0xd5380000 + msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */ + ldr x0, =0xFFFFFF40 + msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */ + ldr x0, =0x000080010033f + msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */ + isb +workaround_reset_end cortex_x925, ERRATUM(2963999) + +check_erratum_ls cortex_x925, ERRATUM(2963999), CPU_REV(0, 0) + /* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ workaround_reset_start cortex_x925, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 sysreg_bit_set CORTEX_X925_CPUECTLR_EL1, BIT(46) diff --git a/lib/cpus/aarch64/neoverse_v3.S b/lib/cpus/aarch64/neoverse_v3.S index 7fe2d7fa2..dad37099c 100644 --- a/lib/cpus/aarch64/neoverse_v3.S +++ b/lib/cpus/aarch64/neoverse_v3.S @@ -28,6 +28,21 @@ add_erratum_entry neoverse_v3, ERRATUM(3701767), ERRATA_V3_3701767, NO_APPLY_AT_ check_erratum_ls neoverse_v3, ERRATUM(3701767), CPU_REV(0, 2) +workaround_reset_start neoverse_v3, ERRATUM(2970647), ERRATA_V3_2970647 + /* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */ + ldr x0, =0x1 + msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */ + ldr x0, =0xd5380000 + msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */ + ldr x0, =0xFFFFFF40 + msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */ + ldr x0, =0x000080010033f + msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */ + isb +workaround_reset_end neoverse_v3, ERRATUM(2970647) + +check_erratum_ls neoverse_v3, ERRATUM(2970647), CPU_REV(0, 0) + #if WORKAROUND_CVE_2022_23960 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V3_BHB_LOOP_COUNT, neoverse_v3 #endif /* WORKAROUND_CVE_2022_23960 */ diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 0db7e94ac..813662496 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -564,6 +564,10 @@ CPU_FLAG_LIST += ERRATA_V1_2743233 # still open. CPU_FLAG_LIST += ERRATA_V1_2779461 +# Flag to apply erratum 2970647 workaround during reset. This erratum applies +# to revisions r0p0 of the Neoverse V3 cpu and is fixed in r0p1. +CPU_FLAG_LIST += ERRATA_V3_2970647 + # Flag to apply erratum 3701767 workaround during context save/restore of # ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r0p1 and r0p2 of # the Neoverse V3 cpu and is still open. @@ -885,6 +889,12 @@ CPU_FLAG_LIST += ERRATA_X4_2897503 # to revisions r0p0 and r0p1 of the Cortex-X4 cpu. It is fixed in r0p2. CPU_FLAG_LIST += ERRATA_X4_2923985 +# Flag to apply erratum 2957258 workaround to avoid incorrect virtualization of +# MPIDR_EL1/VMPIDR_EL2 and MIDR_EL1/VPIDR_EL2 when reading in EL2/EL3. This +# erratum applies to revisions r0p0, r0p1 of the Cortex-X4 cpu. It is fixed +# in r0p2. +CPU_FLAG_LIST += ERRATA_X4_2957258 + # Flag to apply erratum 3076789 workaround on reset. This erratum applies # to revisions r0p0 and r0p1 of the Cortex-X4 cpu. It is fixed in r0p2. CPU_FLAG_LIST += ERRATA_X4_3076789 @@ -894,6 +904,10 @@ CPU_FLAG_LIST += ERRATA_X4_3076789 # of the Cortex-X4 cpu and is still open. CPU_FLAG_LIST += ERRATA_X4_3701758 +# Flag to apply erratum 2963999 workaround during reset. This erratum applies +# to revisions r0p0 of the Cortex-X925 cpu and is fixed in r0p1. +CPU_FLAG_LIST += ERRATA_X925_2963999 + # Flag to apply erratum 3701747 workaround during context save/restore of # ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r0p1 of the # Cortex-X925 cpu and is still open.