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Merge changes from topic "refactor_st_common" into integration

Browse source 
* changes:
  refactor(st): move board info in common code
  refactor(st): move GIC code to common directory
  refactor(st): move boot backup register management
This commit is contained in:
Manish Pandey 2023-01-16 16:44:17 +01:00 • committed by TrustedFirmware Code Review
commit c2c3ca12e5
10 changed files with 142 additions and 122 deletions
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16
plat/st/common/include/stm32mp_common.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved * Copyright (C) 2018-2023, STMicroelectronics - All Rights Reserved
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -35,6 +35,9 @@ uintptr_t stm32mp_pwr_base(void);
/* Return the base address of the RCC peripheral */ /* Return the base address of the RCC peripheral */
uintptr_t stm32mp_rcc_base(void); uintptr_t stm32mp_rcc_base(void);
void stm32mp_gic_pcpu_init(void);
void stm32mp_gic_init(void);
/* Check MMU status to allow spinlock use */ /* Check MMU status to allow spinlock use */
bool stm32mp_lock_available(void); bool stm32mp_lock_available(void);
@ -113,12 +116,15 @@ void stm32mp_io_setup(void);
int stm32mp_map_ddr_non_cacheable(void); int stm32mp_map_ddr_non_cacheable(void);
int stm32mp_unmap_ddr(void); int stm32mp_unmap_ddr(void);
/* Functions to save and get boot peripheral info */ /* Function to save boot info */
void stm32_save_boot_interface(uint32_t interface, uint32_t instance); void stm32_save_boot_info(boot_api_context_t *boot_context);
/* Function to get boot peripheral info */
void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance); void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance);
/* Function to get BOOT_MODE backup register address */
uintptr_t stm32_get_bkpr_boot_mode_addr(void);
/* Functions to save and get boot authentication status and partition used */ /* Display board information from the value found in OTP fuse */
void stm32_save_boot_auth(uint32_t auth_status, uint32_t boot_partition); void stm32_display_board_info(uint32_t board_id);
#if PSA_FWU_SUPPORT #if PSA_FWU_SUPPORT
void stm32mp1_fwu_set_boot_idx(void); void stm32mp1_fwu_set_boot_idx(void);

99
plat/st/common/stm32mp_common.c
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -14,6 +14,7 @@
#include <drivers/st/stm32_console.h> #include <drivers/st/stm32_console.h>
#include <drivers/st/stm32mp_clkfunc.h> #include <drivers/st/stm32mp_clkfunc.h>
#include <drivers/st/stm32mp_reset.h> #include <drivers/st/stm32mp_reset.h>
#include <lib/mmio.h>
#include <lib/smccc.h> #include <lib/smccc.h>
#include <lib/xlat_tables/xlat_tables_v2.h> #include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h> #include <plat/common/platform.h>
@ -24,6 +25,36 @@
#define HEADER_VERSION_MAJOR_MASK GENMASK(23, 16) #define HEADER_VERSION_MAJOR_MASK GENMASK(23, 16)
#define RESET_TIMEOUT_US_1MS 1000U #define RESET_TIMEOUT_US_1MS 1000U
/* Internal layout of the 32bit OTP word board_id */
#define BOARD_ID_BOARD_NB_MASK GENMASK_32(31, 16)
#define BOARD_ID_BOARD_NB_SHIFT 16
#define BOARD_ID_VARCPN_MASK GENMASK_32(15, 12)
#define BOARD_ID_VARCPN_SHIFT 12
#define BOARD_ID_REVISION_MASK GENMASK_32(11, 8)
#define BOARD_ID_REVISION_SHIFT 8
#define BOARD_ID_VARFG_MASK GENMASK_32(7, 4)
#define BOARD_ID_VARFG_SHIFT 4
#define BOARD_ID_BOM_MASK GENMASK_32(3, 0)
#define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \
BOARD_ID_BOARD_NB_SHIFT)
#define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \
BOARD_ID_VARCPN_SHIFT)
#define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \
BOARD_ID_REVISION_SHIFT)
#define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \
BOARD_ID_VARFG_SHIFT)
#define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK)
#define BOOT_AUTH_MASK GENMASK_32(23, 20)
#define BOOT_AUTH_SHIFT 20
#define BOOT_PART_MASK GENMASK_32(19, 16)
#define BOOT_PART_SHIFT 16
#define BOOT_ITF_MASK GENMASK_32(15, 12)
#define BOOT_ITF_SHIFT 12
#define BOOT_INST_MASK GENMASK_32(11, 8)
#define BOOT_INST_SHIFT 8
static console_t console; static console_t console;
uintptr_t plat_get_ns_image_entrypoint(void) uintptr_t plat_get_ns_image_entrypoint(void)
@ -277,3 +308,69 @@ int32_t plat_get_soc_revision(void)
{ {
return (int32_t)(stm32mp_get_chip_version() & SOC_ID_REV_MASK); return (int32_t)(stm32mp_get_chip_version() & SOC_ID_REV_MASK);
} }
void stm32_display_board_info(uint32_t board_id)
{
char rev[2];
rev[0] = BOARD_ID2REV(board_id) - 1 + 'A';
rev[1] = '\0';
NOTICE("Board: MB%04x Var%u.%u Rev.%s-%02u\n",
BOARD_ID2NB(board_id),
BOARD_ID2VARCPN(board_id),
BOARD_ID2VARFG(board_id),
rev,
BOARD_ID2BOM(board_id));
}
void stm32_save_boot_info(boot_api_context_t *boot_context)
{
uint32_t auth_status;
assert(boot_context->boot_interface_instance <= (BOOT_INST_MASK >> BOOT_INST_SHIFT));
assert(boot_context->boot_interface_selected <= (BOOT_ITF_MASK >> BOOT_ITF_SHIFT));
assert(boot_context->boot_partition_used_toboot <= (BOOT_PART_MASK >> BOOT_PART_SHIFT));
switch (boot_context->auth_status) {
case BOOT_API_CTX_AUTH_NO:
auth_status = 0x0U;
break;
case BOOT_API_CTX_AUTH_SUCCESS:
auth_status = 0x2U;
break;
case BOOT_API_CTX_AUTH_FAILED:
default:
auth_status = 0x1U;
break;
}
clk_enable(TAMP_BKP_REG_CLK);
mmio_clrsetbits_32(stm32_get_bkpr_boot_mode_addr(),
BOOT_ITF_MASK | BOOT_INST_MASK | BOOT_PART_MASK | BOOT_AUTH_MASK,
(boot_context->boot_interface_instance << BOOT_INST_SHIFT) |
(boot_context->boot_interface_selected << BOOT_ITF_SHIFT) |
(boot_context->boot_partition_used_toboot << BOOT_PART_SHIFT) |
(auth_status << BOOT_AUTH_SHIFT));
clk_disable(TAMP_BKP_REG_CLK);
}
void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance)
{
static uint32_t itf;
if (itf == 0U) {
clk_enable(TAMP_BKP_REG_CLK);
itf = mmio_read_32(stm32_get_bkpr_boot_mode_addr()) &
(BOOT_ITF_MASK | BOOT_INST_MASK);
clk_disable(TAMP_BKP_REG_CLK);
}
*interface = (itf & BOOT_ITF_MASK) >> BOOT_ITF_SHIFT;
*instance = (itf & BOOT_INST_MASK) >> BOOT_INST_SHIFT;
}

31
plat/st/stm32mp1/stm32mp1_gic.c → plat/st/common/stm32mp_gic.c
View file

@ -1,21 +1,20 @@
/* /*
* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#include <libfdt.h>
#include <platform_def.h>
#include <common/bl_common.h> #include <common/bl_common.h>
#include <common/debug.h> #include <common/debug.h>
#include <drivers/arm/gicv2.h> #include <drivers/arm/gicv2.h>
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <lib/utils.h> #include <lib/utils.h>
#include <libfdt.h>
#include <plat/common/platform.h> #include <plat/common/platform.h>
struct stm32_gic_instance { #include <platform_def.h>
struct stm32mp_gic_instance {
uint32_t cells; uint32_t cells;
uint32_t phandle_node; uint32_t phandle_node;
}; };
@ -24,7 +23,7 @@ struct stm32_gic_instance {
* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
* interrupts. * interrupts.
*****************************************************************************/ *****************************************************************************/
static const interrupt_prop_t stm32mp1_interrupt_props[] = { static const interrupt_prop_t stm32mp_interrupt_props[] = {
PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0), PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0),
PLATFORM_G0_PROPS(GICV2_INTR_GROUP0) PLATFORM_G0_PROPS(GICV2_INTR_GROUP0)
}; };
@ -33,15 +32,15 @@ static const interrupt_prop_t stm32mp1_interrupt_props[] = {
static unsigned int target_mask_array[PLATFORM_CORE_COUNT] = {1, 2}; static unsigned int target_mask_array[PLATFORM_CORE_COUNT] = {1, 2};
static gicv2_driver_data_t platform_gic_data = { static gicv2_driver_data_t platform_gic_data = {
.interrupt_props = stm32mp1_interrupt_props, .interrupt_props = stm32mp_interrupt_props,
.interrupt_props_num = ARRAY_SIZE(stm32mp1_interrupt_props), .interrupt_props_num = ARRAY_SIZE(stm32mp_interrupt_props),
.target_masks = target_mask_array, .target_masks = target_mask_array,
.target_masks_num = ARRAY_SIZE(target_mask_array), .target_masks_num = ARRAY_SIZE(target_mask_array),
}; };
static struct stm32_gic_instance stm32_gic; static struct stm32mp_gic_instance stm32mp_gic;
void stm32mp1_gic_init(void) void stm32mp_gic_init(void)
{ {
int node; int node;
void *fdt; void *fdt;
@ -71,20 +70,20 @@ void stm32mp1_gic_init(void)
panic(); panic();
} }
stm32_gic.cells = fdt32_to_cpu(*cuint); stm32mp_gic.cells = fdt32_to_cpu(*cuint);
stm32_gic.phandle_node = fdt_get_phandle(fdt, node); stm32mp_gic.phandle_node = fdt_get_phandle(fdt, node);
if (stm32_gic.phandle_node == 0U) { if (stm32mp_gic.phandle_node == 0U) {
panic(); panic();
} }
gicv2_driver_init(&platform_gic_data); gicv2_driver_init(&platform_gic_data);
gicv2_distif_init(); gicv2_distif_init();
stm32mp1_gic_pcpu_init(); stm32mp_gic_pcpu_init();
} }
void stm32mp1_gic_pcpu_init(void) void stm32mp_gic_pcpu_init(void)
{ {
gicv2_pcpu_distif_init(); gicv2_pcpu_distif_init();
gicv2_set_pe_target_mask(plat_my_core_pos()); gicv2_set_pe_target_mask(plat_my_core_pos());

7
plat/st/stm32mp1/bl2_plat_setup.c
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -290,10 +290,7 @@ void bl2_el3_plat_arch_setup(void)
panic(); panic();
} }
stm32_save_boot_interface(boot_context->boot_interface_selected, stm32_save_boot_info(boot_context);
boot_context->boot_interface_instance);
stm32_save_boot_auth(boot_context->auth_status,
boot_context->boot_partition_used_toboot);
#if STM32MP_USB_PROGRAMMER && STM32MP15 #if STM32MP_USB_PROGRAMMER && STM32MP15
/* Deconfigure all UART RX pins configured by ROM code */ /* Deconfigure all UART RX pins configured by ROM code */

5
plat/st/stm32mp1/include/stm32mp1_private.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -14,9 +14,6 @@ void configure_mmu(void);
void stm32mp1_arch_security_setup(void); void stm32mp1_arch_security_setup(void);
void stm32mp1_security_setup(void); void stm32mp1_security_setup(void);
void stm32mp1_gic_pcpu_init(void);
void stm32mp1_gic_init(void);
void stm32mp1_syscfg_init(void); void stm32mp1_syscfg_init(void);
void stm32mp1_syscfg_enable_io_compensation_start(void); void stm32mp1_syscfg_enable_io_compensation_start(void);
void stm32mp1_syscfg_enable_io_compensation_finish(void); void stm32mp1_syscfg_enable_io_compensation_finish(void);

4
plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
View file

@ -1,5 +1,5 @@
# #
# Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. # Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
# #
# SPDX-License-Identifier: BSD-3-Clause # SPDX-License-Identifier: BSD-3-Clause
# #
@ -32,7 +32,7 @@ include drivers/arm/gic/v2/gicv2.mk
BL32_SOURCES += ${GICV2_SOURCES} \ BL32_SOURCES += ${GICV2_SOURCES} \
plat/common/plat_gicv2.c \ plat/common/plat_gicv2.c \
plat/st/stm32mp1/stm32mp1_gic.c plat/st/common/stm32mp_gic.c
# Generic PSCI # Generic PSCI
BL32_SOURCES += plat/common/plat_psci_common.c BL32_SOURCES += plat/common/plat_psci_common.c

9
plat/st/stm32mp1/sp_min/sp_min_setup.c
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -7,9 +7,8 @@
#include <assert.h> #include <assert.h>
#include <string.h> #include <string.h>
#include <platform_def.h>
#include <arch_helpers.h> #include <arch_helpers.h>
#include <bl32/sp_min/platform_sp_min.h>
#include <common/bl_common.h> #include <common/bl_common.h>
#include <common/debug.h> #include <common/debug.h>
#include <context.h> #include <context.h>
@ -27,7 +26,7 @@
#include <lib/xlat_tables/xlat_tables_v2.h> #include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h> #include <plat/common/platform.h>
#include <platform_sp_min.h> #include <platform_def.h>
/****************************************************************************** /******************************************************************************
* Placeholder variables for copying the arguments that have been passed to * Placeholder variables for copying the arguments that have been passed to
@ -181,7 +180,7 @@ void sp_min_platform_setup(void)
{ {
generic_delay_timer_init(); generic_delay_timer_init();
stm32mp1_gic_init(); stm32mp_gic_init();
if (stm32_iwdg_init() < 0) { if (stm32_iwdg_init() < 0) {
panic(); panic();

3
plat/st/stm32mp1/stm32mp1_def.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -548,6 +548,7 @@ enum ddr_type {
******************************************************************************/ ******************************************************************************/
#define TAMP_BASE U(0x5C00A000) #define TAMP_BASE U(0x5C00A000)
#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
#define TAMP_BKP_REG_CLK RTCAPB
#define TAMP_COUNTR U(0x40) #define TAMP_COUNTR U(0x40)
#if !(defined(__LINKER__) || defined(__ASSEMBLER__)) #if !(defined(__LINKER__) || defined(__ASSEMBLER__))

4
plat/st/stm32mp1/stm32mp1_pm.c
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -118,7 +118,7 @@ static void stm32_pwr_domain_suspend(const psci_power_state_t *target_state)
******************************************************************************/ ******************************************************************************/
static void stm32_pwr_domain_on_finish(const psci_power_state_t *target_state) static void stm32_pwr_domain_on_finish(const psci_power_state_t *target_state)
{ {
stm32mp1_gic_pcpu_init(); stm32mp_gic_pcpu_init();
write_cntfrq_el0(cntfrq_core0); write_cntfrq_el0(cntfrq_core0);
} }

86
plat/st/stm32mp1/stm32mp1_private.c
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -16,37 +16,12 @@
#include <plat/common/platform.h> #include <plat/common/platform.h>
#include <platform_def.h> #include <platform_def.h>
/* Internal layout of the 32bit OTP word board_id */
#define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16)
#define BOARD_ID_BOARD_NB_SHIFT 16
#define BOARD_ID_VARCPN_MASK GENMASK(15, 12)
#define BOARD_ID_VARCPN_SHIFT 12
#define BOARD_ID_REVISION_MASK GENMASK(11, 8)
#define BOARD_ID_REVISION_SHIFT 8
#define BOARD_ID_VARFG_MASK GENMASK(7, 4)
#define BOARD_ID_VARFG_SHIFT 4
#define BOARD_ID_BOM_MASK GENMASK(3, 0)
#define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \
BOARD_ID_BOARD_NB_SHIFT)
#define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \
BOARD_ID_VARCPN_SHIFT)
#define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \
BOARD_ID_REVISION_SHIFT)
#define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \
BOARD_ID_VARFG_SHIFT)
#define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK)
#if STM32MP13 #if STM32MP13
#define TAMP_BOOT_MODE_BACKUP_REG_ID U(30) #define TAMP_BOOT_MODE_BACKUP_REG_ID U(30)
#endif #endif
#if STM32MP15 #if STM32MP15
#define TAMP_BOOT_MODE_BACKUP_REG_ID U(20) #define TAMP_BOOT_MODE_BACKUP_REG_ID U(20)
#endif #endif
#define TAMP_BOOT_MODE_ITF_MASK GENMASK(15, 8)
#define TAMP_BOOT_MODE_ITF_SHIFT 8
#define TAMP_BOOT_MODE_AUTH_MASK GENMASK(23, 16)
#define TAMP_BOOT_MODE_AUTH_SHIFT 16
/* /*
* Backup register to store fwu update information. * Backup register to store fwu update information.
@ -520,23 +495,14 @@ void stm32mp_print_cpuinfo(void)
void stm32mp_print_boardinfo(void) void stm32mp_print_boardinfo(void)
{ {
uint32_t board_id = 0; uint32_t board_id = 0U;
if (stm32_get_otp_value(BOARD_ID_OTP, &board_id) != 0) { if (stm32_get_otp_value(BOARD_ID_OTP, &board_id) != 0) {
return; return;
} }
if (board_id != 0U) { if (board_id != 0U) {
char rev[2]; stm32_display_board_info(board_id);
rev[0] = BOARD_ID2REV(board_id) - 1 + 'A';
rev[1] = '\0';
NOTICE("Board: MB%04x Var%u.%u Rev.%s-%02u\n",
BOARD_ID2NB(board_id),
BOARD_ID2VARCPN(board_id),
BOARD_ID2VARFG(board_id),
rev,
BOARD_ID2BOM(board_id));
} }
} }
@ -697,51 +663,9 @@ uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags)
} }
#endif #endif
void stm32_save_boot_interface(uint32_t interface, uint32_t instance) uintptr_t stm32_get_bkpr_boot_mode_addr(void)
{ {
uintptr_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID); return tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
clk_enable(RTCAPB);
mmio_clrsetbits_32(bkpr_itf_idx,
TAMP_BOOT_MODE_ITF_MASK,
((interface << 4) | (instance & 0xFU)) <<
TAMP_BOOT_MODE_ITF_SHIFT);
clk_disable(RTCAPB);
}
void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance)
{
static uint32_t itf;
if (itf == 0U) {
uintptr_t bkpr = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
clk_enable(RTCAPB);
itf = (mmio_read_32(bkpr) & TAMP_BOOT_MODE_ITF_MASK) >>
TAMP_BOOT_MODE_ITF_SHIFT;
clk_disable(RTCAPB);
}
*interface = itf >> 4;
*instance = itf & 0xFU;
}
void stm32_save_boot_auth(uint32_t auth_status, uint32_t boot_partition)
{
uint32_t boot_status = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
clk_enable(RTCAPB);
mmio_clrsetbits_32(boot_status,
TAMP_BOOT_MODE_AUTH_MASK,
((auth_status << 4) | (boot_partition & 0xFU)) <<
TAMP_BOOT_MODE_AUTH_SHIFT);
clk_disable(RTCAPB);
} }
#if PSA_FWU_SUPPORT #if PSA_FWU_SUPPORT