diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h index 54cfcfb2f..1d592bd9d 100644 --- a/plat/st/common/include/stm32mp_common.h +++ b/plat/st/common/include/stm32mp_common.h @@ -35,6 +35,9 @@ uintptr_t stm32mp_pwr_base(void); /* Return the base address of the RCC peripheral */ uintptr_t stm32mp_rcc_base(void); +void stm32mp_gic_pcpu_init(void); +void stm32mp_gic_init(void); + /* Check MMU status to allow spinlock use */ bool stm32mp_lock_available(void); diff --git a/plat/st/stm32mp1/stm32mp1_gic.c b/plat/st/common/stm32mp_gic.c similarity index 75% rename from plat/st/stm32mp1/stm32mp1_gic.c rename to plat/st/common/stm32mp_gic.c index 851a9cf0c..d02b635a8 100644 --- a/plat/st/stm32mp1/stm32mp1_gic.c +++ b/plat/st/common/stm32mp_gic.c @@ -1,21 +1,20 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#include - -#include - #include #include #include #include #include +#include #include -struct stm32_gic_instance { +#include + +struct stm32mp_gic_instance { uint32_t cells; uint32_t phandle_node; }; @@ -24,7 +23,7 @@ struct stm32_gic_instance { * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 * interrupts. *****************************************************************************/ -static const interrupt_prop_t stm32mp1_interrupt_props[] = { +static const interrupt_prop_t stm32mp_interrupt_props[] = { PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0), PLATFORM_G0_PROPS(GICV2_INTR_GROUP0) }; @@ -33,15 +32,15 @@ static const interrupt_prop_t stm32mp1_interrupt_props[] = { static unsigned int target_mask_array[PLATFORM_CORE_COUNT] = {1, 2}; static gicv2_driver_data_t platform_gic_data = { - .interrupt_props = stm32mp1_interrupt_props, - .interrupt_props_num = ARRAY_SIZE(stm32mp1_interrupt_props), + .interrupt_props = stm32mp_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(stm32mp_interrupt_props), .target_masks = target_mask_array, .target_masks_num = ARRAY_SIZE(target_mask_array), }; -static struct stm32_gic_instance stm32_gic; +static struct stm32mp_gic_instance stm32mp_gic; -void stm32mp1_gic_init(void) +void stm32mp_gic_init(void) { int node; void *fdt; @@ -71,20 +70,20 @@ void stm32mp1_gic_init(void) panic(); } - stm32_gic.cells = fdt32_to_cpu(*cuint); + stm32mp_gic.cells = fdt32_to_cpu(*cuint); - stm32_gic.phandle_node = fdt_get_phandle(fdt, node); - if (stm32_gic.phandle_node == 0U) { + stm32mp_gic.phandle_node = fdt_get_phandle(fdt, node); + if (stm32mp_gic.phandle_node == 0U) { panic(); } gicv2_driver_init(&platform_gic_data); gicv2_distif_init(); - stm32mp1_gic_pcpu_init(); + stm32mp_gic_pcpu_init(); } -void stm32mp1_gic_pcpu_init(void) +void stm32mp_gic_pcpu_init(void) { gicv2_pcpu_distif_init(); gicv2_set_pe_target_mask(plat_my_core_pos()); diff --git a/plat/st/stm32mp1/include/stm32mp1_private.h b/plat/st/stm32mp1/include/stm32mp1_private.h index 21ef60d0a..4a522555d 100644 --- a/plat/st/stm32mp1/include/stm32mp1_private.h +++ b/plat/st/stm32mp1/include/stm32mp1_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,9 +14,6 @@ void configure_mmu(void); void stm32mp1_arch_security_setup(void); void stm32mp1_security_setup(void); -void stm32mp1_gic_pcpu_init(void); -void stm32mp1_gic_init(void); - void stm32mp1_syscfg_init(void); void stm32mp1_syscfg_enable_io_compensation_start(void); void stm32mp1_syscfg_enable_io_compensation_finish(void); diff --git a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk index 1d754d980..f5184e749 100644 --- a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk +++ b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -32,7 +32,7 @@ include drivers/arm/gic/v2/gicv2.mk BL32_SOURCES += ${GICV2_SOURCES} \ plat/common/plat_gicv2.c \ - plat/st/stm32mp1/stm32mp1_gic.c + plat/st/common/stm32mp_gic.c # Generic PSCI BL32_SOURCES += plat/common/plat_psci_common.c diff --git a/plat/st/stm32mp1/sp_min/sp_min_setup.c b/plat/st/stm32mp1/sp_min/sp_min_setup.c index 50b079471..b46f4af44 100644 --- a/plat/st/stm32mp1/sp_min/sp_min_setup.c +++ b/plat/st/stm32mp1/sp_min/sp_min_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,9 +7,8 @@ #include #include -#include - #include +#include #include #include #include @@ -27,7 +26,7 @@ #include #include -#include +#include /****************************************************************************** * Placeholder variables for copying the arguments that have been passed to @@ -181,7 +180,7 @@ void sp_min_platform_setup(void) { generic_delay_timer_init(); - stm32mp1_gic_init(); + stm32mp_gic_init(); if (stm32_iwdg_init() < 0) { panic(); diff --git a/plat/st/stm32mp1/stm32mp1_pm.c b/plat/st/stm32mp1/stm32mp1_pm.c index 6e438c44e..74393811c 100644 --- a/plat/st/stm32mp1/stm32mp1_pm.c +++ b/plat/st/stm32mp1/stm32mp1_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -118,7 +118,7 @@ static void stm32_pwr_domain_suspend(const psci_power_state_t *target_state) ******************************************************************************/ static void stm32_pwr_domain_on_finish(const psci_power_state_t *target_state) { - stm32mp1_gic_pcpu_init(); + stm32mp_gic_pcpu_init(); write_cntfrq_el0(cntfrq_core0); }