From 58d98ba82db1bea008c7c02c44b7b626b2455a35 Mon Sep 17 00:00:00 2001 From: Govindraj Raja Date: Tue, 21 Jan 2025 12:13:20 -0600 Subject: [PATCH 01/14] chore(cpus): fix incorrect header macro - errata.h is using incorrect header macro ERRATA_REPORT_H fix this. - Group errata function utilities. Change-Id: I6a4a8ec6546adb41e24d8885cb445fa8be830148 Signed-off-by: Govindraj Raja --- include/lib/cpus/errata.h | 41 +++++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 19 deletions(-) diff --git a/include/lib/cpus/errata.h b/include/lib/cpus/errata.h index a2f2fc641..18ddc836d 100644 --- a/include/lib/cpus/errata.h +++ b/include/lib/cpus/errata.h @@ -4,12 +4,11 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef ERRATA_REPORT_H -#define ERRATA_REPORT_H +#ifndef ERRATA_H +#define ERRATA_H #include - #define ERRATUM_WA_FUNC_SIZE CPU_WORD_SIZE #define ERRATUM_CHECK_FUNC_SIZE CPU_WORD_SIZE #define ERRATUM_ID_SIZE 4 @@ -35,21 +34,6 @@ void print_errata_status(void); -#if ERRATA_A75_764081 -bool errata_a75_764081_applies(void); -#else -static inline bool errata_a75_764081_applies(void) -{ - return false; -} -#endif - -#if ERRATA_A520_2938996 || ERRATA_X4_2726228 -unsigned int check_if_affected_core(void); -#endif - -int check_wa_cve_2024_7881(void); - /* * NOTE that this structure will be different on AArch32 and AArch64. The * uintptr_t will reflect the change and the alignment will be correct in both. @@ -68,6 +52,25 @@ struct erratum_entry { CASSERT(sizeof(struct erratum_entry) == ERRATUM_ENTRY_SIZE, assert_erratum_entry_asm_c_different_sizes); + +/* + * Runtime errata helpers. + */ +#if ERRATA_A75_764081 +bool errata_a75_764081_applies(void); +#else +static inline bool errata_a75_764081_applies(void) +{ + return false; +} +#endif + +#if ERRATA_A520_2938996 || ERRATA_X4_2726228 +unsigned int check_if_affected_core(void); +#endif + +int check_wa_cve_2024_7881(void); + #else /* @@ -96,4 +99,4 @@ CASSERT(sizeof(struct erratum_entry) == ERRATUM_ENTRY_SIZE, /* Macro to get CPU revision code for checking errata version compatibility. */ #define CPU_REV(r, p) ((r << 4) | p) -#endif /* ERRATA_REPORT_H */ +#endif /* ERRATA_H */ From 7455cd1721ec3b8671d6a2fae879f86ecfe497fb Mon Sep 17 00:00:00 2001 From: Govindraj Raja Date: Wed, 29 Jan 2025 15:01:10 -0600 Subject: [PATCH 02/14] fix(cpus): workaround for accessing ICH_VMCR_EL2 When ICH_VMCR_EL2.VBPR1 is written in Secure state (SCR_EL3.NS==0) and then subsequently read in Non-secure state (SCR_EL3.NS==1), a wrong value might be returned. The same issue exists in the opposite way. Adding workaround in EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. For example, EL3 software should set SCR_EL3.NS to 1 when saving or restoring the value ICH_VMCR_EL2 for Non-secure(or Realm) state. EL3 software should clear SCR_EL3.NS to 0 when saving or restoring the value ICH_VMCR_EL2 for Secure state. SDEN documentation: https://developer.arm.com/documentation/SDEN-1775101/latest/ Change-Id: I9f0403601c6346276e925f02eab55908b009d957 Signed-off-by: Govindraj Raja --- include/lib/cpus/errata.h | 1 + lib/cpus/errata_common.c | 14 ++++++-- lib/el3_runtime/aarch64/context_mgmt.c | 46 ++++++++++++++++++++++---- 3 files changed, 52 insertions(+), 9 deletions(-) diff --git a/include/lib/cpus/errata.h b/include/lib/cpus/errata.h index 18ddc836d..b9166f713 100644 --- a/include/lib/cpus/errata.h +++ b/include/lib/cpus/errata.h @@ -70,6 +70,7 @@ unsigned int check_if_affected_core(void); #endif int check_wa_cve_2024_7881(void); +bool errata_ich_vmcr_el2_applies(void); #else diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c index a4515a9e2..4cd105e34 100644 --- a/lib/cpus/errata_common.c +++ b/lib/cpus/errata_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,9 +8,9 @@ #include #include +#include #include #include -#include #include #include @@ -40,3 +40,13 @@ bool errata_a75_764081_applies(void) return false; } #endif /* ERRATA_A75_764081 */ + +bool errata_ich_vmcr_el2_applies(void) +{ + switch (EXTRACT_PARTNUM(read_midr())) { + default: + break; + } + + return false; +} diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 473190c11..f396752ef 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -1291,12 +1291,13 @@ static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) * SCR_EL3.NS = 1 before accessing this register. * --------------------------------------------------------------------------- */ -static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx) +static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx, uint32_t security_state) { + u_register_t scr_el3 = read_scr_el3(); + #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); #else - u_register_t scr_el3 = read_scr_el3(); write_scr_el3(scr_el3 | SCR_NS_BIT); isb(); @@ -1306,15 +1307,31 @@ static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx) isb(); #endif write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); + + if (errata_ich_vmcr_el2_applies()) { + if (security_state == SECURE) { + write_scr_el3(scr_el3 & ~SCR_NS_BIT); + } else { + write_scr_el3(scr_el3 | SCR_NS_BIT); + } + isb(); + } + write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); + + if (errata_ich_vmcr_el2_applies()) { + write_scr_el3(scr_el3); + isb(); + } } -static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx) +static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t security_state) { + u_register_t scr_el3 = read_scr_el3(); + #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); #else - u_register_t scr_el3 = read_scr_el3(); write_scr_el3(scr_el3 | SCR_NS_BIT); isb(); @@ -1324,7 +1341,22 @@ static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx) isb(); #endif write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); + + if (errata_ich_vmcr_el2_applies()) { + if (security_state == SECURE) { + write_scr_el3(scr_el3 & ~SCR_NS_BIT); + } else { + write_scr_el3(scr_el3 | SCR_NS_BIT); + } + isb(); + } + write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); + + if (errata_ich_vmcr_el2_applies()) { + write_scr_el3(scr_el3); + isb(); + } } /* ----------------------------------------------------- @@ -1416,7 +1448,7 @@ void cm_el2_sysregs_context_save(uint32_t security_state) el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); el2_sysregs_context_save_common(el2_sysregs_ctx); - el2_sysregs_context_save_gic(el2_sysregs_ctx); + el2_sysregs_context_save_gic(el2_sysregs_ctx, security_state); if (is_feat_mte2_supported()) { write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); @@ -1507,7 +1539,7 @@ void cm_el2_sysregs_context_restore(uint32_t security_state) el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); el2_sysregs_context_restore_common(el2_sysregs_ctx); - el2_sysregs_context_restore_gic(el2_sysregs_ctx); + el2_sysregs_context_restore_gic(el2_sysregs_ctx, security_state); if (is_feat_mte2_supported()) { write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); From 463b5b4a46552887c4fb70536d20f315f889add1 Mon Sep 17 00:00:00 2001 From: Govindraj Raja Date: Tue, 21 Jan 2025 12:32:14 -0600 Subject: [PATCH 03/14] fix(cpus): workaround for Cortex-A710 erratum 3701772 Cortex-A710 erratum 3701772 that applies to all revisions <= r2p1 and is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-1775101/latest/ Change-Id: I997c9cfaa75321f22b4f690c4d3f234c0b51c670 Signed-off-by: Govindraj Raja --- docs/design/cpu-specific-build-macros.rst | 4 ++++ include/lib/cpus/aarch64/cortex_a710.h | 6 +++++- lib/cpus/aarch64/cortex_a710.S | 8 +++++++- lib/cpus/cpu-ops.mk | 5 +++++ lib/cpus/errata_common.c | 8 ++++++++ 5 files changed, 29 insertions(+), 2 deletions(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 17b295451..ed0988555 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -653,6 +653,10 @@ For Cortex-A710, the following errata build flags are defined : CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the CPU and is still open. +- ``ERRATA_A710_3701772``: This applies errata 3701772 workaround to Cortex-A710 + CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0, r2p1 of the + CPU and is still open. + For Neoverse N2, the following errata build flags are defined : - ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2 diff --git a/include/lib/cpus/aarch64/cortex_a710.h b/include/lib/cpus/aarch64/cortex_a710.h index 9df8d471b..650193cc0 100644 --- a/include/lib/cpus/aarch64/cortex_a710.h +++ b/include/lib/cpus/aarch64/cortex_a710.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * Copyright (c) 2021-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -67,4 +67,8 @@ #define CORTEX_A710_CPUPOR_EL3 S3_6_C15_C8_2 #define CORTEX_A710_CPUPMR_EL3 S3_6_C15_C8_3 +#ifndef __ASSEMBLER__ +long check_erratum_cortex_a710_3701772(long cpu_rev); +#endif /* __ASSEMBLER__ */ + #endif /* CORTEX_A710_H */ diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S index dce9c7354..71ed6dbd4 100644 --- a/lib/cpus/aarch64/cortex_a710.S +++ b/lib/cpus/aarch64/cortex_a710.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + * Copyright (c) 2021-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,6 +22,8 @@ #error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif +.global check_erratum_cortex_a710_3701772 + #if WORKAROUND_CVE_2022_23960 wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710 #endif /* WORKAROUND_CVE_2022_23960 */ @@ -218,6 +220,10 @@ workaround_reset_end cortex_a710, CVE(2022, 23960) check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +add_erratum_entry cortex_a710, ERRATUM(3701772), ERRATA_A710_3701772, NO_APPLY_AT_RESET + +check_erratum_ls cortex_a710, ERRATUM(3701772), CPU_REV(2, 1) + /* ---------------------------------------------------- * HW will do the cache maintenance while powering down * ---------------------------------------------------- diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 19846890d..81ce13108 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -642,6 +642,11 @@ CPU_FLAG_LIST += ERRATA_A710_2768515 # open. CPU_FLAG_LIST += ERRATA_A710_2778471 +# Flag to apply erratum 3701772 workaround during context save/restore of +# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r1p0, r2p0, r2p1 +# of the Cortex-A710 cpu and is still open. +CPU_FLAG_LIST += ERRATA_A710_3701772 + # Flag to apply erratum 2002655 workaround during reset. This erratum applies # to revisions r0p0 of the Neoverse-N2 cpu and is fixed in r0p1. CPU_FLAG_LIST += ERRATA_N2_2002655 diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c index 4cd105e34..7c4db4648 100644 --- a/lib/cpus/errata_common.c +++ b/lib/cpus/errata_common.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -44,6 +45,13 @@ bool errata_a75_764081_applies(void) bool errata_ich_vmcr_el2_applies(void) { switch (EXTRACT_PARTNUM(read_midr())) { +#if ERRATA_A710_3701772 + case EXTRACT_PARTNUM(CORTEX_A710_MIDR): + if (check_erratum_cortex_a710_3701772(cpu_get_rev_var()) == ERRATA_APPLIES) + return true; + break; +#endif /* ERRATA_A710_3701772 */ + default: break; } From 26437afde1e7c16a5a05b8c7e0bb062efe63c3cf Mon Sep 17 00:00:00 2001 From: Govindraj Raja Date: Tue, 21 Jan 2025 17:00:11 -0600 Subject: [PATCH 04/14] fix(cpus): workaround for Cortex-A715 erratum 3699560 Cortex-A715 erratum 3699560 that applies to all revisions <= r1p3 and is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-2148827/latest/ Change-Id: I183aa921b4b6f715d64eb6b70809de2566017d31 Signed-off-by: Govindraj Raja --- docs/design/cpu-specific-build-macros.rst | 4 ++++ include/lib/cpus/aarch64/cortex_a715.h | 6 +++++- lib/cpus/aarch64/cortex_a715.S | 8 +++++++- lib/cpus/cpu-ops.mk | 5 +++++ lib/cpus/errata_common.c | 8 ++++++++ 5 files changed, 29 insertions(+), 2 deletions(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index ed0988555..47fa95568 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -960,6 +960,10 @@ For Cortex-A715, the following errata build flags are defined : Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1. It is fixed in r1p2. +- ``ERRATA_A715_3699560``: This applies errata 3699560 workaround to + Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, + r1p2, r1p3. It is still open. + For Cortex-A720, the following errata build flags are defined : - ``ERRATA_A720_2792132``: This applies errata 2792132 workaround to diff --git a/include/lib/cpus/aarch64/cortex_a715.h b/include/lib/cpus/aarch64/cortex_a715.h index c7f50db34..e9bd886f5 100644 --- a/include/lib/cpus/aarch64/cortex_a715.h +++ b/include/lib/cpus/aarch64/cortex_a715.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + * Copyright (c) 2021-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -38,4 +38,8 @@ #define CORTEX_A715_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +#ifndef __ASSEMBLER__ +long check_erratum_cortex_a715_3699560(long cpu_rev); +#endif /* __ASSEMBLER__ */ + #endif /* CORTEX_A715_H */ diff --git a/lib/cpus/aarch64/cortex_a715.S b/lib/cpus/aarch64/cortex_a715.S index 8c9988da0..fbc73eda3 100644 --- a/lib/cpus/aarch64/cortex_a715.S +++ b/lib/cpus/aarch64/cortex_a715.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + * Copyright (c) 2021-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,6 +22,8 @@ #error "Cortex-A715 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif +.global check_erratum_cortex_a715_3699560 + #if WORKAROUND_CVE_2022_23960 wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715 #endif /* WORKAROUND_CVE_2022_23960 */ @@ -127,6 +129,10 @@ workaround_reset_end cortex_a715, CVE(2022, 23960) check_erratum_chosen cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +add_erratum_entry cortex_a715, ERRATUM(3699560), ERRATA_A715_3699560, NO_APPLY_AT_RESET + +check_erratum_ls cortex_a715, ERRATUM(3699560), CPU_REV(1, 3) + cpu_reset_func_start cortex_a715 /* Disable speculative loads */ msr SSBS, xzr diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 81ce13108..0e5e24c69 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -989,6 +989,11 @@ CPU_FLAG_LIST += ERRATA_A715_2561034 # only to revision r0p0, r1p0 and r1p1. It is fixed in r1p2. CPU_FLAG_LIST += ERRATA_A715_2728106 +# Flag to apply erratum 3699560 workaround during context save/restore of +# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r1p0, r1p2, r1p3 +# of the Cortex-A715 cpu and is still open. +CPU_FLAG_LIST += ERRATA_A715_3699560 + # Flag to apply erratum 2792132 workaround during reset. This erratum applies # to revisions r0p0 and r0p1. It is fixed in r0p2. CPU_FLAG_LIST += ERRATA_A720_2792132 diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c index 7c4db4648..08f878606 100644 --- a/lib/cpus/errata_common.c +++ b/lib/cpus/errata_common.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -52,6 +53,13 @@ bool errata_ich_vmcr_el2_applies(void) break; #endif /* ERRATA_A710_3701772 */ +#if ERRATA_A715_3699560 + case EXTRACT_PARTNUM(CORTEX_A715_MIDR): + if (check_erratum_cortex_a715_3699560(cpu_get_rev_var()) == ERRATA_APPLIES) + return true; + break; +#endif /* ERRATA_A715_3699560 */ + default: break; } From 050c4a38a335c721c2f6ce38c33f1aa6aa328800 Mon Sep 17 00:00:00 2001 From: Govindraj Raja Date: Tue, 21 Jan 2025 17:12:33 -0600 Subject: [PATCH 05/14] fix(cpus): workaround for Cortex-A720 erratum 3699561 Cortex-A720 erratum 3699561 that applies to all revisions <= r0p2 and is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-2439421/latest/ Change-Id: I7ea3aaf3e7bf6b4f3648f6872e505a41247b14ba Signed-off-by: Govindraj Raja --- docs/design/cpu-specific-build-macros.rst | 4 ++++ include/lib/cpus/aarch64/cortex_a720.h | 6 +++++- lib/cpus/aarch64/cortex_a720.S | 8 +++++++- lib/cpus/cpu-ops.mk | 7 ++++++- lib/cpus/errata_common.c | 8 ++++++++ 5 files changed, 30 insertions(+), 3 deletions(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 47fa95568..34fa2e933 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -982,6 +982,10 @@ For Cortex-A720, the following errata build flags are defined : Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. +- ``ERRATA_A720_3699561``: This applies errata 3699561 workaround to + Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1 + and r0p2. It is still open. + DSU Errata Workarounds ---------------------- diff --git a/include/lib/cpus/aarch64/cortex_a720.h b/include/lib/cpus/aarch64/cortex_a720.h index 129c1ee33..670438f10 100644 --- a/include/lib/cpus/aarch64/cortex_a720.h +++ b/include/lib/cpus/aarch64/cortex_a720.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + * Copyright (c) 2021-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -38,4 +38,8 @@ #define CORTEX_A720_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +#ifndef __ASSEMBLER__ +long check_erratum_cortex_a720_3699561(long cpu_rev); +#endif /* __ASSEMBLER__ */ + #endif /* CORTEX_A720_H */ diff --git a/lib/cpus/aarch64/cortex_a720.S b/lib/cpus/aarch64/cortex_a720.S index 9befb36eb..ab2c12f3f 100644 --- a/lib/cpus/aarch64/cortex_a720.S +++ b/lib/cpus/aarch64/cortex_a720.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + * Copyright (c) 2021-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,6 +22,8 @@ #error "Cortex A720 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif +.global check_erratum_cortex_a720_3699561 + #if WORKAROUND_CVE_2022_23960 wa_cve_2022_23960_bhb_vector_table CORTEX_A720_BHB_LOOP_COUNT, cortex_a720 #endif /* WORKAROUND_CVE_2022_23960 */ @@ -72,6 +74,10 @@ workaround_reset_end cortex_a720, CVE(2022, 23960) check_erratum_chosen cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +add_erratum_entry cortex_a720, ERRATUM(3699561), ERRATA_A720_3699561, NO_APPLY_AT_RESET + +check_erratum_ls cortex_a720, ERRATUM(3699561), CPU_REV(0, 2) + cpu_reset_func_start cortex_a720 /* Disable speculative loads */ msr SSBS, xzr diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 0e5e24c69..68a50fc0d 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -1010,12 +1010,17 @@ CPU_FLAG_LIST += ERRATA_A720_2926083 # to revisions r0p0 and r0p1. It is fixed in r0p2. CPU_FLAG_LIST += ERRATA_A720_2940794 +# Flag to apply erratum 3699561 workaround during context save/restore of +# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r0p1, r0p2 of +# the Cortex-A720 cpu and is still open. +CPU_FLAG_LIST += ERRATA_A720_3699561 + # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0. # Applying the workaround results in higher DSU power consumption on idle. CPU_FLAG_LIST += ERRATA_DSU_798953 # Flag to apply DSU erratum 936184. This erratum applies to DSUs containing -# the ACP interface and revision < r2p0. Applying the workaround results in +# the ACP interface and revision < r0p0. Applying the workaround results in # higher DSU power consumption on idle. CPU_FLAG_LIST += ERRATA_DSU_936184 diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c index 08f878606..e5d14d509 100644 --- a/lib/cpus/errata_common.c +++ b/lib/cpus/errata_common.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -60,6 +61,13 @@ bool errata_ich_vmcr_el2_applies(void) break; #endif /* ERRATA_A715_3699560 */ +#if ERRATA_A720_3699561 + case EXTRACT_PARTNUM(CORTEX_A720_MIDR): + if (check_erratum_cortex_a720_3699561(cpu_get_rev_var()) == ERRATA_APPLIES) + return true;; + break; +#endif /* ERRATA_A720_3699561 */ + default: break; } From af5ae9a73f67dc8c9ed493846d031b052b0f22a0 Mon Sep 17 00:00:00 2001 From: Govindraj Raja Date: Tue, 21 Jan 2025 17:23:26 -0600 Subject: [PATCH 06/14] fix(cpus): workaround for Cortex-A720-AE erratum 3699562 Cortex-A720-AE erratum 3699562 that applies to r0p0 and is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-3090091/latest/ Change-Id: Ib830470747822cac916750c01684a65cb5efc15b Signed-off-by: Govindraj Raja --- docs/design/cpu-specific-build-macros.rst | 6 ++++++ include/lib/cpus/aarch64/cortex_a720_ae.h | 6 +++++- lib/cpus/aarch64/cortex_a720_ae.S | 8 +++++++- lib/cpus/cpu-ops.mk | 5 +++++ lib/cpus/errata_common.c | 8 ++++++++ 5 files changed, 31 insertions(+), 2 deletions(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 34fa2e933..5b439c950 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -986,6 +986,12 @@ For Cortex-A720, the following errata build flags are defined : Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is still open. +For Cortex-A720_AE, the following errata build flags are defined : + +- ``ERRATA_A720_AE_3699562``: This applies errata 3699562 workaround + to Cortex-A715_AE CPU. This needs to be enabled for revisions r0p0. + It is still open. + DSU Errata Workarounds ---------------------- diff --git a/include/lib/cpus/aarch64/cortex_a720_ae.h b/include/lib/cpus/aarch64/cortex_a720_ae.h index c88b1f9c0..cc9c3b0f2 100644 --- a/include/lib/cpus/aarch64/cortex_a720_ae.h +++ b/include/lib/cpus/aarch64/cortex_a720_ae.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024, Arm Limited. All rights reserved. + * Copyright (c) 2024-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,4 +20,8 @@ #define CORTEX_A720_AE_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A720_AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +#ifndef __ASSEMBLER__ +long check_erratum_cortex_a720_ae_3699562(long cpu_rev); +#endif /* __ASSEMBLER__ */ + #endif /* CORTEX_A720_AE_H */ diff --git a/lib/cpus/aarch64/cortex_a720_ae.S b/lib/cpus/aarch64/cortex_a720_ae.S index 42d49c336..57a5030d8 100644 --- a/lib/cpus/aarch64/cortex_a720_ae.S +++ b/lib/cpus/aarch64/cortex_a720_ae.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024, Arm Limited. All rights reserved. + * Copyright (c) 2024-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,6 +21,12 @@ #error "Cortex-A720AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif +.global check_erratum_cortex_a720_ae_3699562 + +add_erratum_entry cortex_a720_ae, ERRATUM(3699562), ERRATA_A720_AE_3699562, NO_APPLY_AT_RESET + +check_erratum_ls cortex_a720_ae, ERRATUM(3699562), CPU_REV(0, 0) + cpu_reset_func_start cortex_a720_ae /* Disable speculative loads */ msr SSBS, xzr diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 68a50fc0d..75d5ad247 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -1015,6 +1015,11 @@ CPU_FLAG_LIST += ERRATA_A720_2940794 # the Cortex-A720 cpu and is still open. CPU_FLAG_LIST += ERRATA_A720_3699561 +# Flag to apply erratum 3699562 workaround during context save/restore of +# ICH_VMCR_EL2 reg. This erratum applies to revision r0p0 the Cortex-A720-AE +# cpu and is still open. +CPU_FLAG_LIST += ERRATA_A720_AE_3699562 + # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0. # Applying the workaround results in higher DSU power consumption on idle. CPU_FLAG_LIST += ERRATA_DSU_798953 diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c index e5d14d509..a6be68a44 100644 --- a/lib/cpus/errata_common.c +++ b/lib/cpus/errata_common.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -68,6 +69,13 @@ bool errata_ich_vmcr_el2_applies(void) break; #endif /* ERRATA_A720_3699561 */ +#if ERRATA_A720_AE_3699562 + case EXTRACT_PARTNUM(CORTEX_A720_AE_MIDR): + if (check_erratum_cortex_a720_ae_3699562(cpu_get_rev_var()) == ERRATA_APPLIES) + return true; + break; +#endif /* ERRATA_A720_AE_3699562 */ + default: break; } From d732300b86238ac7166bc9bebd667a24dc3ed062 Mon Sep 17 00:00:00 2001 From: Govindraj Raja Date: Tue, 21 Jan 2025 17:44:17 -0600 Subject: [PATCH 07/14] fix(cpus): workaround for Cortex-A725 erratum 3699564 Cortex-A725 erratum 3699564 that applies to r0p0, r0p1 and is fixed in r0p2. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-2832921/latest Change-Id: Ifad1f6c3f5b74060273f897eb5e4b79dd9f088f7 Signed-off-by: Govindraj Raja --- docs/design/cpu-specific-build-macros.rst | 6 ++++++ include/lib/cpus/aarch64/cortex_a725.h | 6 +++++- lib/cpus/aarch64/cortex_a725.S | 8 +++++++- lib/cpus/cpu-ops.mk | 5 +++++ lib/cpus/errata_common.c | 7 +++++++ 5 files changed, 30 insertions(+), 2 deletions(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 5b439c950..57875da13 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -992,6 +992,12 @@ For Cortex-A720_AE, the following errata build flags are defined : to Cortex-A715_AE CPU. This needs to be enabled for revisions r0p0. It is still open. +For Cortex-A725, the following errata build flags are defined : + +- ``ERRATA_A725_3699564``: This applies errata 3699564 workaround to + Cortex-A725 CPU. This needs to be enabled for revisions r0p0 and r0p1. + It is fixed in r0p2. + DSU Errata Workarounds ---------------------- diff --git a/include/lib/cpus/aarch64/cortex_a725.h b/include/lib/cpus/aarch64/cortex_a725.h index cb1c099c8..20488dddf 100644 --- a/include/lib/cpus/aarch64/cortex_a725.h +++ b/include/lib/cpus/aarch64/cortex_a725.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023-2024, Arm Limited. All rights reserved. + * Copyright (c) 2023-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,4 +21,8 @@ #define CORTEX_A725_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A725_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +#ifndef __ASSEMBLER__ +long check_erratum_cortex_a725_3699564(long cpu_rev); +#endif /* __ASSEMBLER__ */ + #endif /* CORTEX_A725_H */ diff --git a/lib/cpus/aarch64/cortex_a725.S b/lib/cpus/aarch64/cortex_a725.S index af98d1453..c4d603441 100644 --- a/lib/cpus/aarch64/cortex_a725.S +++ b/lib/cpus/aarch64/cortex_a725.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023-2024, Arm Limited. All rights reserved. + * Copyright (c) 2023-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,6 +21,12 @@ #error "Cortex-A725 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif +.global check_erratum_cortex_a725_3699564 + +add_erratum_entry cortex_a725, ERRATUM(3699564), ERRATA_A725_3699564, NO_APPLY_AT_RESET + +check_erratum_ls cortex_a725, ERRATUM(3699564), CPU_REV(0, 1) + cpu_reset_func_start cortex_a725 /* Disable speculative loads */ msr SSBS, xzr diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 75d5ad247..747edf4e3 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -1020,6 +1020,11 @@ CPU_FLAG_LIST += ERRATA_A720_3699561 # cpu and is still open. CPU_FLAG_LIST += ERRATA_A720_AE_3699562 +# Flag to apply erratum 3699564 workaround during context save/restore of +# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r0p1 of +# the Cortex-A725 cpu and is fixed in r0p2 +CPU_FLAG_LIST += ERRATA_A725_3699564 + # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0. # Applying the workaround results in higher DSU power consumption on idle. CPU_FLAG_LIST += ERRATA_DSU_798953 diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c index a6be68a44..d9f83391f 100644 --- a/lib/cpus/errata_common.c +++ b/lib/cpus/errata_common.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -76,6 +77,12 @@ bool errata_ich_vmcr_el2_applies(void) break; #endif /* ERRATA_A720_AE_3699562 */ +#if ERRATA_A725_3699564 + case EXTRACT_PARTNUM(CORTEX_A725_MIDR): + if (check_erratum_cortex_a725_3699564(cpu_get_rev_var()) == ERRATA_APPLIES) + return true; + break; +#endif /* ERRATA_A725_3699564 */ default: break; } From ae6c7c97d4e0f491854b34628e0fa1038668f8e4 Mon Sep 17 00:00:00 2001 From: Govindraj Raja Date: Tue, 21 Jan 2025 18:02:51 -0600 Subject: [PATCH 08/14] fix(cpus): workaround for Cortex-X2 erratum 3701772 Cortex-X2 erratum 3701772 that applies to r0p0, r1p0, r2p0, r2p1 is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-1775100/latest/ Change-Id: I2ffc5e7d7467f1bcff8b895fea52a1daa7d14495 Signed-off-by: Govindraj Raja --- docs/design/cpu-specific-build-macros.rst | 4 ++++ include/lib/cpus/aarch64/cortex_x2.h | 6 +++++- lib/cpus/aarch64/cortex_x2.S | 8 +++++++- lib/cpus/cpu-ops.mk | 5 +++++ lib/cpus/errata_common.c | 9 +++++++++ 5 files changed, 30 insertions(+), 2 deletions(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 57875da13..00cfe191c 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -782,6 +782,10 @@ For Cortex-X2, the following errata build flags are defined : CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the CPU and it is still open. +- ``ERRATA_X2_3701772``: This applies errata 3701772 workaround to Cortex-X2 + CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the + CPU and it is still open. + For Cortex-X3, the following errata build flags are defined : - ``ERRATA_X3_2070301``: This applies errata 2070301 workaround to the Cortex-X3 diff --git a/include/lib/cpus/aarch64/cortex_x2.h b/include/lib/cpus/aarch64/cortex_x2.h index 0f97b1e11..9ec51775e 100644 --- a/include/lib/cpus/aarch64/cortex_x2.h +++ b/include/lib/cpus/aarch64/cortex_x2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * Copyright (c) 2021-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -64,4 +64,8 @@ #define CORTEX_X2_IMP_CPUPOR_EL3 S3_6_C15_C8_2 #define CORTEX_X2_IMP_CPUPMR_EL3 S3_6_C15_C8_3 +#ifndef __ASSEMBLER__ +long check_erratum_cortex_x2_3701772(long cpu_rev); +#endif /* __ASSEMBLER__ */ + #endif /* CORTEX_X2_H */ diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S index 2fc357ab5..c18ce3c0f 100644 --- a/lib/cpus/aarch64/cortex_x2.S +++ b/lib/cpus/aarch64/cortex_x2.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + * Copyright (c) 2021-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,6 +22,12 @@ #error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif +.global check_erratum_cortex_x2_3701772 + +add_erratum_entry cortex_x2, ERRATUM(3701772), ERRATA_X2_3701772, NO_APPLY_AT_RESET + +check_erratum_ls cortex_x2, ERRATUM(3701772), CPU_REV(2, 1) + #if WORKAROUND_CVE_2022_23960 wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2 #endif /* WORKAROUND_CVE_2022_23960 */ diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 747edf4e3..a879bb0c7 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -786,6 +786,11 @@ CPU_FLAG_LIST += ERRATA_X2_2768515 # to revisions r0p0, r1p0, r2p0, r2p1 of the Cortex-X2 cpu and it is still open. CPU_FLAG_LIST += ERRATA_X2_2778471 +# Flag to apply erratum 3701772 workaround during context save/restore of +# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r1p0, r2p0 and r2p1 +# of the Cortex-X2 cpu and is still open. +CPU_FLAG_LIST += ERRATA_X2_3701772 + # Flag to apply erratum 2070301 workaround on reset. This erratum applies # to revisions r0p0, r1p0, r1p1 and r1p2 of the Cortex-X3 cpu and is # still open. diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c index d9f83391f..5dbc50d61 100644 --- a/lib/cpus/errata_common.c +++ b/lib/cpus/errata_common.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -83,6 +84,14 @@ bool errata_ich_vmcr_el2_applies(void) return true; break; #endif /* ERRATA_A725_3699564 */ + +#if ERRATA_X2_3701772 + case EXTRACT_PARTNUM(CORTEX_X2_MIDR): + if (check_erratum_cortex_x2_3701772(cpu_get_rev_var()) == ERRATA_APPLIES) + return true; + break; +#endif /* ERRATA_X2_3701772 */ + default: break; } From 77feb745e42296c553c33bcaea5be3304168eff3 Mon Sep 17 00:00:00 2001 From: Govindraj Raja Date: Tue, 21 Jan 2025 18:12:35 -0600 Subject: [PATCH 09/14] fix(cpus): workaround for Cortex-X3 erratum 3701769 Cortex-X3 erratum 3701769 that applies to r0p0, r1p0, r1p1 and r1p2 is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-2055130/latest/ Change-Id: Ifd722e1bb8616ada2ad158297a7ca80b19a3370b Signed-off-by: Govindraj Raja --- docs/design/cpu-specific-build-macros.rst | 4 ++++ include/lib/cpus/aarch64/cortex_x3.h | 6 +++++- lib/cpus/aarch64/cortex_x3.S | 6 ++++++ lib/cpus/cpu-ops.mk | 5 +++++ lib/cpus/errata_common.c | 8 ++++++++ 5 files changed, 28 insertions(+), 1 deletion(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 00cfe191c..5862f673e 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -833,6 +833,10 @@ For Cortex-X3, the following errata build flags are defined : CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the CPU. It is fixed in r1p2. +- ``ERRATA_X3_3701769``: This applies errata 3701769 workaround to Cortex-X3 + CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 + of the CPU and it is still open. + For Cortex-X4, the following errata build flags are defined : - ``ERRATA_X4_2701112``: This applies erratum 2701112 workaround to Cortex-X4 diff --git a/include/lib/cpus/aarch64/cortex_x3.h b/include/lib/cpus/aarch64/cortex_x3.h index c5f820cf4..8834db118 100644 --- a/include/lib/cpus/aarch64/cortex_x3.h +++ b/include/lib/cpus/aarch64/cortex_x3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + * Copyright (c) 2021-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -63,4 +63,8 @@ #define CORTEX_X3_CPUACTLR3_EL1 S3_0_C15_C1_2 #define CORTEX_X3_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47) +#ifndef __ASSEMBLER__ +long check_erratum_cortex_x3_3701769(long cpu_rev); +#endif /* __ASSEMBLER__ */ + #endif /* CORTEX_X3_H */ diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S index 4a0212e20..24dbf9d83 100644 --- a/lib/cpus/aarch64/cortex_x3.S +++ b/lib/cpus/aarch64/cortex_x3.S @@ -22,6 +22,12 @@ #error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif +.global check_erratum_cortex_x3_3701769 + +add_erratum_entry cortex_x3, ERRATUM(3701769), ERRATA_X3_3701769, NO_APPLY_AT_RESET + +check_erratum_ls cortex_x3, ERRATUM(3701769), CPU_REV(1, 2) + #if WORKAROUND_CVE_2022_23960 wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3 #endif /* WORKAROUND_CVE_2022_23960 */ diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index a879bb0c7..fb153f71e 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -832,6 +832,11 @@ CPU_FLAG_LIST += ERRATA_X3_2742421 # to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu, it is fixed in r1p2. CPU_FLAG_LIST += ERRATA_X3_2743088 +# Flag to apply erratum 3701769 workaround during context save/restore of +# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r1p0, r1p1 and r1p2 +# of the Cortex-X3 cpu and is still open. +CPU_FLAG_LIST += ERRATA_X3_3701769 + # Flag to apply erratum 2779509 workaround on reset. This erratum applies # to revisions r0p0, r1p0, r1p1 of the Cortex-X3 cpu, it is fixed in r1p2. CPU_FLAG_LIST += ERRATA_X3_2779509 diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c index 5dbc50d61..f61d6e8c2 100644 --- a/lib/cpus/errata_common.c +++ b/lib/cpus/errata_common.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -92,6 +93,13 @@ bool errata_ich_vmcr_el2_applies(void) break; #endif /* ERRATA_X2_3701772 */ +#if ERRATA_X3_3701769 + case EXTRACT_PARTNUM(CORTEX_X3_MIDR): + if (check_erratum_cortex_x3_3701769(cpu_get_rev_var()) == ERRATA_APPLIES) + return true; + break; +#endif /* ERRATA_X3_3701769 */ + default: break; } From 38401c5388b5c3127745b758b3dc939d27041d7d Mon Sep 17 00:00:00 2001 From: Govindraj Raja Date: Tue, 21 Jan 2025 18:24:57 -0600 Subject: [PATCH 10/14] fix(cpus): workaround for Cortex-X4 erratum 3701758 Cortex-X4 erratum 3701758 that applies to r0p0, r0p1, r0p2 and r0p3 is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/109148/latest/ Change-Id: I4ee941d1e7653de7a12d69f538ca05f7f9f9961d Signed-off-by: Govindraj Raja --- docs/design/cpu-specific-build-macros.rst | 4 ++++ include/lib/cpus/aarch64/cortex_x4.h | 2 ++ lib/cpus/aarch64/cortex_x4.S | 5 +++++ lib/cpus/cpu-ops.mk | 5 +++++ lib/cpus/errata_common.c | 7 +++++++ 5 files changed, 23 insertions(+) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 5862f673e..63c316673 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -870,6 +870,10 @@ For Cortex-X4, the following errata build flags are defined : - ``ERRATA_X4_3076789``: This applies errata 3076789 workaround to Cortex-X4 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. +- ``ERRATA_X4_3701758``: This applies errata 3701758 workaround to Cortex-X4 + CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 and r0p3. + It is still open. + For Cortex-A510, the following errata build flags are defined : - ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to diff --git a/include/lib/cpus/aarch64/cortex_x4.h b/include/lib/cpus/aarch64/cortex_x4.h index 116f9a031..8ef830a48 100644 --- a/include/lib/cpus/aarch64/cortex_x4.h +++ b/include/lib/cpus/aarch64/cortex_x4.h @@ -50,6 +50,8 @@ static inline long check_erratum_cortex_x4_2726228(long cpu_rev) return 0; } #endif /* ERRATA_X4_2726228 */ + +long check_erratum_cortex_x4_3701758(long cpu_rev); #endif /* __ASSEMBLER__ */ #endif /* CORTEX_X4_H */ diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S index 57658286e..fded73fe4 100644 --- a/lib/cpus/aarch64/cortex_x4.S +++ b/lib/cpus/aarch64/cortex_x4.S @@ -23,6 +23,7 @@ #endif .global check_erratum_cortex_x4_2726228 +.global check_erratum_cortex_x4_3701758 #if WORKAROUND_CVE_2022_23960 wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4 @@ -119,6 +120,10 @@ workaround_reset_end cortex_x4, CVE(2024, 7881) check_erratum_chosen cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 +add_erratum_entry cortex_x4, ERRATUM(3701758), ERRATA_X4_3701758, NO_APPLY_AT_RESET + +check_erratum_ls cortex_x4, ERRATUM(3701758), CPU_REV(0, 3) + cpu_reset_func_start cortex_x4 /* Disable speculative loads */ msr SSBS, xzr diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index fb153f71e..e78234438 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -874,6 +874,11 @@ CPU_FLAG_LIST += ERRATA_X4_2923985 # to revisions r0p0 and r0p1 of the Cortex-X4 cpu. It is fixed in r0p2. CPU_FLAG_LIST += ERRATA_X4_3076789 +# Flag to apply erratum 3701758 workaround during context save/restore of +# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r0p1, r0p2 and r0p3 +# of the Cortex-X4 cpu and is still open. +CPU_FLAG_LIST += ERRATA_X4_3701758 + # Flag to apply erratum 1922240 workaround during reset. This erratum applies # to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1. CPU_FLAG_LIST += ERRATA_A510_1922240 diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c index f61d6e8c2..acb9fe3d2 100644 --- a/lib/cpus/errata_common.c +++ b/lib/cpus/errata_common.c @@ -100,6 +100,13 @@ bool errata_ich_vmcr_el2_applies(void) break; #endif /* ERRATA_X3_3701769 */ +#if ERRATA_X4_3701758 + case EXTRACT_PARTNUM(CORTEX_X4_MIDR): + if (check_erratum_cortex_x4_3701758(cpu_get_rev_var()) == ERRATA_APPLIES) + return true; + break; +#endif /* ERRATA_X4_3701758 */ + default: break; } From 511148ef5077dfb8f6bc7b9655e4ac19e16c4af0 Mon Sep 17 00:00:00 2001 From: Govindraj Raja Date: Tue, 21 Jan 2025 18:38:56 -0600 Subject: [PATCH 11/14] fix(cpus): workaround for Cortex-X925 erratum 3701747 Cortex-X925 erratum 3701747 that applies to r0p0, r0p1 and is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/109180/latest/ Change-Id: I080296666f89276b3260686c2bdb8de63fc174c1 Signed-off-by: Govindraj Raja --- docs/design/cpu-specific-build-macros.rst | 5 +++++ include/lib/cpus/aarch64/cortex_x925.h | 4 ++++ lib/cpus/aarch64/cortex_x925.S | 6 ++++++ lib/cpus/cpu-ops.mk | 5 +++++ lib/cpus/errata_common.c | 7 +++++++ 5 files changed, 27 insertions(+) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 63c316673..90c65be08 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -874,6 +874,11 @@ For Cortex-X4, the following errata build flags are defined : CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 and r0p3. It is still open. +For Cortex-X925, the following errata build flags are defined : + +- ``ERRATA_X925_3701747``: This applies errata 3701747 workaround to Cortex-X925 + CPU. This needs to be enabled for revisions r0p0 and r0p1. It is still open. + For Cortex-A510, the following errata build flags are defined : - ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to diff --git a/include/lib/cpus/aarch64/cortex_x925.h b/include/lib/cpus/aarch64/cortex_x925.h index ecbbb599a..170afbf41 100644 --- a/include/lib/cpus/aarch64/cortex_x925.h +++ b/include/lib/cpus/aarch64/cortex_x925.h @@ -26,4 +26,8 @@ ******************************************************************************/ #define CORTEX_X925_CPUACTLR6_EL1 S3_0_C15_C8_1 +#ifndef __ASSEMBLER__ +long check_erratum_cortex_x925_3701747(long cpu_rev); +#endif /* __ASSEMBLER__ */ + #endif /* CORTEX_X925_H */ diff --git a/lib/cpus/aarch64/cortex_x925.S b/lib/cpus/aarch64/cortex_x925.S index 5b6632aef..e2e70dd9a 100644 --- a/lib/cpus/aarch64/cortex_x925.S +++ b/lib/cpus/aarch64/cortex_x925.S @@ -21,6 +21,12 @@ #error "Cortex-X925 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif +.global check_erratum_cortex_x925_3701747 + +add_erratum_entry cortex_x925, ERRATUM(3701747), ERRATA_X925_3701747, NO_APPLY_AT_RESET + +check_erratum_ls cortex_x925, ERRATUM(3701747), CPU_REV(0, 1) + /* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ workaround_reset_start cortex_x925, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 sysreg_bit_set CORTEX_X925_CPUECTLR_EL1, BIT(46) diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index e78234438..947902aa7 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -879,6 +879,11 @@ CPU_FLAG_LIST += ERRATA_X4_3076789 # of the Cortex-X4 cpu and is still open. CPU_FLAG_LIST += ERRATA_X4_3701758 +# Flag to apply erratum 3701747 workaround during context save/restore of +# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r0p1 of the +# Cortex-X925 cpu and is still open. +CPU_FLAG_LIST += ERRATA_X925_3701747 + # Flag to apply erratum 1922240 workaround during reset. This erratum applies # to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1. CPU_FLAG_LIST += ERRATA_A510_1922240 diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c index acb9fe3d2..7f025b4b2 100644 --- a/lib/cpus/errata_common.c +++ b/lib/cpus/errata_common.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -107,6 +108,12 @@ bool errata_ich_vmcr_el2_applies(void) break; #endif /* ERRATA_X4_3701758 */ +#if ERRATA_X925_3701747 + case EXTRACT_PARTNUM(CORTEX_X925_MIDR): + if (check_erratum_cortex_x925_3701747(cpu_get_rev_var()) == ERRATA_APPLIES) + return true; + break; +#endif /* ERRATA_X925_3701747 */ default: break; } From adea6e52a782eeabd9027e3ca9a9847a13453cfa Mon Sep 17 00:00:00 2001 From: Govindraj Raja Date: Tue, 21 Jan 2025 18:56:25 -0600 Subject: [PATCH 12/14] fix(cpus): workaround for Neoverse-N2 erratum 3701773 Neoverse-N2 erratum 3701773 that applies to r0p0, r0p1, r0p2 and r0p3 is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-1982442/latest/ Change-Id: If95bd67363228c8083724b31f630636fb27f3b61 Signed-off-by: Govindraj Raja --- docs/design/cpu-specific-build-macros.rst | 4 ++++ include/lib/cpus/aarch64/neoverse_n2.h | 6 +++++- lib/cpus/aarch64/neoverse_n2.S | 8 +++++++- lib/cpus/cpu-ops.mk | 5 +++++ lib/cpus/errata_common.c | 9 +++++++++ 5 files changed, 30 insertions(+), 2 deletions(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 90c65be08..a978d9bd2 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -728,6 +728,10 @@ For Neoverse N2, the following errata build flags are defined : CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed in r0p3. +- ``ERRATA_N2_3701773``: This applies errata 3701773 workaround to Neoverse-N2 + CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is + still open. + For Cortex-X2, the following errata build flags are defined : - ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2 diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h index b379faba6..f5837d4fb 100644 --- a/include/lib/cpus/aarch64/neoverse_n2.h +++ b/include/lib/cpus/aarch64/neoverse_n2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2023, Arm Limited. All rights reserved. + * Copyright (c) 2020-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -69,4 +69,8 @@ #define CPUECTLR2_EL1_TXREQ_LSB U(0) #define CPUECTLR2_EL1_TXREQ_WIDTH U(3) +#ifndef __ASSEMBLER__ +long check_erratum_neoverse_n2_3701773(long cpu_rev); +#endif /* __ASSEMBLER__ */ + #endif /* NEOVERSE_N2_H */ diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S index 69aa8abbc..3df383942 100644 --- a/lib/cpus/aarch64/neoverse_n2.S +++ b/lib/cpus/aarch64/neoverse_n2.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2024, Arm Limited. All rights reserved. + * Copyright (c) 2020-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,6 +20,12 @@ #error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif +.global check_erratum_neoverse_n2_3701773 + +add_erratum_entry neoverse_n2, ERRATUM(3701773), ERRATA_N2_3701773, NO_APPLY_AT_RESET + +check_erratum_ls neoverse_n2, ERRATUM(3701773), CPU_REV(0, 3) + #if WORKAROUND_CVE_2022_23960 wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2 #endif /* WORKAROUND_CVE_2022_23960 */ diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 947902aa7..abe46992f 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -728,6 +728,11 @@ CPU_FLAG_LIST += ERRATA_N2_2743089 # to r0p0, r0p1, r0p2 of the Neoverse N2 cpu, it is fixed in r0p3. CPU_FLAG_LIST += ERRATA_N2_2779511 +# Flag to apply erratum 3701773 workaround during context save/restore of +# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r0p1, r0p2 and r0p3 +# of the Neoverse N2 cpu and is still open. +CPU_FLAG_LIST += ERRATA_N2_3701773 + # Flag to apply erratum 2002765 workaround during reset. This erratum applies # to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open. CPU_FLAG_LIST += ERRATA_X2_2002765 diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c index 7f025b4b2..3944fc07e 100644 --- a/lib/cpus/errata_common.c +++ b/lib/cpus/errata_common.c @@ -21,6 +21,7 @@ #include #include #include +#include #if ERRATA_A520_2938996 || ERRATA_X4_2726228 unsigned int check_if_affected_core(void) @@ -114,6 +115,14 @@ bool errata_ich_vmcr_el2_applies(void) return true; break; #endif /* ERRATA_X925_3701747 */ + +#if ERRATA_N2_3701773 + case EXTRACT_PARTNUM(NEOVERSE_N2_MIDR): + if (check_erratum_neoverse_n2_3701773(cpu_get_rev_var()) == ERRATA_APPLIES) + return true; + break; +#endif /* ERRATA_N2_3701773 */ + default: break; } From fded839285bdbdb72d492a573274abe22edc9311 Mon Sep 17 00:00:00 2001 From: Govindraj Raja Date: Tue, 21 Jan 2025 19:03:34 -0600 Subject: [PATCH 13/14] fix(cpus): workaround for Neoverse-N3 erratum 3699563 Neoverse-N3 erratum 3699563 that applies to r0p0 is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-3050973/latest/ Change-Id: I77aaf8ae0afff3adde9a85f4a1a13ac9d1daf0af Signed-off-by: Govindraj Raja --- docs/design/cpu-specific-build-macros.rst | 5 +++++ include/lib/cpus/aarch64/neoverse_n3.h | 6 +++++- lib/cpus/aarch64/neoverse_n3.S | 8 +++++++- lib/cpus/cpu-ops.mk | 5 +++++ lib/cpus/errata_common.c | 7 +++++++ 5 files changed, 29 insertions(+), 2 deletions(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index a978d9bd2..f4c2312a8 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -732,6 +732,11 @@ For Neoverse N2, the following errata build flags are defined : CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is still open. +For Neoverse N3, the following errata build flags are defined : + +- ``ERRATA_N3_3699563``: This applies errata 3699563 workaround to Neoverse-N3 + CPU. This needs to be enabled for revisions r0p0 and is still open. + For Cortex-X2, the following errata build flags are defined : - ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2 diff --git a/include/lib/cpus/aarch64/neoverse_n3.h b/include/lib/cpus/aarch64/neoverse_n3.h index 91963305d..24988aa45 100644 --- a/include/lib/cpus/aarch64/neoverse_n3.h +++ b/include/lib/cpus/aarch64/neoverse_n3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023-2024, Arm Limited. All rights reserved. + * Copyright (c) 2023-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,4 +21,8 @@ #define NEOVERSE_N3_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define NEOVERSE_N3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +#ifndef __ASSEMBLER__ +long check_erratum_neoverse_n3_3699563(long cpu_rev); +#endif /* __ASSEMBLER__ */ + #endif /* NEOVERSE_N3_H */ diff --git a/lib/cpus/aarch64/neoverse_n3.S b/lib/cpus/aarch64/neoverse_n3.S index d96c9d46a..8abcafeb9 100644 --- a/lib/cpus/aarch64/neoverse_n3.S +++ b/lib/cpus/aarch64/neoverse_n3.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023-2024, Arm Limited. All rights reserved. + * Copyright (c) 2023-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,6 +21,12 @@ #error "Neoverse-N3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif +.global check_erratum_neoverse_n3_3699563 + +add_erratum_entry neoverse_n3, ERRATUM(3699563), ERRATA_N3_3699563, NO_APPLY_AT_RESET + +check_erratum_ls neoverse_n3, ERRATUM(3699563), CPU_REV(0, 0) + cpu_reset_func_start neoverse_n3 /* Disable speculative loads */ msr SSBS, xzr diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index abe46992f..be4ce7739 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -733,6 +733,11 @@ CPU_FLAG_LIST += ERRATA_N2_2779511 # of the Neoverse N2 cpu and is still open. CPU_FLAG_LIST += ERRATA_N2_3701773 +# Flag to apply erratum 3699563 workaround during context save/restore of +# ICH_VMCR_EL2 reg. This erratum applies to revision r0p0 of the Neoverse N3 +# cpu and is still open. +CPU_FLAG_LIST += ERRATA_N3_3699563 + # Flag to apply erratum 2002765 workaround during reset. This erratum applies # to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open. CPU_FLAG_LIST += ERRATA_X2_2002765 diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c index 3944fc07e..fd7a387e4 100644 --- a/lib/cpus/errata_common.c +++ b/lib/cpus/errata_common.c @@ -22,6 +22,7 @@ #include #include #include +#include #if ERRATA_A520_2938996 || ERRATA_X4_2726228 unsigned int check_if_affected_core(void) @@ -123,6 +124,12 @@ bool errata_ich_vmcr_el2_applies(void) break; #endif /* ERRATA_N2_3701773 */ +#if ERRATA_N3_3699563 + case EXTRACT_PARTNUM(NEOVERSE_N3_MIDR): + if (check_erratum_neoverse_n3_3699563(cpu_get_rev_var()) == ERRATA_APPLIES) + return true; + break; +#endif /* ERRATA_N3_3699563 */ default: break; } From e25fc9df25092be31e7f7a9cc740e8df661a35c1 Mon Sep 17 00:00:00 2001 From: Govindraj Raja Date: Tue, 21 Jan 2025 19:20:29 -0600 Subject: [PATCH 14/14] fix(cpus): workaround for Neoverse-V3 erratum 3701767 Neoverse-V3 erratum 3701767 that applies to r0p0, r0p1, r0p2 is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-2891958/latest/ Change-Id: I5be0de881f408a9e82a07b8459d79490e9065f94 Signed-off-by: Govindraj Raja --- docs/design/cpu-specific-build-macros.rst | 6 ++++++ include/lib/cpus/aarch64/neoverse_v3.h | 4 ++++ lib/cpus/aarch64/neoverse_v3.S | 6 ++++++ lib/cpus/cpu-ops.mk | 5 +++++ lib/cpus/errata_common.c | 9 +++++++++ 5 files changed, 30 insertions(+) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index f4c2312a8..463790859 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -578,6 +578,12 @@ For Neoverse V2, the following errata build flags are defined : CPU, this affects all configurations. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed in r0p2. +For Neoverse V3, the following errata build flags are defined : + +- ``ERRATA_V3_3701767``: This applies errata 3701767 workaround to Neoverse-V3 + CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 of the CPU and + is still open. + For Cortex-A710, the following errata build flags are defined : - ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to diff --git a/include/lib/cpus/aarch64/neoverse_v3.h b/include/lib/cpus/aarch64/neoverse_v3.h index a31bdd3aa..5a828c0c7 100644 --- a/include/lib/cpus/aarch64/neoverse_v3.h +++ b/include/lib/cpus/aarch64/neoverse_v3.h @@ -30,4 +30,8 @@ ******************************************************************************/ #define NEOVERSE_V3_CPUACTLR6_EL1 S3_0_C15_C8_1 +#ifndef __ASSEMBLER__ +long check_erratum_neoverse_v3_3701767(long cpu_rev); +#endif /* __ASSEMBLER__ */ + #endif /* NEOVERSE_V3_H */ diff --git a/lib/cpus/aarch64/neoverse_v3.S b/lib/cpus/aarch64/neoverse_v3.S index 69b66278d..7fe2d7fa2 100644 --- a/lib/cpus/aarch64/neoverse_v3.S +++ b/lib/cpus/aarch64/neoverse_v3.S @@ -22,6 +22,12 @@ #error "Neoverse V3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif +.global check_erratum_neoverse_v3_3701767 + +add_erratum_entry neoverse_v3, ERRATUM(3701767), ERRATA_V3_3701767, NO_APPLY_AT_RESET + +check_erratum_ls neoverse_v3, ERRATUM(3701767), CPU_REV(0, 2) + #if WORKAROUND_CVE_2022_23960 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V3_BHB_LOOP_COUNT, neoverse_v3 #endif /* WORKAROUND_CVE_2022_23960 */ diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index be4ce7739..fb904e232 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -564,6 +564,11 @@ CPU_FLAG_LIST += ERRATA_V1_2743233 # still open. CPU_FLAG_LIST += ERRATA_V1_2779461 +# Flag to apply erratum 3701767 workaround during context save/restore of +# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r0p1 and r0p2 of +# the Neoverse V3 cpu and is still open. +CPU_FLAG_LIST += ERRATA_V3_3701767 + # Flag to apply erratum 1987031 workaround during reset. This erratum applies # to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open. CPU_FLAG_LIST += ERRATA_A710_1987031 diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c index fd7a387e4..a39143031 100644 --- a/lib/cpus/errata_common.c +++ b/lib/cpus/errata_common.c @@ -23,6 +23,7 @@ #include #include #include +#include #if ERRATA_A520_2938996 || ERRATA_X4_2726228 unsigned int check_if_affected_core(void) @@ -130,6 +131,14 @@ bool errata_ich_vmcr_el2_applies(void) return true; break; #endif /* ERRATA_N3_3699563 */ + +#if ERRATA_V3_3701767 + case EXTRACT_PARTNUM(NEOVERSE_V3_MIDR): + if (check_erratum_neoverse_v3_3701767(cpu_get_rev_var()) == ERRATA_APPLIES) + return true; + break; +#endif /* ERRATA_V3_3701767 */ + default: break; }