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Merge changes from topic "sm/errata_refactor" into integration

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* changes:
  refactor(cpus): convert Cortex-A15 to use the errata framework
  refactor(cpus): convert the Cortex-X3 to use the cpu helpers
  refactor(cpus): convert Cortex-X3 to use the errata framework
  refactor(cpus): reorder Cortex-X3 errata by ascending order
  refactor(cpus): convert the Cortex-A73 to use the cpu helpers
  refactor(cpus): convert Cortex-A73 to use the errata framework
  refactor(cpus): reorder Cortex-A73 errata by ascending order
  refactor(cpus): convert the Cortex-A35 to use the cpu helpers
  refactor(cpus): convert Cortex-A35 to use the errata framework
This commit is contained in:
Bipin Ravi 2023-08-05 00:50:32 +02:00 • committed by TrustedFirmware Code Review
commit bfd856004f
4 changed files with 126 additions and 386 deletions
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33
lib/cpus/aarch32/cortex_a15.S
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2016-2022, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -62,6 +62,7 @@ func check_errata_816470
bx lr bx lr
endfunc check_errata_816470 endfunc check_errata_816470
add_erratum_entry cortex_a15, ERRATUM(816470), ERRATA_A15_816470
/* ---------------------------------------------------- /* ----------------------------------------------------
* Errata Workaround for Cortex A15 Errata #827671. * Errata Workaround for Cortex A15 Errata #827671.
* This applies only to revision >= r3p0 of Cortex A15. * This applies only to revision >= r3p0 of Cortex A15.
@ -91,6 +92,8 @@ func check_errata_827671
b cpu_rev_var_hs b cpu_rev_var_hs
endfunc check_errata_827671 endfunc check_errata_827671
add_erratum_entry cortex_a15, ERRATUM(827671), ERRATA_A15_827671
func check_errata_cve_2017_5715 func check_errata_cve_2017_5715
#if WORKAROUND_CVE_2017_5715 #if WORKAROUND_CVE_2017_5715
mov r0, #ERRATA_APPLIES mov r0, #ERRATA_APPLIES
@ -100,6 +103,8 @@ func check_errata_cve_2017_5715
bx lr bx lr
endfunc check_errata_cve_2017_5715 endfunc check_errata_cve_2017_5715
add_erratum_entry cortex_a15, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
func check_errata_cve_2022_23960 func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960 #if WORKAROUND_CVE_2022_23960
mov r0, #ERRATA_APPLIES mov r0, #ERRATA_APPLIES
@ -109,29 +114,7 @@ func check_errata_cve_2022_23960
bx lr bx lr
endfunc check_errata_cve_2022_23960 endfunc check_errata_cve_2022_23960
#if REPORT_ERRATA add_erratum_entry cortex_a15, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
/*
* Errata printing function for Cortex A15. Must follow AAPCS.
*/
func cortex_a15_errata_report
push {r12, lr}
bl cpu_get_rev_var
mov r4, r0
/*
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata ERRATA_A15_816470, cortex_a15, 816470
report_errata ERRATA_A15_827671, cortex_a15, 827671
report_errata WORKAROUND_CVE_2017_5715, cortex_a15, cve_2017_5715
report_errata WORKAROUND_CVE_2022_23960, cortex_a15, cve_2022_23960
pop {r12, lr}
bx lr
endfunc cortex_a15_errata_report
#endif
func cortex_a15_reset_func func cortex_a15_reset_func
mov r5, lr mov r5, lr
@ -185,6 +168,8 @@ func cortex_a15_cluster_pwr_dwn
b cortex_a15_disable_smp b cortex_a15_disable_smp
endfunc cortex_a15_cluster_pwr_dwn endfunc cortex_a15_cluster_pwr_dwn
errata_report_shim cortex_a15
declare_cpu_ops cortex_a15, CORTEX_A15_MIDR, \ declare_cpu_ops cortex_a15, CORTEX_A15_MIDR, \
cortex_a15_reset_func, \ cortex_a15_reset_func, \
cortex_a15_core_pwr_dwn, \ cortex_a15_core_pwr_dwn, \

80
lib/cpus/aarch64/cortex_a35.S
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -16,9 +16,7 @@
* --------------------------------------------- * ---------------------------------------------
*/ */
func cortex_a35_disable_dcache func cortex_a35_disable_dcache
mrs x1, sctlr_el3 sysreg_bit_clear sctlr_el3, SCTLR_C_BIT
bic x1, x1, #SCTLR_C_BIT
msr sctlr_el3, x1
isb isb
ret ret
endfunc cortex_a35_disable_dcache endfunc cortex_a35_disable_dcache
@ -28,65 +26,29 @@ endfunc cortex_a35_disable_dcache
* --------------------------------------------- * ---------------------------------------------
*/ */
func cortex_a35_disable_smp func cortex_a35_disable_smp
mrs x0, CORTEX_A35_CPUECTLR_EL1 sysreg_bit_clear CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT
bic x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT
msr CORTEX_A35_CPUECTLR_EL1, x0
isb isb
dsb sy dsb sy
ret ret
endfunc cortex_a35_disable_smp endfunc cortex_a35_disable_smp
/* --------------------------------------------------- workaround_reset_start cortex_a35, ERRATUM(855472), ERRATA_A35_855472
* Errata Workaround for Cortex A35 Errata #855472. sysreg_bit_set CORTEX_A35_CPUACTLR_EL1, CORTEX_A35_CPUACTLR_EL1_ENDCCASCI
* This applies to revisions r0p0 of Cortex A35. workaround_reset_end cortex_a35, ERRATUM(855472)
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* ---------------------------------------------------
*/
func errata_a35_855472_wa
/*
* Compare x0 against revision r0p0
*/
mov x17, x30
bl check_errata_855472
cbz x0, 1f
mrs x1, CORTEX_A35_CPUACTLR_EL1
orr x1, x1, #CORTEX_A35_CPUACTLR_EL1_ENDCCASCI
msr CORTEX_A35_CPUACTLR_EL1, x1
isb
1:
ret x17
endfunc errata_a35_855472_wa
func check_errata_855472 check_erratum_ls cortex_a35, ERRATUM(855472), CPU_REV(0, 0)
mov x1, #0x00
b cpu_rev_var_ls
endfunc check_errata_855472
/* ------------------------------------------------- /* -------------------------------------------------
* The CPU Ops reset function for Cortex-A35. * The CPU Ops reset function for Cortex-A35.
* Clobbers: x0
* ------------------------------------------------- * -------------------------------------------------
*/ */
func cortex_a35_reset_func cpu_reset_func_start cortex_a35
mov x19, x30
bl cpu_get_rev_var
#if ERRATA_A35_855472
bl errata_a35_855472_wa
#endif
/* --------------------------------------------- /* ---------------------------------------------
* Enable the SMP bit. * Enable the SMP bit.
* --------------------------------------------- * ---------------------------------------------
*/ */
mrs x0, CORTEX_A35_CPUECTLR_EL1 sysreg_bit_set CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT
orr x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT cpu_reset_func_end cortex_a35
msr CORTEX_A35_CPUECTLR_EL1, x0
isb
ret x19
endfunc cortex_a35_reset_func
func cortex_a35_core_pwr_dwn func cortex_a35_core_pwr_dwn
mov x18, x30 mov x18, x30
@ -149,27 +111,7 @@ func cortex_a35_cluster_pwr_dwn
b cortex_a35_disable_smp b cortex_a35_disable_smp
endfunc cortex_a35_cluster_pwr_dwn endfunc cortex_a35_cluster_pwr_dwn
#if REPORT_ERRATA errata_report_shim cortex_a35
/*
* Errata printing function for Cortex A35. Must follow AAPCS.
*/
func cortex_a35_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
mov x8, x0
/*
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata ERRATA_A35_855472, cortex_a35, 855472
ldp x8, x30, [sp], #16
ret
endfunc cortex_a35_errata_report
#endif
/* --------------------------------------------- /* ---------------------------------------------
* This function provides cortex_a35 specific * This function provides cortex_a35 specific

241
lib/cpus/aarch64/cortex_a73.S
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -15,9 +15,7 @@
* --------------------------------------------- * ---------------------------------------------
*/ */
func cortex_a73_disable_dcache func cortex_a73_disable_dcache
mrs x1, sctlr_el3 sysreg_bit_clear sctlr_el3, SCTLR_C_BIT
bic x1, x1, #SCTLR_C_BIT
msr sctlr_el3, x1
isb isb
ret ret
endfunc cortex_a73_disable_dcache endfunc cortex_a73_disable_dcache
@ -27,124 +25,95 @@ endfunc cortex_a73_disable_dcache
* --------------------------------------------- * ---------------------------------------------
*/ */
func cortex_a73_disable_smp func cortex_a73_disable_smp
mrs x0, CORTEX_A73_CPUECTLR_EL1 sysreg_bit_clear CORTEX_A73_CPUECTLR_EL1, CORTEX_A73_CPUECTLR_SMP_BIT
bic x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT
msr CORTEX_A73_CPUECTLR_EL1, x0
isb isb
dsb sy dsb sy
ret ret
endfunc cortex_a73_disable_smp endfunc cortex_a73_disable_smp
/* --------------------------------------------------- func check_smccc_arch_workaround_3
* Errata Workaround for Cortex A73 Errata #852427. mov x0, #ERRATA_APPLIES
* This applies only to revision r0p0 of Cortex A73. ret
* Inputs: endfunc check_smccc_arch_workaround_3
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17 workaround_reset_start cortex_a73, ERRATUM(852427), ERRATA_A73_852427
* --------------------------------------------------- sysreg_bit_set CORTEX_A73_DIAGNOSTIC_REGISTER, BIT(12)
*/ workaround_reset_end cortex_a73, ERRATUM(852427)
func errata_a73_852427_wa
/* check_erratum_ls cortex_a73, ERRATUM(852427), CPU_REV(0, 0)
* Compare x0 against revision r0p0
*/ workaround_reset_start cortex_a73, ERRATUM(855423), ERRATA_A73_855423
mov x17, x30 sysreg_bit_set CORTEX_A73_IMP_DEF_REG2, BIT(7)
bl check_errata_852427 workaround_reset_end cortex_a73, ERRATUM(855423)
cbz x0, 1f
mrs x1, CORTEX_A73_DIAGNOSTIC_REGISTER check_erratum_ls cortex_a73, ERRATUM(855423), CPU_REV(0, 1)
orr x1, x1, #(1 << 12)
msr CORTEX_A73_DIAGNOSTIC_REGISTER, x1 workaround_reset_start cortex_a73, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
isb #if IMAGE_BL31
override_vector_table wa_cve_2017_5715_bpiall_vbar
#endif /* IMAGE_BL31 */
workaround_reset_end cortex_a73, CVE(2017, 5715)
check_erratum_custom_start cortex_a73, CVE(2017, 5715)
cpu_check_csv2 x0, 1f
#if WORKAROUND_CVE_2017_5715
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif
ret
1: 1:
ret x17 mov x0, #ERRATA_NOT_APPLIES
endfunc errata_a73_852427_wa ret
check_erratum_custom_end cortex_a73, CVE(2017, 5715)
func check_errata_852427 workaround_reset_start cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
mov x1, #0x00 sysreg_bit_set CORTEX_A73_IMP_DEF_REG1, CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE
b cpu_rev_var_ls workaround_reset_end cortex_a73, CVE(2018, 3639)
endfunc check_errata_852427
/* --------------------------------------------------- check_erratum_chosen cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
* Errata Workaround for Cortex A73 Errata #855423.
* This applies only to revision <= r0p1 of Cortex A73. workaround_reset_start cortex_a73, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
* Inputs: #if IMAGE_BL31
* x0: variant[4:7] and revision[0:3] of current cpu. /* Skip installing vector table again for CVE_2022_23960 */
* Shall clobber: x0-x17 override_vector_table wa_cve_2017_5715_bpiall_vbar
* --------------------------------------------------- cmp x0, x1
*/ b.eq 1f
func errata_a73_855423_wa msr vbar_el3, x0
/*
* Compare x0 against revision r0p1
*/
mov x17, x30
bl check_errata_855423
cbz x0, 1f
mrs x1, CORTEX_A73_IMP_DEF_REG2
orr x1, x1, #(1 << 7)
msr CORTEX_A73_IMP_DEF_REG2, x1
isb
1: 1:
ret x17 #endif /* IMAGE_BL31 */
endfunc errata_a73_855423_wa workaround_reset_end cortex_a73, CVE(2022, 23960)
func check_errata_855423 check_erratum_custom_start cortex_a73, CVE(2022, 23960)
mov x1, #0x01 #if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960
b cpu_rev_var_ls cpu_check_csv2 x0, 1f
endfunc check_errata_855423 mov x0, #ERRATA_APPLIES
ret
1:
#if WORKAROUND_CVE_2022_23960
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif /* WORKAROUND_CVE_2022_23960 */
ret
#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */
mov x0, #ERRATA_MISSING
ret
check_erratum_custom_end cortex_a73, CVE(2022, 23960)
/* ------------------------------------------------- /* -------------------------------------------------
* The CPU Ops reset function for Cortex-A73. * The CPU Ops reset function for Cortex-A73.
* ------------------------------------------------- * -------------------------------------------------
*/ */
func cortex_a73_reset_func cpu_reset_func_start cortex_a73
mov x19, x30
bl cpu_get_rev_var
mov x18, x0
#if ERRATA_A73_852427
mov x0, x18
bl errata_a73_852427_wa
#endif
#if ERRATA_A73_855423
mov x0, x18
bl errata_a73_855423_wa
#endif
#if IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960)
cpu_check_csv2 x0, 1f
adr x0, wa_cve_2017_5715_bpiall_vbar
msr vbar_el3, x0
isb
/* Skip installing vector table again for CVE_2022_23960 */
b 2f
1:
#if WORKAROUND_CVE_2022_23960
adr x0, wa_cve_2017_5715_bpiall_vbar
msr vbar_el3, x0
isb
#endif
2:
#endif /* IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) */
#if WORKAROUND_CVE_2018_3639
mrs x0, CORTEX_A73_IMP_DEF_REG1
orr x0, x0, #CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE
msr CORTEX_A73_IMP_DEF_REG1, x0
isb
#endif
/* --------------------------------------------- /* ---------------------------------------------
* Enable the SMP bit. * Enable the SMP bit.
* Clobbers : x0 * Clobbers : x0
* --------------------------------------------- * ---------------------------------------------
*/ */
mrs x0, CORTEX_A73_CPUECTLR_EL1 sysreg_bit_set CORTEX_A73_CPUECTLR_EL1, CORTEX_A73_CPUECTLR_SMP_BIT
orr x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT cpu_reset_func_end cortex_a73
msr CORTEX_A73_CPUECTLR_EL1, x0
isb
ret x19
endfunc cortex_a73_reset_func
func cortex_a73_core_pwr_dwn func cortex_a73_core_pwr_dwn
mov x18, x30 mov x18, x30
@ -207,74 +176,8 @@ func cortex_a73_cluster_pwr_dwn
b cortex_a73_disable_smp b cortex_a73_disable_smp
endfunc cortex_a73_cluster_pwr_dwn endfunc cortex_a73_cluster_pwr_dwn
func check_errata_cve_2017_5715
cpu_check_csv2 x0, 1f
#if WORKAROUND_CVE_2017_5715
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif
ret
1:
mov x0, #ERRATA_NOT_APPLIES
ret
endfunc check_errata_cve_2017_5715
func check_errata_cve_2018_3639 errata_report_shim cortex_a73
#if WORKAROUND_CVE_2018_3639
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif
ret
endfunc check_errata_cve_2018_3639
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960
cpu_check_csv2 x0, 1f
mov x0, #ERRATA_APPLIES
ret
1:
# if WORKAROUND_CVE_2022_23960
mov x0, #ERRATA_APPLIES
# else
mov x0, #ERRATA_MISSING
# endif /* WORKAROUND_CVE_2022_23960 */
ret
#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */
mov x0, #ERRATA_MISSING
ret
endfunc check_errata_cve_2022_23960
func check_smccc_arch_workaround_3
mov x0, #ERRATA_APPLIES
ret
endfunc check_smccc_arch_workaround_3
#if REPORT_ERRATA
/*
* Errata printing function for Cortex A75. Must follow AAPCS.
*/
func cortex_a73_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
mov x8, x0
/*
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata ERRATA_A73_852427, cortex_a73, 852427
report_errata ERRATA_A73_855423, cortex_a73, 855423
report_errata WORKAROUND_CVE_2017_5715, cortex_a73, cve_2017_5715
report_errata WORKAROUND_CVE_2018_3639, cortex_a73, cve_2018_3639
report_errata WORKAROUND_CVE_2022_23960, cortex_a73, cve_2022_23960
ldp x8, x30, [sp], #16
ret
endfunc cortex_a73_errata_report
#endif
/* --------------------------------------------- /* ---------------------------------------------
* This function provides cortex_a73 specific * This function provides cortex_a73 specific
@ -298,7 +201,7 @@ endfunc cortex_a73_cpu_reg_dump
declare_cpu_ops_wa cortex_a73, CORTEX_A73_MIDR, \ declare_cpu_ops_wa cortex_a73, CORTEX_A73_MIDR, \
cortex_a73_reset_func, \ cortex_a73_reset_func, \
check_errata_cve_2017_5715, \ check_erratum_cortex_a73_5715, \
CPU_NO_EXTRA2_FUNC, \ CPU_NO_EXTRA2_FUNC, \
check_smccc_arch_workaround_3, \ check_smccc_arch_workaround_3, \
cortex_a73_core_pwr_dwn, \ cortex_a73_core_pwr_dwn, \

158
lib/cpus/aarch64/cortex_x3.S
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2021-2022, Arm Limited. All rights reserved. * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -26,141 +26,51 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3 wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3
#endif /* WORKAROUND_CVE_2022_23960 */ #endif /* WORKAROUND_CVE_2022_23960 */
/* ---------------------------------------------------- workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
* HW will do the cache maintenance while powering down sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36
* ---------------------------------------------------- workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB
*/
func cortex_x3_core_pwr_dwn
#if ERRATA_X3_2313909
mov x15, x30
bl cpu_get_rev_var
bl errata_cortex_x3_2313909_wa
mov x30, x15
#endif /* ERRATA_X3_2313909 */
/* --------------------------------------------------- check_erratum_ls cortex_x3, ERRATUM(2313909), CPU_REV(1, 0)
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
mrs x0, CORTEX_X3_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr CORTEX_X3_CPUPWRCTLR_EL1, x0
isb
ret
endfunc cortex_x3_core_pwr_dwn
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif
ret
endfunc check_errata_cve_2022_23960
func cortex_x3_reset_func
mov x19, x30
/* Disable speculative loads */
msr SSBS, xzr
#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
/*
* The Cortex-X3 generic vectors are overridden to apply
* errata mitigation on exception entry from lower ELs.
*/
adr x0, wa_cve_vbar_cortex_x3
msr vbar_el3, x0
#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
bl cpu_get_rev_var
#if ERRATA_X3_2615812
bl errata_cortex_x3_2615812_wa
#endif /* ERRATA_X3_2615812 */
isb
ret x19
endfunc cortex_x3_reset_func
/* ----------------------------------------------------------------------
* Errata Workaround for Cortex-X3 Erratum 2313909 on power down request.
* This applies to revision r0p0 and r1p0 of Cortex-X3. Fixed in r1p1.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x1, x17
* ----------------------------------------------------------------------
*/
func errata_cortex_x3_2313909_wa
/* Check revision. */
mov x17, x30
bl check_errata_2313909
cbz x0, 1f
/* Set bit 36 in ACTLR2_EL1 */
mrs x1, CORTEX_X3_CPUACTLR2_EL1
orr x1, x1, #CORTEX_X3_CPUACTLR2_EL1_BIT_36
msr CORTEX_X3_CPUACTLR2_EL1, x1
1:
ret x17
endfunc errata_cortex_x3_2313909_wa
func check_errata_2313909
/* Applies to r0p0 and r1p0 */
mov x1, #0x10
b cpu_rev_var_ls
endfunc check_errata_2313909
/* ----------------------------------------------------------------------
* Errata Workaround for Cortex-X3 Erratum 2615812 on power-on.
* This applies to revision r0p0, r1p0, r1p1 of Cortex-X3. Open.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x1, x17
* ----------------------------------------------------------------------
*/
func errata_cortex_x3_2615812_wa
/* Check revision. */
mov x17, x30
bl check_errata_2615812
cbz x0, 1f
workaround_reset_start cortex_x3, ERRATUM(2615812), ERRATA_X3_2615812
/* Disable retention control for WFI and WFE. */ /* Disable retention control for WFI and WFE. */
mrs x0, CORTEX_X3_CPUPWRCTLR_EL1 mrs x0, CORTEX_X3_CPUPWRCTLR_EL1
bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3
bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3
msr CORTEX_X3_CPUPWRCTLR_EL1, x0 msr CORTEX_X3_CPUPWRCTLR_EL1, x0
1: workaround_reset_end cortex_x3, ERRATUM(2615812)
ret x17
endfunc errata_cortex_x3_2615812_wa
func check_errata_2615812 check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1)
/* Applies to r1p1 and below. */
mov x1, #0x11
b cpu_rev_var_ls
endfunc check_errata_2615812
#if REPORT_ERRATA workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
/* #if IMAGE_BL31
* Errata printing function for Cortex-X3. Must follow AAPCS. override_vector_table wa_cve_vbar_cortex_x3
#endif /* IMAGE_BL31 */
workaround_reset_end cortex_x3, CVE(2022, 23960)
check_erratum_chosen cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
cpu_reset_func_start cortex_x3
/* Disable speculative loads */
msr SSBS, xzr
cpu_reset_func_end cortex_x3
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
*/ */
func cortex_x3_errata_report func cortex_x3_core_pwr_dwn
stp x8, x30, [sp, #-16]! apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
/* ---------------------------------------------------
bl cpu_get_rev_var * Enable CPU power down bit in power control register
mov x8, x0 * ---------------------------------------------------
/*
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/ */
report_errata ERRATA_X3_2313909, cortex_x3, 2313909 sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
report_errata ERRATA_X3_2615812, cortex_x3, 2615812 isb
report_errata WORKAROUND_CVE_2022_23960, cortex_x3, cve_2022_23960
ldp x8, x30, [sp], #16
ret ret
endfunc cortex_x3_errata_report endfunc cortex_x3_core_pwr_dwn
#endif
errata_report_shim cortex_x3
/* --------------------------------------------- /* ---------------------------------------------
* This function provides Cortex-X3- * This function provides Cortex-X3-