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feat(st-gpio): add set GPIO config API

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Add get and set GPIO level from bank and pin value.
Add functions to set a pad in GPIO configuration
and to apply some settings.

Change-Id: I5e3acb5c95cd03f3e130e1a263b221b956cb3c8d
Signed-off-by: Pascal Paillet <p.paillet@st.com>
This commit is contained in:
Pascal Paillet 2022-02-17 17:22:04 +01:00 • committed by Yann Gautier
parent 5c457689b2
commit bfa5f61b57
2 changed files with 84 additions and 2 deletions
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73
drivers/st/gpio/stm32_gpio.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2022, STMicroelectronics - All Rights Reserved
* Copyright (c) 2016-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -321,3 +321,74 @@ void set_gpio_reset_cfg(uint32_t bank, uint32_t pin)
GPIO_ALTERNATE_(0), DT_DISABLED);
set_gpio_secure_cfg(bank, pin, stm32_gpio_is_secure_at_reset(bank));
}
void set_gpio_level(uint32_t bank, uint32_t pin, enum gpio_level level)
{
uintptr_t base = stm32_get_gpio_bank_base(bank);
unsigned long clock = stm32_get_gpio_bank_clock(bank);
assert(pin <= GPIO_PIN_MAX);
clk_enable(clock);
if (level == GPIO_LEVEL_HIGH) {
mmio_write_32(base + GPIO_BSRR_OFFSET, BIT(pin));
} else {
mmio_write_32(base + GPIO_BSRR_OFFSET, BIT(pin + 16U));
}
VERBOSE("GPIO %u level set to 0x%x\n", bank,
mmio_read_32(base + GPIO_IDR_OFFSET));
clk_disable(clock);
}
enum gpio_level get_gpio_level(uint32_t bank, uint32_t pin)
{
uintptr_t base = stm32_get_gpio_bank_base(bank);
unsigned long clock = stm32_get_gpio_bank_clock(bank);
enum gpio_level level = GPIO_LEVEL_LOW;
assert(pin <= GPIO_PIN_MAX);
clk_enable(clock);
if (mmio_read_32(base + GPIO_IDR_OFFSET) & BIT(pin)) {
level = GPIO_LEVEL_HIGH;
}
VERBOSE("GPIO %u get level 0x%x\n", bank,
mmio_read_32(base + GPIO_IDR_OFFSET));
clk_disable(clock);
return level;
}
void set_gpio_config(uint32_t bank, uint32_t pin, uint32_t config, uint8_t status)
{
uint32_t mode = GPIO_MODE_OUTPUT;
uint32_t od = 0U;
uint32_t pull = GPIO_NO_PULL;
VERBOSE("GPIO %u:%u set config to 0x%x\n", bank, pin, config);
if (config & GPIOF_DIR_IN) {
mode = GPIO_MODE_INPUT;
}
if (config & GPIOF_OUT_INIT_HIGH) {
od = 1U;
}
if (config & GPIOF_PULL_UP) {
pull |= GPIO_PULL_UP;
}
if (config & GPIOF_PULL_DOWN) {
pull |= GPIO_PULL_DOWN;
}
set_gpio(bank, pin, mode, GPIO_TYPE_PUSH_PULL, GPIO_SPEED_LOW,
pull, od, GPIO_ALTERNATE_(0), status);
}

13
include/drivers/st/stm32_gpio.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2022, STMicroelectronics - All Rights Reserved
* Copyright (c) 2015-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -13,6 +13,7 @@
#define GPIO_TYPE_OFFSET U(0x04)
#define GPIO_SPEED_OFFSET U(0x08)
#define GPIO_PUPD_OFFSET U(0x0C)
#define GPIO_IDR_OFFSET U(0x10)
#define GPIO_OD_OFFSET U(0x14)
#define GPIO_BSRR_OFFSET U(0x18)
#define GPIO_AFRL_OFFSET U(0x20)
@ -58,6 +59,16 @@
int dt_set_pinctrl_config(int node);
void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure);
void set_gpio_reset_cfg(uint32_t bank, uint32_t pin);
enum gpio_level {
GPIO_LEVEL_LOW,
GPIO_LEVEL_HIGH
};
void set_gpio_level(uint32_t bank, uint32_t pin, enum gpio_level level);
enum gpio_level get_gpio_level(uint32_t bank, uint32_t pin);
void set_gpio_config(uint32_t bank, uint32_t pin, uint32_t config, uint8_t status);
#endif /*__ASSEMBLER__*/
#endif /* STM32_GPIO_H */