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Merge changes from topic "xilinx-console-sync" into integration

Browse source 
* changes:
  fix(xilinx): remove console error message
  feat(xilinx): sync macro names
  feat(xilinx): remove crash console unused macros
This commit is contained in:
Joanna Farley 2023-10-03 09:31:29 +02:00 • committed by TrustedFirmware Code Review
commit be3e0b896f
9 changed files with 47 additions and 54 deletions
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12
plat/xilinx/versal/bl31_versal_setup.c
View file

@ -74,12 +74,12 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
enum pm_ret_status ret_status;
uint64_t addr[HANDOFF_PARAMS_MAX_SIZE];
if (VERSAL_CONSOLE_IS(pl011) || (VERSAL_CONSOLE_IS(pl011_1))) {
if (CONSOLE_IS(pl011) || (CONSOLE_IS(pl011_1))) {
static console_t versal_runtime_console;
/* Initialize the console to provide early debug support */
int32_t rc = console_pl011_register((uintptr_t)VERSAL_UART_BASE,
(uint32_t)VERSAL_UART_CLOCK,
(uint32_t)VERSAL_UART_BAUDRATE,
int32_t rc = console_pl011_register((uintptr_t)UART_BASE,
(uint32_t)UART_CLOCK,
(uint32_t)UART_BAUDRATE,
&versal_runtime_console);
if (rc == 0) {
panic();
@ -87,14 +87,14 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
console_set_scope(&versal_runtime_console, (uint32_t)(CONSOLE_FLAG_BOOT |
CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH));
} else if (VERSAL_CONSOLE_IS(dcc)) {
} else if (CONSOLE_IS(dcc)) {
/* Initialize the dcc console for debug */
int32_t rc = console_dcc_register();
if (rc == 0) {
panic();
}
} else {
NOTICE("BL31: Did not register for any console.\n");
/* No console device found. */
}
/* Initialize the platform config for future decision making */

30
plat/xilinx/versal/include/versal_def.h
View file

@ -23,7 +23,7 @@
#define VERSAL_CONSOLE_ID_pl011_1 2
#define VERSAL_CONSOLE_ID_dcc 3
#define VERSAL_CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE)
#define CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE)
/* List all supported platforms */
#define VERSAL_PLATFORM_ID_versal_virt 1
@ -63,40 +63,36 @@
#define VERSAL_UART0_BASE 0xFF000000
#define VERSAL_UART1_BASE 0xFF010000
#if VERSAL_CONSOLE_IS(pl011) || VERSAL_CONSOLE_IS(dcc)
# define VERSAL_UART_BASE VERSAL_UART0_BASE
#elif VERSAL_CONSOLE_IS(pl011_1)
# define VERSAL_UART_BASE VERSAL_UART1_BASE
#if CONSOLE_IS(pl011) || CONSOLE_IS(dcc)
# define UART_BASE VERSAL_UART0_BASE
#elif CONSOLE_IS(pl011_1)
# define UART_BASE VERSAL_UART1_BASE
#else
# error "invalid VERSAL_CONSOLE"
#endif
#define PLAT_VERSAL_CRASH_UART_BASE VERSAL_UART_BASE
#define PLAT_VERSAL_CRASH_UART_CLK_IN_HZ VERSAL_UART_CLOCK
#define VERSAL_CONSOLE_BAUDRATE VERSAL_UART_BAUDRATE
/*******************************************************************************
* Platform related constants
******************************************************************************/
#if VERSAL_PLATFORM_IS(versal_virt)
# define PLATFORM_NAME "Versal Virt"
# define VERSAL_UART_CLOCK 25000000
# define VERSAL_UART_BAUDRATE 115200
# define UART_CLOCK 25000000
# define UART_BAUDRATE 115200
# define VERSAL_CPU_CLOCK 2720000
#elif VERSAL_PLATFORM_IS(silicon)
# define PLATFORM_NAME "Versal Silicon"
# define VERSAL_UART_CLOCK 100000000
# define VERSAL_UART_BAUDRATE 115200
# define UART_CLOCK 100000000
# define UART_BAUDRATE 115200
# define VERSAL_CPU_CLOCK 100000000
#elif VERSAL_PLATFORM_IS(spp_itr6)
# define PLATFORM_NAME "SPP ITR6"
# define VERSAL_UART_CLOCK 25000000
# define VERSAL_UART_BAUDRATE 115200
# define UART_CLOCK 25000000
# define UART_BAUDRATE 115200
# define VERSAL_CPU_CLOCK 2720000
#elif VERSAL_PLATFORM_IS(emu_itr6)
# define PLATFORM_NAME "EMU ITR6"
# define VERSAL_UART_CLOCK 212000
# define VERSAL_UART_BAUDRATE 9600
# define UART_CLOCK 212000
# define UART_BAUDRATE 9600
# define VERSAL_CPU_CLOCK 212000
#endif

10
plat/xilinx/versal_net/bl31_versal_net_setup.c
View file

@ -101,12 +101,12 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
panic();
}
if (VERSAL_NET_CONSOLE_IS(pl011_0) || VERSAL_NET_CONSOLE_IS(pl011_1)) {
if (CONSOLE_IS(pl011_0) || CONSOLE_IS(pl011_1)) {
static console_t versal_net_runtime_console;
/* Initialize the console to provide early debug support */
rc = console_pl011_register(VERSAL_NET_UART_BASE, uart_clock,
VERSAL_NET_UART_BAUDRATE,
rc = console_pl011_register(UART_BASE, uart_clock,
UART_BAUDATE,
&versal_net_runtime_console);
if (rc == 0) {
panic();
@ -114,7 +114,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
console_set_scope(&versal_net_runtime_console, CONSOLE_FLAG_BOOT |
CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
} else if (VERSAL_NET_CONSOLE_IS(dcc)) {
} else if (CONSOLE_IS(dcc)) {
/* Initialize the dcc console for debug.
* dcc is over jtag and does not configures uart0 or uart1.
*/
@ -122,6 +122,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
if (rc == 0) {
panic();
}
} else {
/* No console device found. */
}
NOTICE("TF-A running on %s %d.%d\n", board_name_decode(),

12
plat/xilinx/versal_net/include/versal_net_def.h
View file

@ -20,7 +20,7 @@
#define VERSAL_NET_CONSOLE_ID_pl011_1 U(2)
#define VERSAL_NET_CONSOLE_ID_dcc U(3)
#define VERSAL_NET_CONSOLE_IS(con) (VERSAL_NET_CONSOLE_ID_ ## con == VERSAL_NET_CONSOLE)
#define CONSOLE_IS(con) (VERSAL_NET_CONSOLE_ID_ ## con == VERSAL_NET_CONSOLE)
/* List all platforms */
#define VERSAL_NET_SILICON U(0)
@ -135,17 +135,15 @@
#define VERSAL_NET_UART0_BASE U(0xF1920000)
#define VERSAL_NET_UART1_BASE U(0xF1930000)
#define VERSAL_NET_UART_BAUDRATE 115200
#define UART_BAUDATE 115200
#if VERSAL_NET_CONSOLE_IS(pl011_1)
#define VERSAL_NET_UART_BASE VERSAL_NET_UART1_BASE
#if CONSOLE_IS(pl011_1)
#define UART_BASE VERSAL_NET_UART1_BASE
#else
/* Default console is UART0 */
#define VERSAL_NET_UART_BASE VERSAL_NET_UART0_BASE
#define UART_BASE VERSAL_NET_UART0_BASE
#endif
#define VERSAL_NET_CONSOLE_BAUDRATE VERSAL_NET_UART_BAUDRATE
/* Processor core device IDs */
#define PM_DEV_CLUSTER0_ACPU_0 (0x1810C0AFU)
#define PM_DEV_CLUSTER0_ACPU_1 (0x1810C0B0U)

2
plat/xilinx/zynqmp/aarch64/zynqmp_common.c
View file

@ -48,7 +48,7 @@ static uint32_t zynqmp_get_silicon_ver(void)
return ver;
}
uint32_t zynqmp_get_uart_clk(void)
uint32_t get_uart_clk(void)
{
unsigned int ver = zynqmp_get_silicon_ver();

12
plat/xilinx/zynqmp/bl31_zynqmp_setup.c
View file

@ -73,24 +73,24 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
{
uint64_t tfa_handoff_addr;
if (ZYNQMP_CONSOLE_IS(cadence) || (ZYNQMP_CONSOLE_IS(cadence1))) {
if (CONSOLE_IS(cadence) || (CONSOLE_IS(cadence1))) {
/* Register the console to provide early debug support */
static console_t bl31_boot_console;
(void)console_cdns_register(ZYNQMP_UART_BASE,
zynqmp_get_uart_clk(),
ZYNQMP_UART_BAUDRATE,
(void)console_cdns_register(UART_BASE,
get_uart_clk(),
UART_BAUDRATE,
&bl31_boot_console);
console_set_scope(&bl31_boot_console,
CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT |
CONSOLE_FLAG_CRASH);
} else if (ZYNQMP_CONSOLE_IS(dcc)) {
} else if (CONSOLE_IS(dcc)) {
/* Initialize the dcc console for debug */
int32_t rc = console_dcc_register();
if (rc == 0) {
panic();
}
} else {
ERROR("BL31: No console device found.\n");
/* No console device found. */
}
/* Initialize the platform config for future decision making */
zynqmp_config_setup();

2
plat/xilinx/zynqmp/include/plat_private.h
View file

@ -19,7 +19,7 @@ void zynqmp_config_setup(void);
uint32_t zynqmp_calc_core_pos(u_register_t mpidr);
/* ZynqMP specific functions */
uint32_t zynqmp_get_uart_clk(void);
uint32_t get_uart_clk(void);
uint32_t zynqmp_get_bootmode(void);
#if ZYNQMP_WDT_RESTART

15
plat/xilinx/zynqmp/include/zynqmp_def.h
View file

@ -15,7 +15,7 @@
#define ZYNQMP_CONSOLE_ID_cadence1 2
#define ZYNQMP_CONSOLE_ID_dcc 3
#define ZYNQMP_CONSOLE_IS(con) (ZYNQMP_CONSOLE_ID_ ## con == ZYNQMP_CONSOLE)
#define CONSOLE_IS(con) (ZYNQMP_CONSOLE_ID_ ## con == ZYNQMP_CONSOLE)
/* Default counter frequency */
#define ZYNQMP_DEFAULT_COUNTER_FREQ 0U
@ -144,19 +144,16 @@
#define ZYNQMP_UART0_BASE U(0xFF000000)
#define ZYNQMP_UART1_BASE U(0xFF010000)
#if ZYNQMP_CONSOLE_IS(cadence) || ZYNQMP_CONSOLE_IS(dcc)
# define ZYNQMP_UART_BASE ZYNQMP_UART0_BASE
#elif ZYNQMP_CONSOLE_IS(cadence1)
# define ZYNQMP_UART_BASE ZYNQMP_UART1_BASE
#if CONSOLE_IS(cadence) || CONSOLE_IS(dcc)
# define UART_BASE ZYNQMP_UART0_BASE
#elif CONSOLE_IS(cadence1)
# define UART_BASE ZYNQMP_UART1_BASE
#else
# error "invalid ZYNQMP_CONSOLE"
#endif
#define ZYNQMP_CRASH_UART_BASE ZYNQMP_UART_BASE
/* impossible to call C routine how it is done now - hardcode any value */
#define ZYNQMP_CRASH_UART_CLK_IN_HZ 100000000 /* FIXME */
/* Must be non zero */
#define ZYNQMP_UART_BAUDRATE 115200
#define UART_BAUDRATE 115200
/* Silicon version detection */
#define ZYNQMP_SILICON_VER_MASK 0xF000

6
plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
View file

@ -22,9 +22,9 @@ void tsp_early_platform_setup(void)
* messages from TSP
*/
static console_t tsp_boot_console;
(void)console_cdns_register(ZYNQMP_UART_BASE,
zynqmp_get_uart_clk(),
ZYNQMP_UART_BAUDRATE,
(void)console_cdns_register(UART_BASE,
get_uart_clk(),
UART_BAUDRATE,
&tsp_boot_console);
console_set_scope(&tsp_boot_console,
CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT);