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Merge changes from topic "rd-v3-reset-to-bl31" into integration

Browse source 
* changes:
  feat(neoverse-rd): allow RESET_TO_BL31 for third gen platforms
  feat(arm): setup GPT in BL31 in RESET_TO_BL31 boot flow
  feat(neoverse-rd): enable RESET_TO_BL31 for RD-V3
  feat(neoverse-rd): add a routine to update NT_FW_CONFIG in BL31
This commit is contained in:
Madhukar Pappireddy 2024-09-26 21:23:43 +02:00 • committed by TrustedFirmware Code Review
commit bcce173da3
13 changed files with 260 additions and 8 deletions
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14
plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h
View file

@ -111,4 +111,18 @@
ARM_REALM_SIZE, \
MT_MEMORY | MT_RW | MT_REALM)
#if RESET_TO_BL31
/*******************************************************************************
* BL31 specific defines.
******************************************************************************/
/* Define the DTB image base and size */
#define NRD_CSS_BL31_PRELOAD_DTB_BASE UL(0xF3000000)
#define NRD_CSS_BL31_PRELOAD_DTB_SIZE UL(0x1000)
#define NRD_CSS_MAP_BL31_DTB MAP_REGION_FLAT( \
NRD_CSS_BL31_PRELOAD_DTB_BASE, \
NRD_CSS_BL31_PRELOAD_DTB_SIZE, \
MT_RW_DATA | MT_NS)
#endif /* RESET_TO_BL31 */
#endif /* NRD_CSS_FW_DEF3_H */

34
plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h
View file

@ -56,8 +56,8 @@
* chips are accessed - secure ram, css device and soc device regions.
*/
#if defined(IMAGE_BL31)
# define PLAT_ARM_MMAP_ENTRIES (9 + ((NRD_CHIP_COUNT - 1) * 3))
# define MAX_XLAT_TABLES (9 + ((NRD_CHIP_COUNT - 1) * 3))
# define PLAT_ARM_MMAP_ENTRIES (10 + ((NRD_CHIP_COUNT - 1) * 3))
# define MAX_XLAT_TABLES (10 + ((NRD_CHIP_COUNT - 1) * 3))
#elif defined(IMAGE_BL32)
# define PLAT_ARM_MMAP_ENTRIES U(8)
# define MAX_XLAT_TABLES U(5)
@ -442,7 +442,7 @@
* SRAM layout
******************************************************************************/
/*
/* if !RESET_TO_BL31
* Trusted SRAM
* 0x00100000 +--------------+
* | L0 GPT |
@ -460,6 +460,26 @@
* 0x00019000 +--------------+
* | BL1 (ro) |
* 0x00000000 +--------------+
*
* else
*
* Trusted SRAM
* 0x00100000 +--------------+
* | L0 GPT |
* 0x000E0000 +--------------
* | | side-loaded +----------------+
* | | <<<<<<<<<<<<< | |
* | | <<<<<<<<<<<<< | BL31 NOBITS |
* | | <<<<<<<<<<<<< | |
* | | <<<<<<<<<<<<< |----------------|
* | | <<<<<<<<<<<<< | BL31 PROGBITS |
* 0x00063000 | | +----------------+
* 0x0001A000 +--------------+
* | Shared |
* 0x00019000 +--------------+
* | BL1 (ro) |
* 0x00000000 +--------------+
* endif
*/
/*******************************************************************************
@ -531,7 +551,11 @@
* ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory
*/
#define ARM_FW_CONFIGS_SIZE (PAGE_SIZE * 2)
#if RESET_TO_BL31
#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE)
#else
#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + ARM_FW_CONFIGS_SIZE)
#endif
/*******************************************************************************
* BL1 RW specifics
@ -556,9 +580,13 @@
******************************************************************************/
/* Keep BL31 below BL2 in the Trusted SRAM.*/
#if RESET_TO_BL31
#define BL31_BASE (0x63000)
#else
#define BL31_BASE ((ARM_BL_RAM_BASE + \
ARM_BL_RAM_SIZE) - \
PLAT_ARM_MAX_BL31_SIZE)
#endif
#define BL31_PROGBITS_LIMIT BL2_BASE
#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)

5
plat/arm/board/neoverse_rd/common/nrd-common.mk
View file

@ -54,11 +54,6 @@ BL31_SOURCES += ${INTERCONNECT_SOURCES} \
${NRD_COMMON_BASE}/nrd_topology.c \
drivers/delay_timer/generic_delay_timer.c
ifneq (${RESET_TO_BL31},0)
$(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
Please set RESET_TO_BL31 to 0.")
endif
$(eval $(call add_define,NRD_CHIP_COUNT))
$(eval $(call add_define,NRD_PLATFORM_VARIANT))

68
plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
View file

@ -155,6 +155,65 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
}
/*******************************************************************************
* This function inserts platform information via device tree nodes as,
* system-id {
* platform-id = <0>;
* config-id = <0>;
* }
******************************************************************************/
#if RESET_TO_BL31
static int append_config_node(uintptr_t fdt_base_addr, uintptr_t fdt_base_size)
{
void *fdt;
int nodeoffset, err;
unsigned int platid = 0, platcfg = 0;
if (fdt_base_addr == 0) {
ERROR("NT_FW CONFIG base address is NULL\n");
return -1;
}
fdt = (void *)fdt_base_addr;
/* Check the validity of the fdt */
if (fdt_check_header(fdt) != 0) {
ERROR("Invalid NT_FW_CONFIG DTB passed\n");
return -1;
}
nodeoffset = fdt_subnode_offset(fdt, 0, "system-id");
if (nodeoffset < 0) {
ERROR("Failed to get system-id node offset\n");
return -1;
}
platid = plat_arm_nrd_get_platform_id();
err = fdt_setprop_u32(fdt, nodeoffset, "platform-id", platid);
if (err < 0) {
ERROR("Failed to set platform-id\n");
return -1;
}
platcfg = plat_arm_nrd_get_config_id();
err = fdt_setprop_u32(fdt, nodeoffset, "config-id", platcfg);
if (err < 0) {
ERROR("Failed to set config-id\n");
return -1;
}
platcfg = plat_arm_nrd_get_multi_chip_mode();
err = fdt_setprop_u32(fdt, nodeoffset, "multi-chip-mode", platcfg);
if (err < 0) {
ERROR("Failed to set multi-chip-mode\n");
return -1;
}
flush_dcache_range((uintptr_t)fdt, fdt_base_size);
return 0;
}
#endif
void nrd_bl31_common_platform_setup(void)
{
generic_delay_timer_init();
@ -169,6 +228,15 @@ void nrd_bl31_common_platform_setup(void)
ehf_register_priority_handler(PLAT_REBOOT_PRI,
css_reboot_interrupt_handler);
#endif
#if RESET_TO_BL31
int ret = append_config_node(NRD_CSS_BL31_PRELOAD_DTB_BASE,
NRD_CSS_BL31_PRELOAD_DTB_SIZE);
if (ret != 0) {
panic();
}
#endif
}
const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)

3
plat/arm/board/neoverse_rd/common/nrd_plat3.c
View file

@ -60,6 +60,9 @@ const mmap_region_t plat_arm_mmap[] = {
NRD_CSS_GPT_L1_DRAM_MMAP,
NRD_CSS_EL3_RMM_SHARED_MEM_MMAP,
NRD_CSS_GPC_SMMU_SMMUV3_MMAP,
#if RESET_TO_BL31
NRD_CSS_MAP_BL31_DTB,
#endif
{0}
};
#endif /* IMAGE_BL31 */

5
plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk
View file

@ -71,6 +71,11 @@ ifneq ($(NRD_PLATFORM_VARIANT),0)
currently set to ${NRD_PLATFORM_VARIANT}.")
endif
ifneq (${RESET_TO_BL31},0)
$(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
Please set RESET_TO_BL31 to 0.")
endif
override CTX_INCLUDE_AARCH32_REGS := 0
override SPMD_SPM_AT_SEL2 := 0

5
plat/arm/board/neoverse_rd/platform/rdn2/platform.mk
View file

@ -103,6 +103,11 @@ TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${STMM_CONFIG_DTS})).dt
$(eval $(call TOOL_ADD_PAYLOAD,${TOS_FW_CONFIG},--tos-fw-config,${TOS_FW_CONFIG}))
endif
ifneq (${RESET_TO_BL31},0)
$(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
Please set RESET_TO_BL31 to 0.")
endif
override CTX_INCLUDE_AARCH32_REGS := 0
override ENABLE_FEAT_AMU := 2
override ENABLE_FEAT_MTE2 := 2

5
plat/arm/board/neoverse_rd/platform/rdv1/platform.mk
View file

@ -66,5 +66,10 @@ ifneq ($(NRD_PLATFORM_VARIANT),0)
currently set to ${NRD_PLATFORM_VARIANT}.")
endif
ifneq (${RESET_TO_BL31},0)
$(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
Please set RESET_TO_BL31 to 0.")
endif
# Enable the flag since RD-V1 has a system level cache
NEOVERSE_Nx_EXTERNAL_LLC := 1

5
plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk
View file

@ -77,5 +77,10 @@ ifneq ($(NRD_PLATFORM_VARIANT),0)
currently set to ${NRD_PLATFORM_VARIANT}.")
endif
ifneq (${RESET_TO_BL31},0)
$(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
Please set RESET_TO_BL31 to 0.")
endif
# Enable the flag since RD-V1-MC has a system level cache
NEOVERSE_Nx_EXTERNAL_LLC := 1

22
plat/arm/board/neoverse_rd/platform/rdv3/platform.mk
View file

@ -24,6 +24,24 @@ override ARM_ARCH_MINOR := 7
# Misc options
override CTX_INCLUDE_AARCH32_REGS := 0
ifeq (${PLAT_RESET_TO_BL31}, 1)
# Support for BL31 boot flow
override RESET_TO_BL31 := 1
# arm_common.mk sets ENABLE_PIE=1, but Makefile blocks PIE for RME
override ENABLE_PIE := 0
# Non Trusted Firmware parameters
override ARM_PRELOADED_DTB_BASE := 0xF3000000
override ARM_LINUX_KERNEL_AS_BL33 := 1
override PRELOADED_BL33_BASE := 0xE0000000
# These are internal build flags but as of now RESET_TO_BL31 won't work without defining them
override NEED_BL1 := no
override NEED_BL2 := no
override NEED_BL32 := no
endif
# RD-V3 platform uses GIC-700 which is based on GICv4.1
GIC_ENABLE_V4_EXTN := 1
@ -86,6 +104,10 @@ BL2_SOURCES += ${PLAT_MEASURED_BOOT_SOURCES} \
${RDV3_BASE}/rdv3_bl2_measured_boot.c
endif
ifeq (${PLAT_RESET_TO_BL31}, 1)
BL31_SOURCES += ${RDV3_BASE}/rdv3_security.c
endif
BL31_SOURCES += ${NRD_CPU_SOURCES} \
${MBEDTLS_SOURCES} \
${RSE_COMMS_SOURCES} \

89
plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl31_setup.c
View file

@ -130,3 +130,92 @@ void bl31_platform_setup(void)
WARN("Failed initializing AP-RSE comms.\n");
}
}
#if RESET_TO_BL31
/*
* The GPT library might modify the gpt regions structure to optimize
* the layout, so the array cannot be constant.
*/
static pas_region_t pas_regions[] = {
NRD_PAS_SHARED_SRAM,
NRD_PAS_SYSTEM_NCI,
NRD_PAS_DEBUG_NIC,
NRD_PAS_NS_UART,
NRD_PAS_REALM_UART,
NRD_PAS_AP_NS_WDOG,
NRD_PAS_AP_ROOT_WDOG,
NRD_PAS_AP_SECURE_WDOG,
NRD_PAS_SECURE_SRAM_ERB_AP,
NRD_PAS_NS_SRAM_ERB_AP,
NRD_PAS_ROOT_SRAM_ERB_AP,
NRD_PAS_REALM_SRAM_ERB_AP,
NRD_PAS_SECURE_SRAM_ERB_SCP,
NRD_PAS_NS_SRAM_ERB_SCP,
NRD_PAS_ROOT_SRAM_ERB_SCP,
NRD_PAS_REALM_SRAM_ERB_SCP,
NRD_PAS_SECURE_SRAM_ERB_MCP,
NRD_PAS_NS_SRAM_ERB_MCP,
NRD_PAS_ROOT_SRAM_ERB_MCP,
NRD_PAS_REALM_SRAM_ERB_MCP,
NRD_PAS_SECURE_SRAM_ERB_RSE,
NRD_PAS_NS_SRAM_ERB_RSE,
NRD_PAS_ROOT_SRAM_ERB_RSE,
NRD_PAS_REALM_SRAM_ERB_RSE,
NRD_PAS_RSE_SECURE_SRAM_ERB_RSM,
NRD_PAS_RSE_NS_SRAM_ERB_RSM,
NRD_PAS_SCP_SECURE_SRAM_ERB_RSM,
NRD_PAS_SCP_NS_SRAM_ERB_RSM,
NRD_PAS_MCP_SECURE_SRAM_ERB_RSM,
NRD_PAS_MCP_NS_SRAM_ERB_RSM,
NRD_PAS_AP_SCP_ROOT_MHU,
NRD_PAS_AP_MCP_NS_MHU,
NRD_PAS_AP_MCP_SECURE_MHU,
NRD_PAS_AP_MCP_ROOT_MHU,
NRD_PAS_AP_RSE_NS_MHU,
NRD_PAS_AP_RSE_SECURE_MHU,
NRD_PAS_AP_RSE_ROOT_MHU,
NRD_PAS_AP_RSE_REALM_MHU,
NRD_PAS_SCP_MCP_RSE_CROSS_CHIP_MHU,
NRD_PAS_SYNCNT_MSTUPDTVAL_ADDR,
NRD_PAS_STM_SYSTEM_ITS,
NRD_PAS_SCP_MCP_RSE_SHARED_SRAM,
NRD_PAS_GIC,
NRD_PAS_NS_DRAM,
NRD_PAS_RMM,
NRD_PAS_L1GPT,
NRD_PAS_CMN,
NRD_PAS_LCP_PERIPHERAL,
NRD_PAS_DDR_IO,
NRD_PAS_SMMU_NCI_IO,
NRD_PAS_DRAM2_CHIP0,
#if NRD_CHIP_COUNT > 1
NRD_PAS_DRAM1_CHIP1,
NRD_PAS_DRAM2_CHIP1,
#endif
#if NRD_CHIP_COUNT > 2
NRD_PAS_DRAM1_CHIP2,
NRD_PAS_DRAM2_CHIP2,
#endif
#if NRD_CHIP_COUNT > 3
NRD_PAS_DRAM1_CHIP3,
NRD_PAS_DRAM2_CHIP3
#endif
};
static const arm_gpt_info_t arm_gpt_info = {
.pas_region_base = pas_regions,
.pas_region_count = (unsigned int)ARRAY_SIZE(pas_regions),
.l0_base = (uintptr_t)ARM_L0_GPT_BASE,
.l1_base = (uintptr_t)ARM_L1_GPT_BASE,
.l0_size = (size_t)ARM_L0_GPT_SIZE,
.l1_size = (size_t)ARM_L1_GPT_SIZE,
.pps = GPCCR_PPS_256TB,
.pgs = GPCCR_PGS_4K
};
const arm_gpt_info_t *plat_arm_get_gpt_info(void)
{
return &arm_gpt_info;
}
#endif /* RESET_TO_BL31 */

5
plat/arm/board/neoverse_rd/platform/sgi575/platform.mk
View file

@ -65,4 +65,9 @@ ifneq ($(NRD_PLATFORM_VARIANT),0)
currently set to ${NRD_PLATFORM_VARIANT}.")
endif
ifneq (${RESET_TO_BL31},0)
$(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
Please set RESET_TO_BL31 to 0.")
endif
override SPMD_SPM_AT_SEL2 := 0

8
plat/arm/common/arm_bl31_setup.c
View file

@ -7,6 +7,7 @@
#include <assert.h>
#include <arch.h>
#include <arch_features.h>
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
@ -544,6 +545,13 @@ void __init arm_bl31_plat_arch_setup(void)
enable_mmu_el3(0);
#if ENABLE_RME
#if RESET_TO_BL31
/* initialize GPT only when RME is enabled. */
assert(is_feat_rme_present());
/* Initialise and enable granule protection after MMU. */
arm_gpt_setup();
#endif /* RESET_TO_BL31 */
/*
* Initialise Granule Protection library and enable GPC for the primary
* processor. The tables have already been initialized by a previous BL