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chore: rename Blackhawk to Cortex-X925

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Rename Blackhawk to Cortex-X925.

Change-Id: I51e40a7bc6b8871c53c40d1f341853b1fd7fdf71
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
This commit is contained in:
Govindraj Raja 2024-05-17 13:39:07 -05:00
parent 16aacab801
commit bbe94cddc4
4 changed files with 30 additions and 30 deletions
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16
include/lib/cpus/aarch64/cortex_blackhawk.h → include/lib/cpus/aarch64/cortex_x925.h
View file

@ -1,23 +1,23 @@
/* /*
* Copyright (c) 2023, Arm Limited. All rights reserved. * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#ifndef CORTEX_BLACKHAWK_H #ifndef CORTEX_X925_H
#define CORTEX_BLACKHAWK_H #define CORTEX_X925_H
#define CORTEX_BLACKHAWK_MIDR U(0x410FD850) #define CORTEX_X925_MIDR U(0x410FD850)
/******************************************************************************* /*******************************************************************************
* CPU Extended Control register specific definitions * CPU Extended Control register specific definitions
******************************************************************************/ ******************************************************************************/
#define CORTEX_BLACKHAWK_CPUECTLR_EL1 S3_0_C15_C1_4 #define CORTEX_X925_CPUECTLR_EL1 S3_0_C15_C1_4
/******************************************************************************* /*******************************************************************************
* CPU Power Control register specific definitions * CPU Power Control register specific definitions
******************************************************************************/ ******************************************************************************/
#define CORTEX_BLACKHAWK_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_X925_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_BLACKHAWK_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) #define CORTEX_X925_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
#endif /* CORTEX_BLACKHAWK_H */ #endif /* CORTEX_X925_H */

40
lib/cpus/aarch64/cortex_blackhawk.S → lib/cpus/aarch64/cortex_x925.S
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2023, Arm Limited. All rights reserved. * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -7,43 +7,43 @@
#include <arch.h> #include <arch.h>
#include <asm_macros.S> #include <asm_macros.S>
#include <common/bl_common.h> #include <common/bl_common.h>
#include <cortex_blackhawk.h> #include <cortex_x925.h>
#include <cpu_macros.S> #include <cpu_macros.S>
#include <plat_macros.S> #include <plat_macros.S>
/* Hardware handled coherency */ /* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0 #if HW_ASSISTED_COHERENCY == 0
#error "Cortex blackhawk must be compiled with HW_ASSISTED_COHERENCY enabled" #error "Cortex-X925 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif #endif
/* 64-bit only core */ /* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1 #if CTX_INCLUDE_AARCH32_REGS == 1
#error "Cortex blackhawk supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #error "Cortex-X925 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif #endif
cpu_reset_func_start cortex_blackhawk cpu_reset_func_start cortex_x925
/* Disable speculative loads */ /* Disable speculative loads */
msr SSBS, xzr msr SSBS, xzr
cpu_reset_func_end cortex_blackhawk cpu_reset_func_end cortex_x925
/* ---------------------------------------------------- /* ----------------------------------------------------
* HW will do the cache maintenance while powering down * HW will do the cache maintenance while powering down
* ---------------------------------------------------- * ----------------------------------------------------
*/ */
func cortex_blackhawk_core_pwr_dwn func cortex_x925_core_pwr_dwn
/* --------------------------------------------------- /* ---------------------------------------------------
* Enable CPU power down bit in power control register * Enable CPU power down bit in power control register
* --------------------------------------------------- * ---------------------------------------------------
*/ */
sysreg_bit_set CORTEX_BLACKHAWK_CPUPWRCTLR_EL1, CORTEX_BLACKHAWK_CPUPWRCTLR_EL1_CORE_PWRDN_BIT sysreg_bit_set CORTEX_X925_CPUPWRCTLR_EL1, CORTEX_X925_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
isb isb
ret ret
endfunc cortex_blackhawk_core_pwr_dwn endfunc cortex_x925_core_pwr_dwn
errata_report_shim cortex_blackhawk errata_report_shim cortex_x925
/* --------------------------------------------- /* ---------------------------------------------
* This function provides Cortex Blackhawk specific * This function provides Cortex-X925 specific
* register information for crash reporting. * register information for crash reporting.
* It needs to return with x6 pointing to * It needs to return with x6 pointing to
* a list of register names in ascii and * a list of register names in ascii and
@ -51,16 +51,16 @@ errata_report_shim cortex_blackhawk
* reported. * reported.
* --------------------------------------------- * ---------------------------------------------
*/ */
.section .rodata.cortex_blackhawk_regs, "aS" .section .rodata.cortex_x925_regs, "aS"
cortex_blackhawk_regs: /* The ascii list of register names to be reported */ cortex_x925_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", "" .asciz "cpuectlr_el1", ""
func cortex_blackhawk_cpu_reg_dump func cortex_x925_cpu_reg_dump
adr x6, cortex_blackhawk_regs adr x6, cortex_x925_regs
mrs x8, CORTEX_BLACKHAWK_CPUECTLR_EL1 mrs x8, CORTEX_X925_CPUECTLR_EL1
ret ret
endfunc cortex_blackhawk_cpu_reg_dump endfunc cortex_x925_cpu_reg_dump
declare_cpu_ops cortex_blackhawk, CORTEX_BLACKHAWK_MIDR, \ declare_cpu_ops cortex_x925, CORTEX_X925_MIDR, \
cortex_blackhawk_reset_func, \ cortex_x925_reset_func, \
cortex_blackhawk_core_pwr_dwn cortex_x925_core_pwr_dwn

2
plat/arm/board/arm_fpga/platform.mk
View file

@ -78,7 +78,7 @@ else
lib/cpus/aarch64/neoverse_n2.S \ lib/cpus/aarch64/neoverse_n2.S \
lib/cpus/aarch64/neoverse_v1.S \ lib/cpus/aarch64/neoverse_v1.S \
lib/cpus/aarch64/cortex_a725.S \ lib/cpus/aarch64/cortex_a725.S \
lib/cpus/aarch64/cortex_blackhawk.S lib/cpus/aarch64/cortex_x925.S
# AArch64/AArch32 cores # AArch64/AArch32 cores
FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \

2
plat/arm/board/tc/platform.mk
View file

@ -101,7 +101,7 @@ endif
ifeq (${TARGET_PLATFORM}, 3) ifeq (${TARGET_PLATFORM}, 3)
TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a520.S \ TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a520.S \
lib/cpus/aarch64/cortex_a725.S \ lib/cpus/aarch64/cortex_a725.S \
lib/cpus/aarch64/cortex_blackhawk.S lib/cpus/aarch64/cortex_x925.S
endif endif
INTERCONNECT_SOURCES := ${TC_BASE}/tc_interconnect.c INTERCONNECT_SOURCES := ${TC_BASE}/tc_interconnect.c