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fix(spmd): relax use of EHF with SPMC at S-EL2
Follow up to [1] and [2], for systems implementing the SPMC at S-EL2, it is necessary to leave the option for handling Group0 interrupts (while the normal world runs) through the EHF by the use of the EL3_EXCEPTION_HANDLING option. Specifically for RAS, the handling through EHF is still required because the platform function provided by the SPMD doesn't provide the facility to link back to the RAS handling framework. [1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/16047 [2] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/19897 Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: Idf8741887904a286fb3f5ab2d754afd2fc78d3b0
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@ -249,6 +249,7 @@ static uint64_t spmd_secure_interrupt_handler(uint32_t id,
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SMC_RET0(&ctx->cpu_ctx);
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}
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#if (EL3_EXCEPTION_HANDLING == 0)
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/*******************************************************************************
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* spmd_group0_interrupt_handler_nwd
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* Group0 secure interrupt in the normal world are trapped to EL3. Delegate the
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@ -281,6 +282,7 @@ static uint64_t spmd_group0_interrupt_handler_nwd(uint32_t id,
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return 0U;
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}
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#endif
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/*******************************************************************************
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* spmd_handle_group0_intr_swd
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@ -560,6 +562,18 @@ static int spmd_spmc_init(void *pm_addr)
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panic();
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}
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/*
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* Permit configurations where the SPM resides at S-EL1/2 and upon a
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* Group0 interrupt triggering while the normal world runs, the
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* interrupt is routed either through the EHF or directly to the SPMD:
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*
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* EL3_EXCEPTION_HANDLING=0: the Group0 interrupt is routed to the SPMD
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* for handling by spmd_group0_interrupt_handler_nwd.
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*
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* EL3_EXCEPTION_HANDLING=1: the Group0 interrupt is routed to the EHF.
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*
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*/
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#if (EL3_EXCEPTION_HANDLING == 0)
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/*
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* Register an interrupt handler routing Group0 interrupts to SPMD
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* while the NWd is running.
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@ -570,6 +584,8 @@ static int spmd_spmc_init(void *pm_addr)
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if (rc != 0) {
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panic();
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}
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#endif
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return 0;
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}
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