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feat(debug): add AARCH32 CP15 fault registers

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For an easier debug on Aarch32, in case of abort, it is useful to access
DFSR, IFSR, DFAR and IFAR CP15 registers.

Change-Id: Ie6b5a2882cd701f76e9d455ec43bd4b0fbe3cc78
Signed-off-by: Yann Gautier <yann.gautier@st.com>
This commit is contained in:
Yann Gautier 2019-05-21 18:59:18 +02:00
parent 967d8c99f4
commit bb2289142c
1 changed files with 7 additions and 1 deletions
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8
include/arch/aarch32/arch.h
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -617,6 +617,12 @@
#define ICC_ASGI1R_EL1_64 p15, 1, c12 #define ICC_ASGI1R_EL1_64 p15, 1, c12
#define ICC_SGI0R_EL1_64 p15, 2, c12 #define ICC_SGI0R_EL1_64 p15, 2, c12
/* Fault registers. The format is: coproc, opt1, CRn, CRm, opt2 */
#define DFSR p15, 0, c5, c0, 0
#define IFSR p15, 0, c5, c0, 1
#define DFAR p15, 0, c6, c0, 0
#define IFAR p15, 0, c6, c0, 2
/******************************************************************************* /*******************************************************************************
* Definitions of MAIR encodings for device and normal memory * Definitions of MAIR encodings for device and normal memory
******************************************************************************/ ******************************************************************************/