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https://github.com/ARM-software/arm-trusted-firmware.git
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refactor(st-ddr): update parameter array initialization
Force alignment of the size of parameters array with the expected value by the binding. The registers dynamic structs are removed as not used in TF-A. Change-Id: I7a41f355a435f54fbf23f468cca87c7f8f7e69e8 Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
This commit is contained in:
Yann Gautier
parent
5def13eb01
commit
ba7d2e2698
2 changed files with 30 additions and 62 deletions
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@ -46,8 +46,21 @@ struct reg_desc {
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.par_offset = offsetof(struct y, x) \
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}
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/*
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* PARAMETERS: value get from device tree :
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* size / order need to be aligned with binding
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* modification NOT ALLOWED !!!
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*/
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#define DDRCTL_REG_REG_SIZE 25 /* st,ctl-reg */
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#define DDRCTL_REG_TIMING_SIZE 12 /* st,ctl-timing */
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#define DDRCTL_REG_MAP_SIZE 9 /* st,ctl-map */
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#define DDRCTL_REG_PERF_SIZE 17 /* st,ctl-perf */
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#define DDRPHY_REG_REG_SIZE 11 /* st,phy-reg */
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#define DDRPHY_REG_TIMING_SIZE 10 /* st,phy-timing */
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#define DDRCTL_REG_REG(x) DDRCTL_REG(x, stm32mp1_ddrctrl_reg)
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static const struct reg_desc ddr_reg[] = {
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static const struct reg_desc ddr_reg[DDRCTL_REG_REG_SIZE] = {
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DDRCTL_REG_REG(mstr),
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DDRCTL_REG_REG(mrctrl0),
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DDRCTL_REG_REG(mrctrl1),
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@ -76,7 +89,7 @@ static const struct reg_desc ddr_reg[] = {
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};
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#define DDRCTL_REG_TIMING(x) DDRCTL_REG(x, stm32mp1_ddrctrl_timing)
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static const struct reg_desc ddr_timing[] = {
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static const struct reg_desc ddr_timing[DDRCTL_REG_TIMING_SIZE] = {
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DDRCTL_REG_TIMING(rfshtmg),
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DDRCTL_REG_TIMING(dramtmg0),
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DDRCTL_REG_TIMING(dramtmg1),
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@ -92,7 +105,7 @@ static const struct reg_desc ddr_timing[] = {
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};
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#define DDRCTL_REG_MAP(x) DDRCTL_REG(x, stm32mp1_ddrctrl_map)
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static const struct reg_desc ddr_map[] = {
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static const struct reg_desc ddr_map[DDRCTL_REG_MAP_SIZE] = {
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DDRCTL_REG_MAP(addrmap1),
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DDRCTL_REG_MAP(addrmap2),
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DDRCTL_REG_MAP(addrmap3),
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@ -105,7 +118,7 @@ static const struct reg_desc ddr_map[] = {
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};
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#define DDRCTL_REG_PERF(x) DDRCTL_REG(x, stm32mp1_ddrctrl_perf)
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static const struct reg_desc ddr_perf[] = {
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static const struct reg_desc ddr_perf[DDRCTL_REG_PERF_SIZE] = {
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DDRCTL_REG_PERF(sched),
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DDRCTL_REG_PERF(sched1),
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DDRCTL_REG_PERF(perfhpr1),
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@ -126,7 +139,7 @@ static const struct reg_desc ddr_perf[] = {
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};
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#define DDRPHY_REG_REG(x) DDRPHY_REG(x, stm32mp1_ddrphy_reg)
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static const struct reg_desc ddrphy_reg[] = {
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static const struct reg_desc ddrphy_reg[DDRPHY_REG_REG_SIZE] = {
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DDRPHY_REG_REG(pgcr),
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DDRPHY_REG_REG(aciocr),
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DDRPHY_REG_REG(dxccr),
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@ -141,7 +154,7 @@ static const struct reg_desc ddrphy_reg[] = {
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};
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#define DDRPHY_REG_TIMING(x) DDRPHY_REG(x, stm32mp1_ddrphy_timing)
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static const struct reg_desc ddrphy_timing[] = {
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static const struct reg_desc ddrphy_timing[DDRPHY_REG_TIMING_SIZE] = {
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DDRPHY_REG_TIMING(ptr0),
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DDRPHY_REG_TIMING(ptr1),
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DDRPHY_REG_TIMING(ptr2),
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@ -154,36 +167,9 @@ static const struct reg_desc ddrphy_timing[] = {
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DDRPHY_REG_TIMING(mr3),
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};
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#define DDR_REG_DYN(x) \
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{ \
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.name = #x, \
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.offset = offsetof(struct stm32mp1_ddrctl, x), \
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.par_offset = INVALID_OFFSET \
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}
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static const struct reg_desc ddr_dyn[] = {
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DDR_REG_DYN(stat),
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DDR_REG_DYN(init0),
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DDR_REG_DYN(dfimisc),
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DDR_REG_DYN(dfistat),
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DDR_REG_DYN(swctl),
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DDR_REG_DYN(swstat),
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DDR_REG_DYN(pctrl_0),
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DDR_REG_DYN(pctrl_1),
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};
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#define DDRPHY_REG_DYN(x) \
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{ \
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.name = #x, \
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.offset = offsetof(struct stm32mp1_ddrphy, x), \
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.par_offset = INVALID_OFFSET \
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}
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static const struct reg_desc ddrphy_dyn[] = {
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DDRPHY_REG_DYN(pir),
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DDRPHY_REG_DYN(pgsr),
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};
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/*
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* REGISTERS ARRAY: used to parse device tree and interactive mode
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*/
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enum reg_type {
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REG_REG,
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REG_TIMING,
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@ -191,12 +177,6 @@ enum reg_type {
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REG_MAP,
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REGPHY_REG,
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REGPHY_TIMING,
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/*
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* Dynamic registers => managed in driver or not changed,
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* can be dumped in interactive mode.
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*/
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REG_DYN,
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REGPHY_DYN,
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REG_TYPE_NB
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};
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@ -217,49 +197,37 @@ static const struct ddr_reg_info ddr_registers[REG_TYPE_NB] = {
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[REG_REG] = {
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.name = "static",
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.desc = ddr_reg,
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.size = ARRAY_SIZE(ddr_reg),
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.size = DDRCTL_REG_REG_SIZE,
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.base = DDR_BASE
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},
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[REG_TIMING] = {
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.name = "timing",
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.desc = ddr_timing,
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.size = ARRAY_SIZE(ddr_timing),
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.size = DDRCTL_REG_TIMING_SIZE,
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.base = DDR_BASE
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},
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[REG_PERF] = {
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.name = "perf",
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.desc = ddr_perf,
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.size = ARRAY_SIZE(ddr_perf),
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.size = DDRCTL_REG_PERF_SIZE,
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.base = DDR_BASE
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},
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[REG_MAP] = {
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.name = "map",
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.desc = ddr_map,
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.size = ARRAY_SIZE(ddr_map),
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.size = DDRCTL_REG_MAP_SIZE,
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.base = DDR_BASE
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},
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[REGPHY_REG] = {
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.name = "static",
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.desc = ddrphy_reg,
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.size = ARRAY_SIZE(ddrphy_reg),
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.size = DDRPHY_REG_REG_SIZE,
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.base = DDRPHY_BASE
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},
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[REGPHY_TIMING] = {
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.name = "timing",
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.desc = ddrphy_timing,
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.size = ARRAY_SIZE(ddrphy_timing),
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.base = DDRPHY_BASE
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},
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[REG_DYN] = {
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.name = "dyn",
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.desc = ddr_dyn,
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.size = ARRAY_SIZE(ddr_dyn),
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.base = DDR_BASE
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},
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[REGPHY_DYN] = {
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.name = "dyn",
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.desc = ddrphy_dyn,
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.size = ARRAY_SIZE(ddrphy_dyn),
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.size = DDRPHY_REG_TIMING_SIZE,
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.base = DDRPHY_BASE
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},
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};
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@ -231,8 +231,8 @@ static int stm32mp1_ddr_setup(void)
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VERBOSE("%s: %s[0x%x] = %d\n", __func__,
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param[idx].name, param[idx].size, ret);
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if (ret != 0) {
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ERROR("%s: Cannot read %s\n",
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__func__, param[idx].name);
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ERROR("%s: Cannot read %s, error=%d\n",
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__func__, param[idx].name, ret);
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return -EINVAL;
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}
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}
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