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mt8173: support big core PLL control in system suspend flow

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This patch adds big core ARMPLL control in system suspend flow.

Change-Id: I27a45dbbb360f17ff0b524a125630358ee2277e2
Signed-off-by: Louis Yu <louis.yu@mediatek.com>
Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
This commit is contained in:
Jimmy Huang 2015-11-16 13:44:31 +08:00 • committed by Yidi Lin
parent 76d47fea7e
commit b99d961c7d
3 changed files with 31 additions and 4 deletions
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4
plat/mediatek/mt8173/drivers/rtc/rtc.c
View file

@ -95,8 +95,8 @@ void rtc_bbpu_power_down(void)
if (Writeif_unlock()) {
RTC_Write(RTC_BBPU, bbpu);
if (!Write_trigger())
assert(1);
assert(0);
} else {
assert(1);
assert(0);
}
}

30
plat/mediatek/mt8173/drivers/spm/spm_suspend.c
View file

@ -29,6 +29,9 @@
*/
#include <bakery_lock.h>
#include <debug.h>
#include <delay_timer.h>
#include <mmio.h>
#include <mt8173_def.h>
#include <spm.h>
#include <spm_suspend.h>
@ -38,8 +41,6 @@
* This driver controls the system power in system suspend flow.
*/
#define WAIT_UART_ACK_TIMES 80 /* 80 * 10us */
#define WAKE_SRC_FOR_SUSPEND \
(WAKE_SRC_KP | WAKE_SRC_EINT | WAKE_SRC_MD32 | \
WAKE_SRC_USB_CD | WAKE_SRC_USB_PDN | WAKE_SRC_THERM | \
@ -50,6 +51,13 @@
#define spm_is_wakesrc_invalid(wakesrc) \
(!!((unsigned int)(wakesrc) & 0xc0003803))
#define ARMCA15PLL_CON0 (APMIXED_BASE + 0x200)
#define ARMCA15PLL_CON1 (APMIXED_BASE + 0x204)
#define ARMCA15PLL_PWR_CON0 (APMIXED_BASE + 0x20c)
#define ARMCA15PLL_PWR_ON (1U << 0)
#define ARMCA15PLL_ISO_EN (1U << 1)
#define ARMCA15PLL_EN (1U << 0)
const unsigned int spm_flags =
SPM_DUALVCORE_PDN_DIS | SPM_PASR_DIS | SPM_DPD_DIS |
SPM_CPU_DVS_DIS | SPM_OPT | SPM_INFRA_PDN_DIS;
@ -293,8 +301,23 @@ static enum wake_reason_t go_to_sleep_after_wfi(void)
return last_wr;
}
static void bigcore_pll_on(void)
{
mmio_setbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_PWR_ON);
mmio_clrbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_ISO_EN);
mmio_setbits_32(ARMCA15PLL_CON0, ARMCA15PLL_EN);
}
static void bigcore_pll_off(void)
{
mmio_clrbits_32(ARMCA15PLL_CON0, ARMCA15PLL_EN);
mmio_setbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_ISO_EN);
mmio_clrbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_PWR_ON);
}
void spm_system_suspend(void)
{
bigcore_pll_off();
spm_lock_get();
go_to_sleep_before_wfi(spm_flags);
set_suspend_ready();
@ -308,4 +331,7 @@ void spm_system_suspend_finish(void)
INFO("spm_wake_reason=%d\n", spm_wake_reason);
clear_all_ready();
spm_lock_release();
bigcore_pll_on();
/* Add 20us delay for turning on PLL*/
udelay(20);
}

1
plat/mediatek/mt8173/include/mt8173_def.h
View file

@ -46,6 +46,7 @@
#define RGU_BASE (IO_PHYS + 0x7000)
#define PMIC_WRAP_BASE (IO_PHYS + 0xD000)
#define MCUCFG_BASE (IO_PHYS + 0x200000)
#define APMIXED_BASE (IO_PHYS + 0x209000)
#define TRNG_BASE (IO_PHYS + 0x20F000)
#define MT_GIC_BASE (IO_PHYS + 0x220000)
#define PLAT_MT_CCI_BASE (IO_PHYS + 0x390000)