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Enable MTE support unilaterally for Normal World

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This patch enables MTE for Normal world if the CPU suppors it. Enabling
MTE for secure world will be done later.

Change-Id: I9ef64460beaba15e9a9c20ab02da4fb2208b6f7d
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
This commit is contained in:
Soby Mathew 2019-07-12 09:23:38 +01:00
parent 21bde92ff6
commit b7e398d64c
3 changed files with 27 additions and 0 deletions
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8
include/arch/aarch64/arch.h
View file

@ -219,6 +219,13 @@
#define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */
#define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
#define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
#define MTE_UNIMPLEMENTED ULL(0)
#define MTE_IMPLEMENTED_EL0 ULL(1) /* MTE is only implemented at EL0 */
#define MTE_IMPLEMENTED_ELX ULL(2) /* MTE is implemented at all ELs */
/* ID_PFR1_EL1 definitions */
#define ID_PFR1_VIRTEXT_SHIFT U(12)
#define ID_PFR1_VIRTEXT_MASK U(0xf)
@ -276,6 +283,7 @@
/* SCR definitions */
#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
#define SCR_ATA_BIT (U(1) << 26)
#define SCR_FIEN_BIT (U(1) << 21)
#define SCR_API_BIT (U(1) << 17)
#define SCR_APK_BIT (U(1) << 16)

6
include/arch/aarch64/arch_features.h
View file

@ -54,4 +54,10 @@ static inline bool is_armv8_5_bti_present(void)
ID_AA64PFR1_EL1_BT_MASK) == BTI_IMPLEMENTED;
}
static inline unsigned int get_armv8_5_mte_support(void)
{
return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_MTE_SHIFT) &
ID_AA64PFR1_EL1_MTE_MASK);
}
#endif /* ARCH_FEATURES_H */

13
lib/el3_runtime/aarch64/context_mgmt.c
View file

@ -12,6 +12,7 @@
#include <arch.h>
#include <arch_helpers.h>
#include <arch_features.h>
#include <bl31/interrupt_mgmt.h>
#include <common/bl_common.h>
#include <context.h>
@ -136,6 +137,18 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
#endif /* !CTX_INCLUDE_PAUTH_REGS */
unsigned int mte = get_armv8_5_mte_support();
/*
* Enable MTE support unilaterally for normal world if the CPU supports
* it.
*/
if (mte != MTE_UNIMPLEMENTED) {
if (security_state == NON_SECURE) {
scr_el3 |= SCR_ATA_BIT;
}
}
#ifdef IMAGE_BL31
/*
* SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as