diff --git a/bl1/bl1.mk b/bl1/bl1.mk index a8a006163..c068ea54c 100644 --- a/bl1/bl1.mk +++ b/bl1/bl1.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -18,8 +18,7 @@ BL1_SOURCES += bl1/${ARCH}/bl1_arch_setup.c \ ${MBEDTLS_SOURCES} ifeq (${ARCH},aarch64) -BL1_SOURCES += lib/cpus/aarch64/dsu_helpers.S \ - lib/el3_runtime/aarch64/context.S \ +BL1_SOURCES += lib/el3_runtime/aarch64/context.S \ lib/cpus/errata_common.c endif diff --git a/bl2/bl2.mk b/bl2/bl2.mk index 850d82668..2a212e135 100644 --- a/bl2/bl2.mk +++ b/bl2/bl2.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -43,10 +43,6 @@ BL2_SOURCES += bl2/${ARCH}/bl2_el3_entrypoint.S \ bl2/${ARCH}/bl2_run_next_image.S \ lib/cpus/${ARCH}/cpu_helpers.S -ifeq (${ARCH},aarch64) -BL2_SOURCES += lib/cpus/aarch64/dsu_helpers.S -endif - BL2_DEFAULT_LINKER_SCRIPT_SOURCE := bl2/bl2_el3.ld.S endif diff --git a/bl31/bl31.mk b/bl31/bl31.mk index 2f9dc6501..9b2b139ae 100644 --- a/bl31/bl31.mk +++ b/bl31/bl31.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -43,7 +43,6 @@ BL31_SOURCES += bl31/bl31_main.c \ bl31/bl31_traps.c \ common/runtime_svc.c \ lib/cpus/errata_common.c \ - lib/cpus/aarch64/dsu_helpers.S \ plat/common/aarch64/platform_mp_stack.S \ services/arm_arch_svc/arm_arch_svc_setup.c \ services/std_svc/std_svc_setup.c \ diff --git a/include/lib/cpus/aarch64/dsu_def.h b/include/lib/cpus/aarch64/dsu_def.h index 51fbfd1db..78b3e7f1c 100644 --- a/include/lib/cpus/aarch64/dsu_def.h +++ b/include/lib/cpus/aarch64/dsu_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -40,7 +40,23 @@ ********************************************************************/ #define DSU_ERRATA_936184_MASK (U(0x3) << 15) +#define CPUCFR_EL1 S3_0_C15_C0_0 +/* SCU bit of CPU Configuration Register, EL1 */ +#define SCU_SHIFT U(2) + #ifndef __ASSEMBLER__ -void dsu_pwr_dwn(void); +DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrctlr_el1, CLUSTERPWRCTLR_EL1); + +/* --------------------------------------------- + * controls power features of the cluster + * 1. Cache portion power not request + * 2. Disable the retention circuit + * --------------------------------------------- + */ +static inline void dsu_pwr_dwn(void) +{ + write_clusterpwrctlr_el1(0); + isb(); +} #endif #endif /* DSU_DEF_H */ diff --git a/include/lib/cpus/aarch64/dsu_macros.S b/include/lib/cpus/aarch64/dsu_macros.S new file mode 100644 index 000000000..6c8cb6904 --- /dev/null +++ b/include/lib/cpus/aarch64/dsu_macros.S @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DSU_MACROS_S +#define DSU_MACROS_S + +#include +#include +#include + +.macro check_errata_dsu_798953_impl + mov x2, #ERRATA_APPLIES + mov x3, #ERRATA_NOT_APPLIES + + /* Check if DSU is equal to r0p0 */ + mrs x1, CLUSTERIDR_EL1 + + /* DSU variant and revision bitfields in CLUSTERIDR are adjacent */ + ubfx x0, x1, #CLUSTERIDR_REV_SHIFT,\ + #(CLUSTERIDR_REV_BITS + CLUSTERIDR_VAR_BITS) + mov x1, #(0x0 << CLUSTERIDR_REV_SHIFT) + cmp x0, x1 + csel x0, x2, x3, EQ +.endm + +.macro errata_dsu_798953_wa_impl + /* If erratum applies, disable high-level clock gating */ + mrs x0, CLUSTERACTLR_EL1 + orr x0, x0, #CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING + msr CLUSTERACTLR_EL1, x0 +.endm + +.macro branch_if_scu_not_present _target:req + /* Check if the SCU L3 Unit is present on the DSU */ + mrs x0, CPUCFR_EL1 + ubfx x0, x0, #SCU_SHIFT, #1 + eor x0, x0, #1 + /* If SCU is not present, return without applying patch */ + cmp x0, xzr + mov x0, #ERRATA_NOT_APPLIES + b.eq \_target +.endm + +.macro check_errata_dsu_936184_impl + mov x0, #ERRATA_NOT_APPLIES + /* Erratum applies only if DSU has the ACP interface */ + mrs x1, CLUSTERCFR_EL1 + ubfx x1, x1, #CLUSTERCFR_ACP_SHIFT, #1 + cbz x1, 1f + + /* If ACP is present, check if DSU is older than r2p0 */ + mrs x1, CLUSTERIDR_EL1 + + /* DSU variant and revision bitfields in CLUSTERIDR are adjacent */ + ubfx x2, x1, #CLUSTERIDR_REV_SHIFT,\ + #(CLUSTERIDR_REV_BITS + CLUSTERIDR_VAR_BITS) + cmp x2, #(0x2 << CLUSTERIDR_VAR_SHIFT) + b.hs 1f + mov x0, #ERRATA_APPLIES +1: +.endm + +.macro errata_dsu_936184_wa_impl + /* If erratum applies, we set a mask to a DSU control register */ + mrs x0, CLUSTERACTLR_EL1 + ldr x1, =DSU_ERRATA_936184_MASK + orr x0, x0, x1 + msr CLUSTERACTLR_EL1, x0 +.endm + +.macro check_errata_dsu_2313941_impl + mov x2, #ERRATA_APPLIES + mov x3, #ERRATA_NOT_APPLIES + + /* Check if DSU version is less than or equal to r3p1 */ + mrs x1, CLUSTERIDR_EL1 + + mov x0, #ERRATA_NOT_APPLIES + /* DSU variant and revision bitfields in CLUSTERIDR are adjacent */ + ubfx x0, x1, #CLUSTERIDR_REV_SHIFT,\ + #(CLUSTERIDR_REV_BITS + CLUSTERIDR_VAR_BITS) + mov x1, #(0x31 << CLUSTERIDR_REV_SHIFT) + cmp x0, x1 + csel x0, x2, x3, LS +1: +.endm + +.macro errata_dsu_2313941_wa_impl + /* If erratum applies, disable high-level clock gating */ + mrs x0, CLUSTERACTLR_EL1 + orr x0, x0, #CLUSTERACTLR_EL1_DISABLE_SCLK_GATING + msr CLUSTERACTLR_EL1, x0 +.endm +#endif /* DSU_MACROS_S */ diff --git a/include/lib/cpus/aarch64/neoverse_n_common.h b/include/lib/cpus/aarch64/neoverse_n_common.h deleted file mode 100644 index 7cb91cd05..000000000 --- a/include/lib/cpus/aarch64/neoverse_n_common.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (c) 2020, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef NEOVERSE_N_COMMON_H -#define NEOVERSE_N_COMMON_H - -/****************************************************************************** - * Neoverse Nx CPU Configuration register definitions - *****************************************************************************/ -#define CPUCFR_EL1 S3_0_C15_C0_0 - -/* SCU bit of CPU Configuration Register, EL1 */ -#define SCU_SHIFT U(2) - -#endif /* NEOVERSE_N_COMMON_H */ diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S index b49d45a22..b399bbc5f 100644 --- a/lib/cpus/aarch64/cortex_a510.S +++ b/lib/cpus/aarch64/cortex_a510.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023-2024, Arm Limited. All rights reserved. + * Copyright (c) 2023-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,7 @@ #include #include #include +#include #include /* Hardware handled coherency */ @@ -180,15 +181,14 @@ workaround_runtime_end cortex_a510, ERRATUM(2684597) check_erratum_ls cortex_a510, ERRATUM(2684597), CPU_REV(1, 2) -/* - * ERRATA_DSU_2313941 : - * The errata is defined in dsu_helpers.S but applies to cortex_a510 - * as well. Henceforth creating symbolic names to the already existing errata - * workaround functions to get them registered under the Errata Framework. - */ -.equ check_erratum_cortex_a510_2313941, check_errata_dsu_2313941 -.equ erratum_cortex_a510_2313941_wa, errata_dsu_2313941_wa -add_erratum_entry cortex_a510, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET +workaround_reset_start cortex_a510, ERRATUM(2313941), ERRATA_DSU_2313941 + errata_dsu_2313941_wa_impl +workaround_reset_end cortex_a510, ERRATUM(2313941) + +check_erratum_custom_start cortex_a510, ERRATUM(2313941) + check_errata_dsu_2313941_impl + ret +check_erratum_custom_end cortex_a510, ERRATUM(2313941) /* ---------------------------------------------------- * HW will do the cache maintenance while powering down diff --git a/lib/cpus/aarch64/cortex_a55.S b/lib/cpus/aarch64/cortex_a55.S index d5a74e96d..f9e3edabc 100644 --- a/lib/cpus/aarch64/cortex_a55.S +++ b/lib/cpus/aarch64/cortex_a55.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,7 @@ #include #include #include +#include #include /* Hardware handled coherency */ @@ -19,23 +20,23 @@ .globl cortex_a55_reset_func .globl cortex_a55_core_pwr_dwn -/* ERRATA_DSU_798953: - * The errata is defined in dsu_helpers.S but applies to cortex_a55 - * as well. Henceforth creating symbolic names to the already existing errata - * workaround functions to get them registered under the Errata Framework. - */ -.equ check_erratum_cortex_a55_798953, check_errata_dsu_798953 -.equ erratum_cortex_a55_798953_wa, errata_dsu_798953_wa -add_erratum_entry cortex_a55, ERRATUM(798953), ERRATA_DSU_798953, APPLY_AT_RESET +workaround_reset_start cortex_a55, ERRATUM(798953), ERRATA_DSU_798953 + errata_dsu_798953_wa_impl +workaround_reset_end cortex_a55, ERRATUM(798953) -/* ERRATA_DSU_936184: - * The errata is defined in dsu_helpers.S but applies to cortex_a55 - * as well. Henceforth creating symbolic names to the already existing errata - * workaround functions to get them registered under the Errata Framework. - */ -.equ check_erratum_cortex_a55_936184, check_errata_dsu_936184 -.equ erratum_cortex_a55_936184_wa, errata_dsu_936184_wa -add_erratum_entry cortex_a55, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET +check_erratum_custom_start cortex_a55, ERRATUM(798953) + check_errata_dsu_798953_impl + ret +check_erratum_custom_end cortex_a55, ERRATUM(798953) + +workaround_reset_start cortex_a55, ERRATUM(936184), ERRATA_DSU_936184 + errata_dsu_936184_wa_impl +workaround_reset_end cortex_a55, ERRATUM(936184) + +check_erratum_custom_start cortex_a55, ERRATUM(936184) + check_errata_dsu_936184_impl + ret +check_erratum_custom_end cortex_a55, ERRATUM(936184) workaround_reset_start cortex_a55, ERRATUM(768277), ERRATA_A55_768277 sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE diff --git a/lib/cpus/aarch64/cortex_a65.S b/lib/cpus/aarch64/cortex_a65.S index b3c1726eb..064e6f0ec 100644 --- a/lib/cpus/aarch64/cortex_a65.S +++ b/lib/cpus/aarch64/cortex_a65.S @@ -10,6 +10,7 @@ #include #include #include +#include #include /* Hardware handled coherency */ @@ -22,15 +23,14 @@ #error "Cortex-A65 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif -/* - * ERRATA_DSU_936184: - * The errata is defined in dsu_helpers.S and applies to neoverse_e1. - * Henceforth creating symbolic names to the already existing errata - * workaround functions to get them registered under the Errata Framework. - */ -.equ check_erratum_neoverse_e1_936184, check_errata_dsu_936184 -.equ erratum_neoverse_e1_936184_wa, errata_dsu_936184_wa -add_erratum_entry neoverse_e1, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET +workaround_reset_start cortex_a65, ERRATUM(936184), ERRATA_DSU_936184 + errata_dsu_936184_wa_impl +workaround_reset_end cortex_a65, ERRATUM(936184) + +check_erratum_custom_start cortex_a65, ERRATUM(936184) + check_errata_dsu_936184_impl + ret +check_erratum_custom_end cortex_a65, ERRATUM(936184) cpu_reset_func_start cortex_a65 cpu_reset_func_end cortex_a65 diff --git a/lib/cpus/aarch64/cortex_a65ae.S b/lib/cpus/aarch64/cortex_a65ae.S index 1cbb06aff..d2f9e49f1 100644 --- a/lib/cpus/aarch64/cortex_a65ae.S +++ b/lib/cpus/aarch64/cortex_a65ae.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2024, Arm Limited. All rights reserved. + * Copyright (c) 2019-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,6 +11,7 @@ #include #include #include +#include /* Hardware handled coherency */ #if !HW_ASSISTED_COHERENCY @@ -22,15 +23,14 @@ #error "Cortex-A65AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif - /* - * ERRATA_DSU_936184 : - * The errata is defined in dsu_helpers.S but applies to cortex_a65ae - * as well. Henceforth creating symbolic names to the already existing errata - * workaround functions to get them registered under the Errata Framework. - */ -.equ check_erratum_cortex_a65ae_936184, check_errata_dsu_936184 -.equ erratum_cortex_a65ae_936184_wa, errata_dsu_936184_wa -add_erratum_entry cortex_a65ae, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET +workaround_reset_start cortex_a65ae, ERRATUM(936184), ERRATA_DSU_936184 + errata_dsu_936184_wa_impl +workaround_reset_end cortex_a65ae, ERRATUM(936184) + +check_erratum_custom_start cortex_a65ae, ERRATUM(936184) + check_errata_dsu_936184_impl + ret +check_erratum_custom_end cortex_a65ae, ERRATUM(936184) cpu_reset_func_start cortex_a65ae cpu_reset_func_end cortex_a65ae diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S index c50a7d322..17163a150 100644 --- a/lib/cpus/aarch64/cortex_a710.S +++ b/lib/cpus/aarch64/cortex_a710.S @@ -9,6 +9,7 @@ #include #include #include +#include #include #include "wa_cve_2022_23960_bhb_vector.S" @@ -173,14 +174,14 @@ workaround_runtime_end cortex_a710, ERRATUM(2291219), NO_ISB check_erratum_ls cortex_a710, ERRATUM(2291219), CPU_REV(2, 0) -/* - * ERRATA_DSU_2313941 is defined in dsu_helpers.S but applies to Cortex-A710 as - * well. Create a symbollic link to existing errata workaround to get them - * registered under the Errata Framework. - */ -.equ check_erratum_cortex_a710_2313941, check_errata_dsu_2313941 -.equ erratum_cortex_a710_2313941_wa, errata_dsu_2313941_wa -add_erratum_entry cortex_a710, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET +workaround_reset_start cortex_a710, ERRATUM(2313941), ERRATA_DSU_2313941 + errata_dsu_2313941_wa_impl +workaround_reset_end cortex_a710, ERRATUM(2313941) + +check_erratum_custom_start cortex_a710, ERRATUM(2313941) + check_errata_dsu_2313941_impl + ret +check_erratum_custom_end cortex_a710, ERRATUM(2313941) workaround_reset_start cortex_a710, ERRATUM(2371105), ERRATA_A710_2371105 /* Set bit 40 in CPUACTLR2_EL1 */ diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S index 152c81f68..336e00e5c 100644 --- a/lib/cpus/aarch64/cortex_a75.S +++ b/lib/cpus/aarch64/cortex_a75.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,7 @@ #include #include #include +#include .global check_erratum_cortex_a75_764081 @@ -29,23 +30,23 @@ workaround_reset_end cortex_a75, ERRATUM(790748) check_erratum_ls cortex_a75, ERRATUM(790748), CPU_REV(0, 0) -/* ERRATA_DSU_798953 : - * The errata is defined in dsu_helpers.S but applies to cortex_a75 - * as well. Henceforth creating symbolic names to the already existing errata - * workaround functions to get them registered under the Errata Framework. - */ -.equ check_erratum_cortex_a75_798953, check_errata_dsu_798953 -.equ erratum_cortex_a75_798953_wa, errata_dsu_798953_wa -add_erratum_entry cortex_a75, ERRATUM(798953), ERRATA_DSU_798953, APPLY_AT_RESET +workaround_reset_start cortex_a75, ERRATUM(798953), ERRATA_DSU_798953 + errata_dsu_798953_wa_impl +workaround_reset_end cortex_a75, ERRATUM(798953) -/* ERRATA_DSU_936184 : - * The errata is defined in dsu_helpers.S but applies to cortex_a75 - * as well. Henceforth creating symbolic names to the already existing errata - * workaround functions to get them registered under the Errata Framework. - */ -.equ check_erratum_cortex_a75_936184, check_errata_dsu_936184 -.equ erratum_cortex_a75_936184_wa, errata_dsu_936184_wa -add_erratum_entry cortex_a75, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET +check_erratum_custom_start cortex_a75, ERRATUM(798953) + check_errata_dsu_798953_impl + ret +check_erratum_custom_end cortex_a75, ERRATUM(798953) + +workaround_reset_start cortex_a75, ERRATUM(936184), ERRATA_DSU_936184 + errata_dsu_936184_wa_impl +workaround_reset_end cortex_a75, ERRATUM(936184) + +check_erratum_custom_start cortex_a75, ERRATUM(936184) + check_errata_dsu_936184_impl + ret +check_erratum_custom_end cortex_a75, ERRATUM(936184) workaround_reset_start cortex_a75, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 #if IMAGE_BL31 diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S index 017086aa9..1fd078959 100644 --- a/lib/cpus/aarch64/cortex_a76.S +++ b/lib/cpus/aarch64/cortex_a76.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include "wa_cve_2022_23960_bhb.S" @@ -431,23 +432,23 @@ check_erratum_chosen cortex_a76, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 /* erratum has no workaround in the cpu. Generic code must take care */ add_erratum_entry cortex_a76, CVE(2022, 23960), WORKAROUND_CVE_2022_23960, NO_APPLY_AT_RESET -/* ERRATA_DSU_798953 : - * The errata is defined in dsu_helpers.S but applies to cortex_a76 - * as well. Henceforth creating symbolic names to the already existing errata - * workaround functions to get them registered under the Errata Framework. - */ -.equ check_erratum_cortex_a76_798953, check_errata_dsu_798953 -.equ erratum_cortex_a76_798953_wa, errata_dsu_798953_wa -add_erratum_entry cortex_a76, ERRATUM(798953), ERRATA_DSU_798953, APPLY_AT_RESET +workaround_reset_start cortex_a76, ERRATUM(798953), ERRATA_DSU_798953 + errata_dsu_798953_wa_impl +workaround_reset_end cortex_a76, ERRATUM(798953) -/* ERRATA_DSU_936184 : - * The errata is defined in dsu_helpers.S but applies to cortex_a76 - * as well. Henceforth creating symbolic names to the already existing errata - * workaround functions to get them registered under the Errata Framework. - */ -.equ check_erratum_cortex_a76_936184, check_errata_dsu_936184 -.equ erratum_cortex_a76_936184_wa, errata_dsu_936184_wa -add_erratum_entry cortex_a76, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET +check_erratum_custom_start cortex_a76, ERRATUM(798953) + check_errata_dsu_798953_impl + ret +check_erratum_custom_end cortex_a76, ERRATUM(798953) + +workaround_reset_start cortex_a76, ERRATUM(936184), ERRATA_DSU_936184 + errata_dsu_936184_wa_impl +workaround_reset_end cortex_a76, ERRATUM(936184) + +check_erratum_custom_start cortex_a76, ERRATUM(936184) + check_errata_dsu_936184_impl + ret +check_erratum_custom_end cortex_a76, ERRATUM(936184) cpu_reset_func_start cortex_a76 diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S index c18ce3c0f..547c430cd 100644 --- a/lib/cpus/aarch64/cortex_x2.S +++ b/lib/cpus/aarch64/cortex_x2.S @@ -9,6 +9,7 @@ #include #include #include +#include #include #include "wa_cve_2022_23960_bhb_vector.S" @@ -164,15 +165,14 @@ workaround_reset_end cortex_x2, CVE(2022, 23960) check_erratum_chosen cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 -/* - * ERRATA_DSU_2313941 : - * The errata is defined in dsu_helpers.S but applies to cortex_x2 - * as well. Henceforth creating symbolic names to the already existing errata - * workaround functions to get them registered under the Errata Framework. - */ -.equ check_erratum_cortex_x2_2313941, check_errata_dsu_2313941 -.equ erratum_cortex_x2_2313941_wa, errata_dsu_2313941_wa -add_erratum_entry cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET +workaround_reset_start cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941 + errata_dsu_2313941_wa_impl +workaround_reset_end cortex_x2, ERRATUM(2313941) + +check_erratum_custom_start cortex_x2, ERRATUM(2313941) + check_errata_dsu_2313941_impl + ret +check_erratum_custom_end cortex_x2, ERRATUM(2313941) /* ---------------------------------------------------- * HW will do the cache maintenance while powering down diff --git a/lib/cpus/aarch64/dsu_helpers.S b/lib/cpus/aarch64/dsu_helpers.S deleted file mode 100644 index 3c5bf2ea1..000000000 --- a/lib/cpus/aarch64/dsu_helpers.S +++ /dev/null @@ -1,217 +0,0 @@ -/* - * Copyright (c) 2019-2023, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - - /* ----------------------------------------------------------------------- - * DSU erratum 798953 check function - * Checks the DSU variant, revision and configuration to determine if - * the erratum applies. Erratum applies on all configurations of the - * DSU and if revision-variant is r0p0. - * - * The erratum was fixed in r0p1. - * - * This function is called from both assembly and C environment. So it - * follows AAPCS. - * - * Clobbers: x0-x3 - * ----------------------------------------------------------------------- - */ - .globl check_errata_dsu_798953 - .globl errata_dsu_798953_wa - .globl dsu_pwr_dwn - -func check_errata_dsu_798953 - mov x2, #ERRATA_APPLIES - mov x3, #ERRATA_NOT_APPLIES - - /* Check if DSU is equal to r0p0 */ - mrs x1, CLUSTERIDR_EL1 - - /* DSU variant and revision bitfields in CLUSTERIDR are adjacent */ - ubfx x0, x1, #CLUSTERIDR_REV_SHIFT,\ - #(CLUSTERIDR_REV_BITS + CLUSTERIDR_VAR_BITS) - mov x1, #(0x0 << CLUSTERIDR_REV_SHIFT) - cmp x0, x1 - csel x0, x2, x3, EQ - ret -endfunc check_errata_dsu_798953 - - /* -------------------------------------------------- - * Errata Workaround for DSU erratum #798953. - * - * Can clobber only: x0-x8 - * -------------------------------------------------- - */ -func errata_dsu_798953_wa - mov x8, x30 - bl check_errata_dsu_798953 - cbz x0, 1f - - /* If erratum applies, disable high-level clock gating */ - mrs x0, CLUSTERACTLR_EL1 - orr x0, x0, #CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING - msr CLUSTERACTLR_EL1, x0 - isb -1: - ret x8 -endfunc errata_dsu_798953_wa - - /* ----------------------------------------------------------------------- - * DSU erratum 936184 check function - * Checks the DSU variant, revision and configuration to determine if - * the erratum applies. Erratum applies if ACP interface is present - * in the DSU and revision-variant < r2p0. - * - * The erratum was fixed in r2p0. - * - * This function is called from both assembly and C environment. So it - * follows AAPCS. - * - * Clobbers: x0-x4 - * ----------------------------------------------------------------------- - */ - .globl check_errata_dsu_936184 - .globl errata_dsu_936184_wa - .weak is_scu_present_in_dsu - - /* -------------------------------------------------------------------- - * Default behaviour respresents SCU is always present with DSU. - * CPUs can override this definition if required. - * - * Can clobber only: x0-x3 - * -------------------------------------------------------------------- - */ -func is_scu_present_in_dsu - mov x0, #1 - ret -endfunc is_scu_present_in_dsu - -func check_errata_dsu_936184 - mov x4, x30 - bl is_scu_present_in_dsu - cmp x0, xzr - /* Default error status */ - mov x0, #ERRATA_NOT_APPLIES - - /* If SCU is not present, return without applying patch */ - b.eq 1f - - /* Erratum applies only if DSU has the ACP interface */ - mrs x1, CLUSTERCFR_EL1 - ubfx x1, x1, #CLUSTERCFR_ACP_SHIFT, #1 - cbz x1, 1f - - /* If ACP is present, check if DSU is older than r2p0 */ - mrs x1, CLUSTERIDR_EL1 - - /* DSU variant and revision bitfields in CLUSTERIDR are adjacent */ - ubfx x2, x1, #CLUSTERIDR_REV_SHIFT,\ - #(CLUSTERIDR_REV_BITS + CLUSTERIDR_VAR_BITS) - cmp x2, #(0x2 << CLUSTERIDR_VAR_SHIFT) - b.hs 1f - mov x0, #ERRATA_APPLIES -1: - ret x4 -endfunc check_errata_dsu_936184 - - /* -------------------------------------------------- - * Errata Workaround for DSU erratum #936184. - * - * Can clobber only: x0-x8 - * -------------------------------------------------- - */ -func errata_dsu_936184_wa - mov x8, x30 - bl check_errata_dsu_936184 - cbz x0, 1f - - /* If erratum applies, we set a mask to a DSU control register */ - mrs x0, CLUSTERACTLR_EL1 - ldr x1, =DSU_ERRATA_936184_MASK - orr x0, x0, x1 - msr CLUSTERACTLR_EL1, x0 - isb -1: - ret x8 -endfunc errata_dsu_936184_wa - - /* ----------------------------------------------------------------------- - * DSU erratum 2313941 check function - * Checks the DSU variant, revision and configuration to determine if - * the erratum applies. Erratum applies on all configurations of the - * DSU and if revision-variant is r0p0, r1p0, r2p0, r2p1, r3p0, r3p1. - * - * The erratum is still open. - * - * This function is called from both assembly and C environment. So it - * follows AAPCS. - * - * Clobbers: x0-x4 - * ----------------------------------------------------------------------- - */ - .globl check_errata_dsu_2313941 - .globl errata_dsu_2313941_wa - -func check_errata_dsu_2313941 - mov x4, x30 - bl is_scu_present_in_dsu - cmp x0, xzr - /* Default error status */ - mov x0, #ERRATA_NOT_APPLIES - - /* If SCU is not present, return without applying patch */ - b.eq 1f - - mov x2, #ERRATA_APPLIES - mov x3, #ERRATA_NOT_APPLIES - - /* Check if DSU version is less than or equal to r3p1 */ - mrs x1, CLUSTERIDR_EL1 - - /* DSU variant and revision bitfields in CLUSTERIDR are adjacent */ - ubfx x0, x1, #CLUSTERIDR_REV_SHIFT,\ - #(CLUSTERIDR_REV_BITS + CLUSTERIDR_VAR_BITS) - mov x1, #(0x31 << CLUSTERIDR_REV_SHIFT) - cmp x0, x1 - csel x0, x2, x3, LS -1: - ret x4 -endfunc check_errata_dsu_2313941 - - /* -------------------------------------------------- - * Errata Workaround for DSU erratum #2313941. - * - * Can clobber only: x0-x8 - * -------------------------------------------------- - */ -func errata_dsu_2313941_wa - mov x8, x30 - bl check_errata_dsu_2313941 - cbz x0, 1f - - /* If erratum applies, disable high-level clock gating */ - mrs x0, CLUSTERACTLR_EL1 - orr x0, x0, #CLUSTERACTLR_EL1_DISABLE_SCLK_GATING - msr CLUSTERACTLR_EL1, x0 - isb -1: - ret x8 -endfunc errata_dsu_2313941_wa - - /* --------------------------------------------- - * controls power features of the cluster - * 1. Cache portion power not request - * 2. Disable the retention circuit - * --------------------------------------------- - */ -func dsu_pwr_dwn - msr CLUSTERPWRCTLR_EL1, xzr - isb - ret -endfunc dsu_pwr_dwn diff --git a/lib/cpus/aarch64/neoverse_e1.S b/lib/cpus/aarch64/neoverse_e1.S index 4bc95d054..c6dd11783 100644 --- a/lib/cpus/aarch64/neoverse_e1.S +++ b/lib/cpus/aarch64/neoverse_e1.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -21,15 +22,16 @@ #error "Neoverse-E1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif -/* - * ERRATA_DSU_936184: - * The errata is defined in dsu_helpers.S and applies to neoverse_e1. - * Henceforth creating symbolic names to the already existing errata - * workaround functions to get them registered under the Errata Framework. - */ -.equ check_erratum_neoverse_e1_936184, check_errata_dsu_936184 -.equ erratum_neoverse_e1_936184_wa, errata_dsu_936184_wa -add_erratum_entry neoverse_e1, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET +workaround_reset_start neoverse_e1, ERRATUM(936184), ERRATA_DSU_936184 + errata_dsu_936184_wa_impl +workaround_reset_end neoverse_e1, ERRATUM(936184) + +check_erratum_custom_start neoverse_e1, ERRATUM(936184) + branch_if_scu_not_present 2f /* label 1 is used in the macro */ + check_errata_dsu_936184_impl + 2: + ret +check_erratum_custom_end neoverse_e1, ERRATUM(936184) cpu_reset_func_start neoverse_e1 cpu_reset_func_end neoverse_e1 diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index f727226bd..638d0d3a3 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,6 +8,7 @@ #include #include #include +#include #include #include "wa_cve_2022_23960_bhb_vector.S" @@ -27,15 +28,16 @@ wa_cve_2022_23960_bhb_vector_table NEOVERSE_N1_BHB_LOOP_COUNT, neoverse_n1 #endif /* WORKAROUND_CVE_2022_23960 */ -/* - * ERRATA_DSU_936184: - * The errata is defined in dsu_helpers.S and applies to Neoverse N1. - * Henceforth creating symbolic names to the already existing errata - * workaround functions to get them registered under the Errata Framework. - */ -.equ check_erratum_neoverse_n1_936184, check_errata_dsu_936184 -.equ erratum_neoverse_n1_936184_wa, errata_dsu_936184_wa -add_erratum_entry neoverse_n1, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET +workaround_reset_start neoverse_n1, ERRATUM(936184), ERRATA_DSU_936184 + errata_dsu_936184_wa_impl +workaround_reset_end neoverse_n1, ERRATUM(936184) + +check_erratum_custom_start neoverse_n1, ERRATUM(936184) + branch_if_scu_not_present 2f /* label 1 is used in the macro */ + check_errata_dsu_936184_impl + 2: + ret +check_erratum_custom_end neoverse_n1, ERRATUM(936184) workaround_reset_start neoverse_n1, ERRATUM(1043202), ERRATA_N1_1043202 /* Apply instruction patching sequence */ diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S index 9ffe98fbb..fd6877dab 100644 --- a/lib/cpus/aarch64/neoverse_n2.S +++ b/lib/cpus/aarch64/neoverse_n2.S @@ -7,6 +7,7 @@ #include #include #include +#include #include #include "wa_cve_2022_23960_bhb_vector.S" @@ -30,15 +31,16 @@ check_erratum_ls neoverse_n2, ERRATUM(3701773), CPU_REV(0, 3) wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2 #endif /* WORKAROUND_CVE_2022_23960 */ -/* - * ERRATA_DSU_2313941: - * The errata is defined in dsu_helpers.S and applies to Neoverse N2. - * Henceforth creating symbolic names to the already existing errata - * workaround functions to get them registered under the Errata Framework. - */ -.equ check_erratum_neoverse_n2_2313941, check_errata_dsu_2313941 -.equ erratum_neoverse_n2_2313941_wa, errata_dsu_2313941_wa -add_erratum_entry neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET +workaround_reset_start neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941 + errata_dsu_2313941_wa_impl +workaround_reset_end neoverse_n2, ERRATUM(2313941) + +check_erratum_custom_start neoverse_n2, ERRATUM(2313941) + branch_if_scu_not_present 2f /* label 1 is used in the macro */ + check_errata_dsu_2313941_impl + 2: + ret +check_erratum_custom_end neoverse_n2, ERRATUM(2313941) /* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ workaround_reset_start neoverse_n2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 diff --git a/lib/cpus/aarch64/neoverse_n_common.S b/lib/cpus/aarch64/neoverse_n_common.S deleted file mode 100644 index b816342ba..000000000 --- a/lib/cpus/aarch64/neoverse_n_common.S +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2020, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - - .global is_scu_present_in_dsu - -/* - * Check if the SCU L3 Unit is present on the DSU - * 1-> SCU present - * 0-> SCU not present - * - * This function is implemented as weak on dsu_helpers.S and must be - * overwritten for Neoverse Nx cores. - */ - -func is_scu_present_in_dsu - mrs x0, CPUCFR_EL1 - ubfx x0, x0, #SCU_SHIFT, #1 - eor x0, x0, #1 - ret -endfunc is_scu_present_in_dsu diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk index 967bf2171..31835f171 100644 --- a/plat/arm/board/arm_fpga/platform.mk +++ b/plat/arm/board/arm_fpga/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2021-2024, Arm Limited. All rights reserved. +# Copyright (c) 2021-2025, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -78,7 +78,6 @@ else lib/cpus/aarch64/cortex_a720.S \ lib/cpus/aarch64/cortex_x3.S \ lib/cpus/aarch64/cortex_x4.S \ - lib/cpus/aarch64/neoverse_n_common.S \ lib/cpus/aarch64/neoverse_n1.S \ lib/cpus/aarch64/neoverse_n2.S \ lib/cpus/aarch64/neoverse_v1.S \ diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 7b55571b0..7bd3e742a 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -210,7 +210,6 @@ else lib/cpus/aarch64/cortex_a715.S \ lib/cpus/aarch64/cortex_a720.S \ lib/cpus/aarch64/cortex_a720_ae.S \ - lib/cpus/aarch64/neoverse_n_common.S \ lib/cpus/aarch64/neoverse_n1.S \ lib/cpus/aarch64/neoverse_n2.S \ lib/cpus/aarch64/neoverse_v1.S \ diff --git a/plat/qemu/common/common.mk b/plat/qemu/common/common.mk index 2dc89bccb..da981e5c9 100644 --- a/plat/qemu/common/common.mk +++ b/plat/qemu/common/common.mk @@ -23,7 +23,6 @@ QEMU_CPU_LIBS := lib/cpus/aarch64/aem_generic.S \ lib/cpus/aarch64/cortex_a72.S \ lib/cpus/aarch64/cortex_a76.S \ lib/cpus/aarch64/cortex_a710.S \ - lib/cpus/aarch64/neoverse_n_common.S \ lib/cpus/aarch64/neoverse_n1.S \ lib/cpus/aarch64/neoverse_v1.S \ lib/cpus/aarch64/neoverse_n2.S \