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Merge changes from topic "feat_state_part2" into integration

Browse source 
* changes:
  refactor(trf): enable FEAT_TRF for FEAT_STATE_CHECKED
  refactor(brbe): enable FEAT_BRBE for FEAT_STATE_CHECKED
  refactor(trbe): enable FEAT_TRBE for FEAT_STATE_CHECKED
  fix(cpufeat): context-switch: move FGT availability check to callers
  feat(cpufeat): extend check_feature() to deal with min/max
  refactor(cpufeat): wrap CPU ID register field isolation
This commit is contained in:
Manish Pandey 2023-02-28 11:40:54 +01:00 • committed by TrustedFirmware Code Review
commit b4fc04103e
15 changed files with 185 additions and 197 deletions
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6
bl31/bl31.mk
View file

@ -112,11 +112,11 @@ ifeq (${ENABLE_MPAM_FOR_LOWER_ELS},1)
BL31_SOURCES += lib/extensions/mpam/mpam.c
endif
ifeq (${ENABLE_TRBE_FOR_NS},1)
ifneq (${ENABLE_TRBE_FOR_NS},0)
BL31_SOURCES += lib/extensions/trbe/trbe.c
endif
ifeq (${ENABLE_BRBE_FOR_NS},1)
ifneq (${ENABLE_BRBE_FOR_NS},0)
BL31_SOURCES += lib/extensions/brbe/brbe.c
endif
@ -124,7 +124,7 @@ ifeq (${ENABLE_SYS_REG_TRACE_FOR_NS},1)
BL31_SOURCES += lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c
endif
ifeq (${ENABLE_TRF_FOR_NS},1)
ifneq (${ENABLE_TRF_FOR_NS},0)
BL31_SOURCES += lib/extensions/trf/aarch64/trf.c
endif

2
bl32/sp_min/sp_min.mk
View file

@ -50,7 +50,7 @@ ifeq (${ENABLE_SYS_REG_TRACE_FOR_NS},1)
BL32_SOURCES += lib/extensions/sys_reg_trace/aarch32/sys_reg_trace.c
endif
ifeq (${ENABLE_TRF_FOR_NS},1)
ifneq (${ENABLE_TRF_FOR_NS},0)
BL32_SOURCES += lib/extensions/trf/aarch32/trf.c
endif

63
common/feat_detect.c
View file

@ -36,19 +36,28 @@ static inline void feature_panic(char *feat_name)
/*******************************************************************************
* Function : check_feature
* Check for a valid combination of build time flags (ENABLE_FEAT_xxx) and
* feature availability on the hardware.
* Panics if a feature is forcefully enabled, but not available on the PE.
* feature availability on the hardware. <min> is the smallest feature
* ID field value that is required for that feature.
* Triggers a panic later if a feature is forcefully enabled, but not
* available on the PE. Also will panic if the hardware feature ID field
* is larger than the maximum known and supported number, specified by <max>.
*
* We force inlining here to let the compiler optimise away the whole check
* if the feature is disabled at build time (FEAT_STATE_DISABLED).
******************************************************************************/
static inline void __attribute((__always_inline__))
check_feature(int state, unsigned long field, const char *feat_name)
check_feature(int state, unsigned long field, const char *feat_name,
unsigned int min, unsigned int max)
{
if (state == FEAT_STATE_ALWAYS && field == 0U) {
if (state == FEAT_STATE_ALWAYS && field < min) {
ERROR("FEAT_%s not supported by the PE\n", feat_name);
tainted = true;
}
if (state >= FEAT_STATE_ALWAYS && field > max) {
ERROR("FEAT_%s is version %ld, but is only known up to version %d\n",
feat_name, field, max);
tainted = true;
}
}
/******************************************
@ -153,16 +162,6 @@ static void read_feat_sel2(void)
#endif
}
/****************************************************
* Feature : FEAT_TRF (Self-hosted Trace Extensions)
***************************************************/
static void read_feat_trf(void)
{
#if (ENABLE_TRF_FOR_NS == FEAT_STATE_ALWAYS)
feat_detect_panic(is_arm8_4_feat_trf_present(), "TRF");
#endif
}
/************************************************
* Feature : FEAT_MTE (Memory Tagging Extension)
***********************************************/
@ -239,26 +238,6 @@ static void read_feat_rme(void)
#endif
}
/******************************************************
* Feature : FEAT_BRBE (Branch Record Buffer Extension)
*****************************************************/
static void read_feat_brbe(void)
{
#if (ENABLE_BRBE_FOR_NS == FEAT_STATE_ALWAYS)
feat_detect_panic(is_feat_brbe_present(), "BRBE");
#endif
}
/******************************************************
* Feature : FEAT_TRBE (Trace Buffer Extension)
*****************************************************/
static void read_feat_trbe(void)
{
#if (ENABLE_TRBE_FOR_NS == FEAT_STATE_ALWAYS)
feat_detect_panic(is_feat_trbe_present(), "TRBE");
#endif
}
/******************************************************************
* Feature : FEAT_RNG_TRAP (Trapping support for RNDR/RNDRRS)
*****************************************************************/
@ -312,11 +291,13 @@ void detect_arch_features(void)
/* v8.4 features */
read_feat_dit();
check_feature(ENABLE_FEAT_AMUv1, read_feat_amu_id_field(), "AMUv1");
check_feature(ENABLE_FEAT_AMUv1, read_feat_amu_id_field(),
"AMUv1", 1, 2);
read_feat_mpam();
read_feat_nv2();
read_feat_sel2();
read_feat_trf();
check_feature(ENABLE_TRF_FOR_NS, read_feat_trf_id_field(),
"TRF", 1, 1);
/* v8.5 features */
read_feat_mte();
@ -326,16 +307,18 @@ void detect_arch_features(void)
/* v8.6 features */
read_feat_amuv1p1();
check_feature(ENABLE_FEAT_FGT, read_feat_fgt_id_field(), "FGT");
check_feature(ENABLE_FEAT_FGT, read_feat_fgt_id_field(), "FGT", 1, 1);
read_feat_ecv();
read_feat_twed();
/* v8.7 features */
check_feature(ENABLE_FEAT_HCX, read_feat_hcx_id_field(), "HCX");
check_feature(ENABLE_FEAT_HCX, read_feat_hcx_id_field(), "HCX", 1, 1);
/* v9.0 features */
read_feat_brbe();
read_feat_trbe();
check_feature(ENABLE_BRBE_FOR_NS, read_feat_brbe_id_field(),
"BRBE", 1, 2);
check_feature(ENABLE_TRBE_FOR_NS, read_feat_trbe_id_field(),
"TRBE", 1, 1);
/* v9.2 features */
read_feat_rme();

30
include/arch/aarch32/arch_features.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, Arm Limited. All rights reserved.
* Copyright (c) 2019-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -10,17 +10,37 @@
#include <stdbool.h>
#include <arch_helpers.h>
#include <common/feat_detect.h>
#define ISOLATE_FIELD(reg, feat) \
((unsigned int)(((reg) >> (feat ## _SHIFT)) & (feat ## _MASK)))
static inline bool is_armv7_gentimer_present(void)
{
return ((read_id_pfr1() >> ID_PFR1_GENTIMER_SHIFT) &
ID_PFR1_GENTIMER_MASK) != 0U;
return ISOLATE_FIELD(read_id_pfr1(), ID_PFR1_GENTIMER) != 0U;
}
static inline bool is_armv8_2_ttcnp_present(void)
{
return ((read_id_mmfr4() >> ID_MMFR4_CNP_SHIFT) &
ID_MMFR4_CNP_MASK) != 0U;
return ISOLATE_FIELD(read_id_mmfr4(), ID_MMFR4_CNP) != 0U;
}
static inline unsigned int read_feat_trf_id_field(void)
{
return ISOLATE_FIELD(read_id_dfr0(), ID_DFR0_TRACEFILT);
}
static inline bool is_feat_trf_supported(void)
{
if (ENABLE_TRF_FOR_NS == FEAT_STATE_DISABLED) {
return false;
}
if (ENABLE_TRF_FOR_NS == FEAT_STATE_ALWAYS) {
return true;
}
return read_feat_trf_id_field() != 0U;
}
#endif /* ARCH_FEATURES_H */

68
include/arch/aarch64/arch_features.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2022, Arm Limited. All rights reserved.
* Copyright (c) 2019-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -12,6 +12,9 @@
#include <arch_helpers.h>
#include <common/feat_detect.h>
#define ISOLATE_FIELD(reg, feat) \
((unsigned int)(((reg) >> (feat ## _SHIFT)) & (feat ## _MASK)))
static inline bool is_armv7_gentimer_present(void)
{
/* The Generic Timer is always present in an ARMv8-A implementation */
@ -100,8 +103,7 @@ static inline bool is_armv8_6_twed_present(void)
static unsigned int read_feat_fgt_id_field(void)
{
return (read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_FGT_SHIFT) &
ID_AA64MMFR0_EL1_FGT_MASK;
return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_FGT);
}
static inline bool is_feat_fgt_supported(void)
@ -134,8 +136,7 @@ static inline bool is_armv8_5_rng_present(void)
******************************************************************************/
static unsigned int read_feat_amu_id_field(void)
{
return (read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT) &
ID_AA64PFR0_AMU_MASK;
return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_AMU);
}
static inline bool is_feat_amu_supported(void)
@ -175,8 +176,7 @@ static inline unsigned int get_mpam_version(void)
static inline unsigned int read_feat_hcx_id_field(void)
{
return (read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_HCX_SHIFT) &
ID_AA64MMFR1_EL1_HCX_MASK;
return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_HCX);
}
static inline bool is_feat_hcx_supported(void)
@ -268,10 +268,22 @@ static inline bool is_armv8_4_feat_dit_present(void)
/*************************************************************************
* Function to identify the presence of FEAT_TRF (TraceLift)
************************************************************************/
static inline bool is_arm8_4_feat_trf_present(void)
static inline unsigned int read_feat_trf_id_field(void)
{
return (((read_id_aa64dfr0_el1() >> ID_AA64DFR0_TRACEFILT_SHIFT) &
ID_AA64DFR0_TRACEFILT_MASK) == ID_AA64DFR0_TRACEFILT_SUPPORTED);
return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEFILT);
}
static inline bool is_feat_trf_supported(void)
{
if (ENABLE_TRF_FOR_NS == FEAT_STATE_DISABLED) {
return false;
}
if (ENABLE_TRF_FOR_NS == FEAT_STATE_ALWAYS) {
return true;
}
return read_feat_trf_id_field() != 0U;
}
/********************************************************************************
@ -288,19 +300,43 @@ static inline unsigned int get_armv8_4_feat_nv_support(void)
* Function to identify the presence of FEAT_BRBE (Branch Record Buffer
* Extension)
******************************************************************************/
static inline bool is_feat_brbe_present(void)
static inline unsigned int read_feat_brbe_id_field(void)
{
return (((read_id_aa64dfr0_el1() >> ID_AA64DFR0_BRBE_SHIFT) &
ID_AA64DFR0_BRBE_MASK) == ID_AA64DFR0_BRBE_SUPPORTED);
return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_BRBE);
}
static inline bool is_feat_brbe_supported(void)
{
if (ENABLE_BRBE_FOR_NS == FEAT_STATE_DISABLED) {
return false;
}
if (ENABLE_BRBE_FOR_NS == FEAT_STATE_ALWAYS) {
return true;
}
return read_feat_brbe_id_field() != 0U;
}
/*******************************************************************************
* Function to identify the presence of FEAT_TRBE (Trace Buffer Extension)
******************************************************************************/
static inline bool is_feat_trbe_present(void)
static inline unsigned int read_feat_trbe_id_field(void)
{
return (((read_id_aa64dfr0_el1() >> ID_AA64DFR0_TRACEBUFFER_SHIFT) &
ID_AA64DFR0_TRACEBUFFER_MASK) == ID_AA64DFR0_TRACEBUFFER_SUPPORTED);
return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEBUFFER);
}
static inline bool is_feat_trbe_supported(void)
{
if (ENABLE_TRBE_FOR_NS == FEAT_STATE_DISABLED) {
return false;
}
if (ENABLE_TRBE_FOR_NS == FEAT_STATE_ALWAYS) {
return true;
}
return read_feat_trbe_id_field() != 0U;
}
#endif /* ARCH_FEATURES_H */

3
include/arch/aarch64/arch_helpers.h
View file

@ -555,6 +555,9 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1)
/* Armv8.4 Data Independent Timing Register */
DEFINE_RENAME_SYSREG_RW_FUNCS(dit, DIT)
/* Armv8.4 FEAT_TRF Register */
DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el2, TRFCR_EL2)
/* Armv8.5 MTE Registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1)

4
include/lib/el3_runtime/aarch64/context.h
View file

@ -539,10 +539,6 @@ void el2_sysregs_context_restore_ras(el2_sysregs_t *regs);
void el2_sysregs_context_save_nv2(el2_sysregs_t *regs);
void el2_sysregs_context_restore_nv2(el2_sysregs_t *regs);
#endif /* CTX_INCLUDE_NEVE_REGS */
#if ENABLE_TRF_FOR_NS
void el2_sysregs_context_save_trf(el2_sysregs_t *regs);
void el2_sysregs_context_restore_trf(el2_sysregs_t *regs);
#endif /* ENABLE_TRF_FOR_NS */
#if ENABLE_FEAT_CSV2_2
void el2_sysregs_context_save_csv2(el2_sysregs_t *regs);
void el2_sysregs_context_restore_csv2(el2_sysregs_t *regs);

7
lib/el3_runtime/aarch32/context_mgmt.c
View file

@ -11,6 +11,7 @@
#include <platform_def.h>
#include <arch.h>
#include <arch_features.h>
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <context.h>
@ -143,9 +144,9 @@ static void enable_extensions_nonsecure(bool el2_unused)
sys_reg_trace_enable();
#endif /* ENABLE_SYS_REG_TRACE_FOR_NS */
#if ENABLE_TRF_FOR_NS
trf_enable();
#endif /* ENABLE_TRF_FOR_NS */
if (is_feat_trf_supported()) {
trf_enable();
}
#endif
}

24
lib/el3_runtime/aarch64/context.S
View file

@ -41,10 +41,6 @@
.global el2_sysregs_context_save_nv2
.global el2_sysregs_context_restore_nv2
#endif /* CTX_INCLUDE_NEVE_REGS */
#if ENABLE_TRF_FOR_NS
.global el2_sysregs_context_save_trf
.global el2_sysregs_context_restore_trf
#endif /* ENABLE_TRF_FOR_NS */
#if ENABLE_FEAT_CSV2_2
.global el2_sysregs_context_save_csv2
.global el2_sysregs_context_restore_csv2
@ -536,26 +532,6 @@ func el2_sysregs_context_restore_nv2
endfunc el2_sysregs_context_restore_nv2
#endif /* CTX_INCLUDE_NEVE_REGS */
#if ENABLE_TRF_FOR_NS
func el2_sysregs_context_save_trf
/*
* TRFCR_EL2 register is saved only when FEAT_TRF is supported.
*/
mrs x12, TRFCR_EL2
str x12, [x0, #CTX_TRFCR_EL2]
ret
endfunc el2_sysregs_context_save_trf
func el2_sysregs_context_restore_trf
/*
* TRFCR_EL2 register is restored only when FEAT_TRF is supported.
*/
ldr x12, [x0, #CTX_TRFCR_EL2]
msr TRFCR_EL2, x12
ret
endfunc el2_sysregs_context_restore_trf
#endif /* ENABLE_TRF_FOR_NS */
#if ENABLE_FEAT_CSV2_2
func el2_sysregs_context_save_csv2
/*

70
lib/el3_runtime/aarch64/context_mgmt.c
View file

@ -495,21 +495,21 @@ static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx)
mpam_enable(el2_unused);
#endif
#if ENABLE_TRBE_FOR_NS
trbe_enable();
#endif /* ENABLE_TRBE_FOR_NS */
if (is_feat_trbe_supported()) {
trbe_enable();
}
#if ENABLE_BRBE_FOR_NS
brbe_enable();
#endif /* ENABLE_BRBE_FOR_NS */
if (is_feat_brbe_supported()) {
brbe_enable();
}
#if ENABLE_SYS_REG_TRACE_FOR_NS
sys_reg_trace_enable(ctx);
#endif /* ENABLE_SYS_REG_TRACE_FOR_NS */
#if ENABLE_TRF_FOR_NS
trf_enable();
#endif /* ENABLE_TRF_FOR_NS */
if (is_feat_trf_supported()) {
trf_enable();
}
#endif
}
@ -805,30 +805,26 @@ void cm_prepare_el3_exit(uint32_t security_state)
static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx)
{
if (is_feat_fgt_supported()) {
write_ctx_reg(ctx, CTX_HDFGRTR_EL2, read_hdfgrtr_el2());
if (is_feat_amu_supported()) {
write_ctx_reg(ctx, CTX_HAFGRTR_EL2, read_hafgrtr_el2());
}
write_ctx_reg(ctx, CTX_HDFGWTR_EL2, read_hdfgwtr_el2());
write_ctx_reg(ctx, CTX_HFGITR_EL2, read_hfgitr_el2());
write_ctx_reg(ctx, CTX_HFGRTR_EL2, read_hfgrtr_el2());
write_ctx_reg(ctx, CTX_HFGWTR_EL2, read_hfgwtr_el2());
write_ctx_reg(ctx, CTX_HDFGRTR_EL2, read_hdfgrtr_el2());
if (is_feat_amu_supported()) {
write_ctx_reg(ctx, CTX_HAFGRTR_EL2, read_hafgrtr_el2());
}
write_ctx_reg(ctx, CTX_HDFGWTR_EL2, read_hdfgwtr_el2());
write_ctx_reg(ctx, CTX_HFGITR_EL2, read_hfgitr_el2());
write_ctx_reg(ctx, CTX_HFGRTR_EL2, read_hfgrtr_el2());
write_ctx_reg(ctx, CTX_HFGWTR_EL2, read_hfgwtr_el2());
}
static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx)
{
if (is_feat_fgt_supported()) {
write_hdfgrtr_el2(read_ctx_reg(ctx, CTX_HDFGRTR_EL2));
if (is_feat_amu_supported()) {
write_hafgrtr_el2(read_ctx_reg(ctx, CTX_HAFGRTR_EL2));
}
write_hdfgwtr_el2(read_ctx_reg(ctx, CTX_HDFGWTR_EL2));
write_hfgitr_el2(read_ctx_reg(ctx, CTX_HFGITR_EL2));
write_hfgrtr_el2(read_ctx_reg(ctx, CTX_HFGRTR_EL2));
write_hfgwtr_el2(read_ctx_reg(ctx, CTX_HFGWTR_EL2));
write_hdfgrtr_el2(read_ctx_reg(ctx, CTX_HDFGRTR_EL2));
if (is_feat_amu_supported()) {
write_hafgrtr_el2(read_ctx_reg(ctx, CTX_HAFGRTR_EL2));
}
write_hdfgwtr_el2(read_ctx_reg(ctx, CTX_HDFGWTR_EL2));
write_hfgitr_el2(read_ctx_reg(ctx, CTX_HFGITR_EL2));
write_hfgrtr_el2(read_ctx_reg(ctx, CTX_HFGRTR_EL2));
write_hfgwtr_el2(read_ctx_reg(ctx, CTX_HFGWTR_EL2));
}
/*******************************************************************************
@ -863,7 +859,9 @@ void cm_el2_sysregs_context_save(uint32_t security_state)
el2_sysregs_context_save_mpam(el2_sysregs_ctx);
#endif
el2_sysregs_context_save_fgt(el2_sysregs_ctx);
if (is_feat_fgt_supported()) {
el2_sysregs_context_save_fgt(el2_sysregs_ctx);
}
#if ENABLE_FEAT_ECV
el2_sysregs_context_save_ecv(el2_sysregs_ctx);
@ -877,9 +875,9 @@ void cm_el2_sysregs_context_save(uint32_t security_state)
#if CTX_INCLUDE_NEVE_REGS
el2_sysregs_context_save_nv2(el2_sysregs_ctx);
#endif
#if ENABLE_TRF_FOR_NS
el2_sysregs_context_save_trf(el2_sysregs_ctx);
#endif
if (is_feat_trf_supported()) {
write_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2, read_trfcr_el2());
}
#if ENABLE_FEAT_CSV2_2
el2_sysregs_context_save_csv2(el2_sysregs_ctx);
#endif
@ -921,7 +919,9 @@ void cm_el2_sysregs_context_restore(uint32_t security_state)
el2_sysregs_context_restore_mpam(el2_sysregs_ctx);
#endif
el2_sysregs_context_restore_fgt(el2_sysregs_ctx);
if (is_feat_fgt_supported()) {
el2_sysregs_context_restore_fgt(el2_sysregs_ctx);
}
#if ENABLE_FEAT_ECV
el2_sysregs_context_restore_ecv(el2_sysregs_ctx);
@ -935,9 +935,9 @@ void cm_el2_sysregs_context_restore(uint32_t security_state)
#if CTX_INCLUDE_NEVE_REGS
el2_sysregs_context_restore_nv2(el2_sysregs_ctx);
#endif
#if ENABLE_TRF_FOR_NS
el2_sysregs_context_restore_trf(el2_sysregs_ctx);
#endif
if (is_feat_trf_supported()) {
write_trfcr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2));
}
#if ENABLE_FEAT_CSV2_2
el2_sysregs_context_restore_csv2(el2_sysregs_ctx);
#endif

22
lib/extensions/brbe/brbe.c
View file

@ -12,16 +12,14 @@ void brbe_enable(void)
{
uint64_t val;
if (is_feat_brbe_present()) {
/*
* MDCR_EL3.SBRBE = 0b01
*
* Allows BRBE usage in non-secure world and prohibited in
* secure world.
*/
val = read_mdcr_el3();
val &= ~(MDCR_SBRBE_MASK << MDCR_SBRBE_SHIFT);
val |= (0x1UL << MDCR_SBRBE_SHIFT);
write_mdcr_el3(val);
}
/*
* MDCR_EL3.SBRBE = 0b01
*
* Allows BRBE usage in non-secure world and prohibited in
* secure world.
*/
val = read_mdcr_el3();
val &= ~(MDCR_SBRBE_MASK << MDCR_SBRBE_SHIFT);
val |= (0x1UL << MDCR_SBRBE_SHIFT);
write_mdcr_el3(val);
}

22
lib/extensions/trbe/trbe.c
View file

@ -23,22 +23,20 @@ void trbe_enable(void)
{
uint64_t val;
if (is_feat_trbe_present()) {
/*
* MDCR_EL3.NSTB = 0b11
* Allow access of trace buffer control registers from NS-EL1
* and NS-EL2, tracing is prohibited in Secure and Realm state
* (if implemented).
*/
val = read_mdcr_el3();
val |= MDCR_NSTB(MDCR_NSTB_EL1);
write_mdcr_el3(val);
}
/*
* MDCR_EL3.NSTB = 0b11
* Allow access of trace buffer control registers from NS-EL1
* and NS-EL2, tracing is prohibited in Secure and Realm state
* (if implemented).
*/
val = read_mdcr_el3();
val |= MDCR_NSTB(MDCR_NSTB_EL1);
write_mdcr_el3(val);
}
static void *trbe_drain_trace_buffers_hook(const void *arg __unused)
{
if (is_feat_trbe_present()) {
if (is_feat_trbe_supported()) {
/*
* Before switching from normal world to secure world
* the trace buffers need to be drained out to memory. This is

25
lib/extensions/trf/aarch32/trf.c
View file

@ -10,26 +10,15 @@
#include <arch_helpers.h>
#include <lib/extensions/trf.h>
static bool trf_supported(void)
{
uint32_t features;
features = read_id_dfr0() >> ID_DFR0_TRACEFILT_SHIFT;
return ((features & ID_DFR0_TRACEFILT_MASK) ==
ID_DFR0_TRACEFILT_SUPPORTED);
}
void trf_enable(void)
{
uint32_t val;
if (trf_supported()) {
/*
* Allow access of trace filter control registers from
* non-monitor mode
*/
val = read_sdcr();
val &= ~SDCR_TTRF_BIT;
write_sdcr(val);
}
/*
* Allow access of trace filter control registers from
* non-monitor mode
*/
val = read_sdcr();
val &= ~SDCR_TTRF_BIT;
write_sdcr(val);
}

30
lib/extensions/trf/aarch64/trf.c
View file

@ -4,33 +4,21 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdbool.h>
#include <arch.h>
#include <arch_features.h>
#include <arch_helpers.h>
#include <lib/extensions/trf.h>
static bool trf_supported(void)
{
uint64_t features;
features = read_id_aa64dfr0_el1() >> ID_AA64DFR0_TRACEFILT_SHIFT;
return ((features & ID_AA64DFR0_TRACEFILT_MASK) ==
ID_AA64DFR0_TRACEFILT_SUPPORTED);
}
void trf_enable(void)
{
uint64_t val;
if (trf_supported()) {
/*
* MDCR_EL3.TTRF = b0
* Allow access of trace filter control registers from NS-EL2
* and NS-EL1 when NS-EL2 is implemented but not used
*/
val = read_mdcr_el3();
val &= ~MDCR_TTRF_BIT;
write_mdcr_el3(val);
}
/*
* MDCR_EL3.TTRF = b0
* Allow access of trace filter control registers from NS-EL2
* and NS-EL1 when NS-EL2 is implemented but not used
*/
val = read_mdcr_el3();
val &= ~MDCR_TTRF_BIT;
write_mdcr_el3(val);
}

6
plat/arm/board/fvp/platform.mk
View file

@ -446,14 +446,14 @@ DYN_DISABLE_AUTH := 1
endif
# enable trace buffer control registers access to NS by default
ENABLE_TRBE_FOR_NS := 1
ENABLE_TRBE_FOR_NS := 2
# enable branch record buffer control registers access in NS by default
# only enable for aarch64
# do not enable when ENABLE_RME=1
ifeq (${ARCH}, aarch64)
ifeq (${ENABLE_RME},0)
ENABLE_BRBE_FOR_NS := 1
ENABLE_BRBE_FOR_NS := 2
endif
endif
@ -461,7 +461,7 @@ endif
ENABLE_SYS_REG_TRACE_FOR_NS := 1
# enable trace filter control registers access to NS by default
ENABLE_TRF_FOR_NS := 1
ENABLE_TRF_FOR_NS := 2
# Linux relies on EL3 enablement if those features are present
ENABLE_FEAT_FGT := 2