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plat/sgi: define default list of memory regions for dmc620 tzc

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Define a default DMC-620 TZC memory region configuration and use it to
specify the TZC memory regions on sgi575, rdn1edge and rde1edge
platforms. The default DMC-620 TZC memory regions are defined
considering the support for secure paritition as well.

Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: Iedee3e57d0d3de5b65321444da51ec990d3702db
This commit is contained in:
Thomas Abraham 2021-02-16 14:22:41 +05:30
parent d306eb801e
commit b4d548f141
4 changed files with 45 additions and 22 deletions
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10
plat/arm/board/rde1edge/rde1edge_security.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, Arm Limited. All rights reserved.
* Copyright (c) 2019-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,7 +7,7 @@
#include <platform_def.h>
#include <common/debug.h>
#include <drivers/arm/tzc_dmc620.h>
#include <sgi_dmc620_tzc_regions.h>
uintptr_t rde1edge_dmc_base[] = {
RDE1EDGE_DMC620_BASE0,
@ -20,11 +20,7 @@ static const tzc_dmc620_driver_data_t rde1edge_plat_driver_data = {
};
static const tzc_dmc620_acc_addr_data_t rde1edge_acc_addr_data[] = {
{
.region_base = ARM_AP_TZC_DRAM1_BASE,
.region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
.sec_attr = TZC_DMC620_REGION_S_RDWR
}
CSS_SGI_DMC620_TZC_REGIONS_DEF
};
static const tzc_dmc620_config_data_t rde1edge_plat_config_data = {

10
plat/arm/board/rdn1edge/rdn1edge_security.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, ARM Limited. All rights reserved.
* Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,7 +7,7 @@
#include <platform_def.h>
#include <common/debug.h>
#include <drivers/arm/tzc_dmc620.h>
#include <sgi_dmc620_tzc_regions.h>
uintptr_t rdn1edge_dmc_base[] = {
RDN1EDGE_DMC620_BASE0,
@ -20,11 +20,7 @@ static const tzc_dmc620_driver_data_t rdn1edge_plat_driver_data = {
};
static const tzc_dmc620_acc_addr_data_t rdn1edge_acc_addr_data[] = {
{
.region_base = ARM_AP_TZC_DRAM1_BASE,
.region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
.sec_attr = TZC_DMC620_REGION_S_RDWR
}
CSS_SGI_DMC620_TZC_REGIONS_DEF
};
static const tzc_dmc620_config_data_t rdn1edge_plat_config_data = {

11
plat/arm/board/sgi575/sgi575_security.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,8 +7,7 @@
#include <platform_def.h>
#include <common/debug.h>
#include <drivers/arm/tzc_dmc620.h>
#include <plat/arm/common/plat_arm.h>
#include <sgi_dmc620_tzc_regions.h>
uintptr_t sgi575_dmc_base[] = {
SGI575_DMC620_BASE0,
@ -21,11 +20,7 @@ static const tzc_dmc620_driver_data_t sgi575_plat_driver_data = {
};
static const tzc_dmc620_acc_addr_data_t sgi575_acc_addr_data[] = {
{
.region_base = ARM_AP_TZC_DRAM1_BASE,
.region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
.sec_attr = TZC_DMC620_REGION_S_RDWR
}
CSS_SGI_DMC620_TZC_REGIONS_DEF
};
static const tzc_dmc620_config_data_t sgi575_plat_config_data = {

36
plat/arm/css/sgi/include/sgi_dmc620_tzc_regions.h Normal file
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@ -0,0 +1,36 @@
/*
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SGI_DMC620_TZC_REGIONS_H
#define SGI_DMC620_TZC_REGIONS_H
#include <drivers/arm/tzc_dmc620.h>
#if SPM_MM
#define CSS_SGI_DMC620_TZC_REGIONS_DEF \
{ \
.region_base = ARM_AP_TZC_DRAM1_BASE, \
.region_top = PLAT_SP_IMAGE_NS_BUF_BASE - 1, \
.sec_attr = TZC_DMC620_REGION_S_RDWR \
}, { \
.region_base = PLAT_SP_IMAGE_NS_BUF_BASE, \
.region_top = PLAT_ARM_SP_IMAGE_STACK_BASE - 1, \
.sec_attr = TZC_DMC620_REGION_S_NS_RDWR \
}, { \
.region_base = PLAT_ARM_SP_IMAGE_STACK_BASE, \
.region_top = ARM_AP_TZC_DRAM1_END, \
.sec_attr = TZC_DMC620_REGION_S_RDWR \
}
#else
#define CSS_SGI_DMC620_TZC_REGIONS_DEF \
{ \
.region_base = ARM_AP_TZC_DRAM1_BASE, \
.region_top = ARM_AP_TZC_DRAM1_END, \
.sec_attr = TZC_DMC620_REGION_S_RDWR \
}
#endif /* SPM_MM */
#endif /* SGI_DMC620_TZC_REGIONS_H */